From 9a0bf54840d09ef38d8040a5440d2a9bfa4f1c8e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Nov 2021 11:26:08 -0600
Subject: [PATCH] Created tcl scripts to build 2 of the 4 xilinx IP.

---
 fpga/generator/ahblite_axi_bridge.tcl  | 20 ++++++++++++++++++++
 fpga/generator/axi_clock_converter.tcl | 20 ++++++++++++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 fpga/generator/ahblite_axi_bridge.tcl
 create mode 100644 fpga/generator/axi_clock_converter.tcl

diff --git a/fpga/generator/ahblite_axi_bridge.tcl b/fpga/generator/ahblite_axi_bridge.tcl
new file mode 100644
index 000000000..ab3839820
--- /dev/null
+++ b/fpga/generator/ahblite_axi_bridge.tcl
@@ -0,0 +1,20 @@
+
+#set partNumber $::env(XILINX_PART)
+#set boardNmae $::env(XILINX_BOARD)
+set partNumber xcvu9p-flga2104-2L-e
+set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName xlnx_ahblite_axi_bridge
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+# really just these two lines which change
+create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C_M_AXI_DATA_WIDTH {64} CONFIG.C_S_AHB_DATA_WIDTH {64} CONFIG.C_M_AXI_THREAD_ID_WIDTH {4}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
diff --git a/fpga/generator/axi_clock_converter.tcl b/fpga/generator/axi_clock_converter.tcl
new file mode 100644
index 000000000..ed038bf49
--- /dev/null
+++ b/fpga/generator/axi_clock_converter.tcl
@@ -0,0 +1,20 @@
+
+#set partNumber $::env(XILINX_PART)
+#set boardNmae $::env(XILINX_BOARD)
+set partNumber xcvu9p-flga2104-2L-e
+set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName xlnx_axi_clock_converter
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
+
+set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {31} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1