diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv
index 0f4cb732c..3e0cf82a1 100644
--- a/pipelined/src/fpu/fclassify.sv
+++ b/pipelined/src/fpu/fclassify.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: classify unit
+// Purpose: Floating-point classify unit
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv
index aa1a20d1a..2c2b5d343 100755
--- a/pipelined/src/fpu/fcmp.sv
+++ b/pipelined/src/fpu/fcmp.sv
@@ -5,7 +5,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Comparison unit
+// Purpose: Floating-point comparison unit
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv
index c968f2251..66602d04f 100755
--- a/pipelined/src/fpu/fctrl.sv
+++ b/pipelined/src/fpu/fctrl.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: control unit
+// Purpose: floating-point control unit
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv
index ce4e6bd22..bf6ce6712 100644
--- a/pipelined/src/fpu/fregfile.sv
+++ b/pipelined/src/fpu/fregfile.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: James Stine 
 //
-// Purpose: 3-port output register file
+// Purpose: 3R1W 4-port register file for FPU
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index 14328750d..cab267f5f 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Conversion shift calculation
+// Purpose: Division shift calculation
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv
index 41cbc2117..1e7034314 100644
--- a/pipelined/src/fpu/postproc/fmashiftcalc.sv
+++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Fma shift calculation
+// Purpose: FMA shift calculation
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv
index 8ef1b5c4e..faeba4b92 100644
--- a/pipelined/src/fpu/postproc/negateintres.sv
+++ b/pipelined/src/fpu/postproc/negateintres.sv
@@ -35,16 +35,12 @@ module negateintres(
     output logic [`XLEN+1:0]    CvtNegRes
 );
 
+    logic [2:0] CvtNegResMsbs3;
     
     // round and negate the positive res if needed
     assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
     
-    always_comb
-        if(Signed)
-            if(Int64)   CvtNegResMsbs = CvtNegRes[`XLEN:`XLEN-1];
-            else        CvtNegResMsbs = CvtNegRes[32:31];
-        else
-            if(Int64)   CvtNegResMsbs = CvtNegRes[`XLEN+1:`XLEN];
-            else        CvtNegResMsbs = CvtNegRes[33:32];
-
+    // select 2 most significant bits
+    mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
+    mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegRes[1:0], Signed, CvtNegResMsbs);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv
index 5f50f873e..59023ef59 100644
--- a/pipelined/src/fpu/unpack.sv
+++ b/pipelined/src/fpu/unpack.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: unpack all inputs
+// Purpose: unpack X, Y, Z floating-point inputs
 // 
 // A component of the Wally configurable RISC-V project.
 // 
diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv
index 3e4efb443..179e5d543 100644
--- a/pipelined/src/fpu/unpackinput.sv
+++ b/pipelined/src/fpu/unpackinput.sv
@@ -4,7 +4,7 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: unpack input
+// Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
 // A component of the Wally configurable RISC-V project.
 //