From 99f72b627ddcf56e9e61175b07d937135472b73b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 28 Aug 2024 13:12:39 -0700 Subject: [PATCH] port works, just need to add extra derived configs for k=8 --- bin/regression-wally-intdiv | 34 +- src/fpu/divremsqrt/divremsqrt.sv | 5 +- src/fpu/divremsqrt/divremsqrtearlyterm.sv | 2 +- .../divremsqrt/divremsqrtfdivsqrtpostproc.sv | 4 +- testbench/testbench_fp.sv | 1242 ++++++++++------- testbench/tests-fp.vh | 639 +++++++++ 6 files changed, 1442 insertions(+), 484 deletions(-) create mode 100644 testbench/tests-fp.vh diff --git a/bin/regression-wally-intdiv b/bin/regression-wally-intdiv index 5efe0dc24..5408e8661 100755 --- a/bin/regression-wally-intdiv +++ b/bin/regression-wally-intdiv @@ -27,7 +27,9 @@ class bcolors: UNDERLINE = '\033[4m' from collections import namedtuple -regressionDir = os.path.dirname(os.path.abspath(__file__)) + +WALLY = os.environ.get('WALLY') +regressionDir = WALLY + '/sim' os.chdir(regressionDir) coverage = '-coverage' in sys.argv @@ -309,6 +311,7 @@ if (nightly): # softfloat tests if (softfloat): + testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved configs = [] softfloatconfigs = [ "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc", @@ -381,6 +384,7 @@ if (softfloat): # intdiv verification if (intdiv): configs = [] + testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved # ***NOTE add to this intdivconfigs = [ @@ -441,29 +445,38 @@ if (intdiv): "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc", "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc" ] - for config in intdivconfigs: # fdivremsqrt test case + name = "div_drsu" + logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log" fdivremsqrttestcase = TestCase( - name="fdivremsqrt", + name=name, variant=config, - cmd="vsim > {} -c < " + logname, grepstr="All Tests completed with 0 errors" ) configs.insert(0,fdivremsqrttestcase) for config in nointdivconfigs: # div,sqrt test cases for no integer flavor of divider + + name = "div_drsu" + logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log" divtestcase = TestCase( - name="fdiv", + name=name, variant=config, - cmd="vsim > {} -c < {} -c < " + logname, grepstr="All Tests completed with 0 errors" ) configs.insert(0,divtestcase) + + name = "sqrt_drsu" + logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log" sqrttestcase = TestCase( - name="fsqrt", + name=name, variant=config, - cmd="vsim > {} -c < {} -c < " + logname, grepstr="All Tests completed with 0 errors" ) configs.insert(0,sqrttestcase) @@ -477,8 +490,11 @@ def search_log_for_text(text, logfile): return os.system(grepcmd) == 0 def run_test_case(config): + testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" - logname = "logs/"+config.variant+"_"+config.name+".log" + #sim_logdir = WALLY+ "/sim/" + sim + "/logs/" + logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config.variant+"_"+config.name+".log" + #logname = "logs/"+config.variant+"_"+config.name+".log" cmd = config.cmd.format(logname) # print(cmd) os.chdir(regressionDir) diff --git a/src/fpu/divremsqrt/divremsqrt.sv b/src/fpu/divremsqrt/divremsqrt.sv index f57a3f8dd..c21267070 100644 --- a/src/fpu/divremsqrt/divremsqrt.sv +++ b/src/fpu/divremsqrt/divremsqrt.sv @@ -65,7 +65,6 @@ logic [P.DIVb+3:0] D; // Iterator Divisor logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values logic [P.DIVb+1:0] FirstC; // Step tracker - logic Firstun; // Quotient selection logic WZeroE; // Early termination flag logic [P.DURLEN:0] CyclesE; // FSM cycles logic SpecialCaseM; // Divide by zero, square root of negative, etc. @@ -96,11 +95,11 @@ fdivsqrtiter #(P) fdivsqrtiter( // CSA Iterator .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, - .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC)); + .FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC)); divremsqrtfdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, - .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, + .SqrtE, .SqrtM, .SpecialCaseM, .UmM, .WZeroE, .DivStickyM, // Int-specific .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, diff --git a/src/fpu/divremsqrt/divremsqrtearlyterm.sv b/src/fpu/divremsqrt/divremsqrtearlyterm.sv index 3d9715ed4..464dfdafa 100644 --- a/src/fpu/divremsqrt/divremsqrtearlyterm.sv +++ b/src/fpu/divremsqrt/divremsqrtearlyterm.sv @@ -3,7 +3,7 @@ module divremsqrtearlyterm import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb+3:0] D, // Q4.DIVb input logic [P.DIVb:0] FirstUM, // U1.DIVb input logic [P.DIVb+1:0] FirstC, // Q2.DIVb - input logic Firstun, SqrtE, + input logic SqrtE, output logic WZeroE ); logic weq0E; diff --git a/src/fpu/divremsqrt/divremsqrtfdivsqrtpostproc.sv b/src/fpu/divremsqrt/divremsqrtfdivsqrtpostproc.sv index e1c152227..87b2ccd0b 100644 --- a/src/fpu/divremsqrt/divremsqrtfdivsqrtpostproc.sv +++ b/src/fpu/divremsqrt/divremsqrtfdivsqrtpostproc.sv @@ -35,7 +35,7 @@ module divremsqrtfdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb:0] FirstU, FirstUM, // U1.DIVb input logic [P.DIVb+1:0] FirstC, // Q2.DIVb input logic SqrtE, - input logic Firstun, SqrtM, SpecialCaseM, + input logic SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0) input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, SIGNOVERFLOWM, ZeroDiffM, IntDivM, input logic [P.DIVBLEN-1:0] IntNormShiftM, @@ -61,7 +61,7 @@ module divremsqrtfdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( ////////////////////////// // check for early termination on an exact result. - divremsqrtearlyterm #(P) earlyterm(.FirstC, .FirstUM, .D, .SqrtE, .WC, .WS,.Firstun, .WZeroE); + divremsqrtearlyterm #(P) earlyterm(.FirstC, .FirstUM, .D, .SqrtE, .WC, .WS, .WZeroE); ////////////////////////// diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 61fa12fcc..1617d392c 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -23,26 +23,28 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "config.vh" -`include "tests_fp.vh" +`include "tests-fp.vh" import cvw::*; module testbench_fp; // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir // to run specific precisions (e.g., quad or all) - parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly - parameter string TEST_SIZE="all"; + parameter TEST="none"; + parameter TEST_SIZE="none"; `include "parameter-defs.vh" - parameter MAXVECTORS = 8388610; + //parameter MAXVECTORS = 8388610; + parameter MAXVECTORS = 100000; // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run - logic [2:0] OpCtrl[]; // list of op controls + logic [3:0] OpCtrl[]; // list of op controls logic [2:0] Unit[]; // list of units being tested logic WriteInt[]; // Is being written to integer resgiter logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 + //logic [2:0] Frm[4:0] = {3'b011, 3'b011, 3'b011, 3'b011, 3'b011}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 *** MODIFIED ROUNDING MODES logic [1:0] Fmt[]; // list of formats for the other units logic clk=0; @@ -51,22 +53,23 @@ module testbench_fp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors + logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt - logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal + logic [2:0] UnitVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal + logic [3:0] OpCtrlVal; logic WriteIntVal; // value of the current WriteInt - logic [P.Q_LEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [P.FLEN-1:0] X, Y, Z; // inputs read from TestFloat logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat - logic [P.XLEN-1:0] SrcA; // integer input - logic [P.Q_LEN-1:0] Ans; // correct answer from TestFloat - logic [P.Q_LEN-1:0] Res; // result from other units + logic [P.XLEN-1:0] SrcA, SrcB; // integer input + logic W64; // is W64 instruction + logic [P.FLEN-1:0] Ans; // correct answer from TestFloat + logic [P.FLEN-1:0] Res; // result from other units logic [4:0] AnsFlg; // correct flags read from testfloat logic [4:0] ResFlg, Flg; // Result flags logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit - logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags logic [4:0] CmpFlg; // Outputed flags logic AnsNaN, ResNaN, NaNGood; @@ -99,8 +102,8 @@ module testbench_fp; logic [P.NE+1:0] Se; logic ASticky; logic KillProd; - logic [$clog2(P.FMALEN+1)-1:0] SCnt; - logic [P.FMALEN-1:0] Sm; + logic [$clog2(3*P.NF+5)-1:0] SCnt; + logic [3*P.NF+3:0] Sm; logic InvA; logic NegSum; logic As; @@ -116,6 +119,7 @@ module testbench_fp; logic [2:0] Funct3M; logic FlushE; logic IFDivStartE; + logic IDivStart; logic FDivDoneE; logic [P.NE+1:0] UeM; logic [P.DIVb:0] UmM; @@ -124,9 +128,7 @@ module testbench_fp; logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check logic FMAop; // Is this a FMA operation? - - logic [P.NE-2:0] BiasE; // Bias of exponent - logic [P.LOGFLEN-1:0] NfE; // Number of fractional bits + logic IntDivE; // Is Integer operation on FPU? // FSM for testing each item per clock typedef enum logic [2:0] {S0, Start, S2, Done} statetype; @@ -150,16 +152,16 @@ module testbench_fp; // sub - test subtraction // div - test division // sqrt - test square root - // all - test all of the above < doesn't report errors properly > - + // all - test all of the above + flopen #(3) funct3reg(.clk, .en(IFDivStartE), .d(Funct3E), .q(Funct3M)); + initial begin // Information displayed for user on what is simulating // $display("\nThe start of simulation..."); + $display("\nThe start of simulation... INTDIVb: %d, DIVB: %d, DIVBLEN: %d , RK: %d",INTDIVb, DIVb, DIVBLEN, RK); // $display("This simulation for TEST is %s", TEST); - // $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); - - if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported - if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion + if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported + if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion // add the 128-bit cvtint tests to the to-be-tested list Tests = {Tests, f128rv32cvtint}; // add the op-codes for these tests to the op-code list @@ -177,13 +179,13 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b11}; + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; end end - end - // if the floating-point conversions are being tested - if (TEST === "cvtfp" | TEST === "all") begin + end + // if the floating-point conversions are being tested + if (TEST === "cvtfp" | TEST === "all") begin if (P.D_SUPPORTED) begin // if double precision is supported // add the 128 <-> 64 bit conversions to the to-be-tested list Tests = {Tests, f128f64cvt}; @@ -192,12 +194,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; end end if (P.F_SUPPORTED) begin // if single precision is supported @@ -208,12 +210,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; end end if (P.ZFH_SUPPORTED) begin // if half precision is supported @@ -224,16 +226,16 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; end end - end - if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested + end + if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested // add the compare tests/op-ctrls/unit/fmt Tests = {Tests, f128cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -242,8 +244,8 @@ module testbench_fp; Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested // add the addition tests/op-ctrls/unit/fmt Tests = {Tests, f128add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; @@ -252,8 +254,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested // add the subtraction tests/op-ctrls/unit/fmt Tests = {Tests, f128sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; @@ -262,8 +264,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested // add the multiply tests/op-ctrls/unit/fmt Tests = {Tests, f128mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; @@ -272,8 +274,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested + end + if (TEST === "div" | TEST === "all") begin // if division is being tested // add the divide tests/op-ctrls/unit/fmt Tests = {Tests, f128div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; @@ -282,8 +284,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested // add the square-root tests/op-ctrls/unit/fmt Tests = {Tests, f128sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; @@ -292,8 +294,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b11}; end - end - if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested + end + if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested Tests = {Tests, f128fma}; OpCtrl = {OpCtrl, `FMA_OPCTRL}; WriteInt = {WriteInt, 1'b0}; @@ -301,10 +303,10 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b11}; end - end + end end if (P.D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported - if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested + if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested Tests = {Tests, f64rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; @@ -321,12 +323,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b01}; + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; end end - end - if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested if (P.F_SUPPORTED) begin // if single precision is supported // add the 64 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f64f32cvt}; @@ -335,12 +337,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; end end if (P.ZFH_SUPPORTED) begin // if half precision is supported @@ -351,16 +353,16 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; end end - end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -369,8 +371,8 @@ module testbench_fp; Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; @@ -379,8 +381,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; @@ -389,8 +391,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; @@ -399,8 +401,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested + end + if (TEST === "div" | TEST === "all") begin // if division is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; @@ -409,8 +411,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f64sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; @@ -419,8 +421,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b01}; end - end - if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested + end + if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested Tests = {Tests, f64fma}; OpCtrl = {OpCtrl, `FMA_OPCTRL}; WriteInt = {WriteInt, 1'b0}; @@ -428,10 +430,10 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b01}; end - end + end end if (P.F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported - if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested Tests = {Tests, f32rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; @@ -448,12 +450,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b00}; + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; end end - end - if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested if (P.ZFH_SUPPORTED) begin // add the 32 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f32f16cvt}; @@ -462,16 +464,16 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0}; // add the unit being tested and fmt (input format) for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; end for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; end end - end - if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + end + if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -480,8 +482,8 @@ module testbench_fp; Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; @@ -490,8 +492,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; @@ -500,8 +502,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "mul" | TEST === "all") begin // if multiply is being tested + end + if (TEST === "mul" | TEST === "all") begin // if multiply is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; @@ -510,8 +512,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested + end + if (TEST === "div" | TEST === "all") begin // if division is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; @@ -520,8 +522,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f32sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; @@ -530,8 +532,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b00}; end - end - if (TEST === "fma" | TEST === "all") begin // if fma is being tested + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested Tests = {Tests, f32fma}; OpCtrl = {OpCtrl, `FMA_OPCTRL}; WriteInt = {WriteInt, 1'b0}; @@ -539,10 +541,10 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b00}; end - end + end end if (P.ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported - if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested + if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested Tests = {Tests, f16rv32cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; @@ -559,12 +561,12 @@ module testbench_fp; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b10}; + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; end end - end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16cmp}; OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; @@ -573,8 +575,8 @@ module testbench_fp; Unit = {Unit, `CMPUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16add}; OpCtrl = {OpCtrl, `ADD_OPCTRL}; @@ -583,8 +585,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16sub}; OpCtrl = {OpCtrl, `SUB_OPCTRL}; @@ -593,8 +595,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16mul}; OpCtrl = {OpCtrl, `MUL_OPCTRL}; @@ -603,8 +605,8 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested + end + if (TEST === "div" | TEST === "all") begin // if division is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16div}; OpCtrl = {OpCtrl, `DIV_OPCTRL}; @@ -613,8 +615,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested // add the correct tests/op-ctrls/unit/fmt to their lists Tests = {Tests, f16sqrt}; OpCtrl = {OpCtrl, `SQRT_OPCTRL}; @@ -623,8 +625,8 @@ module testbench_fp; Unit = {Unit, `DIVUNIT}; Fmt = {Fmt, 2'b10}; end - end - if (TEST === "fma" | TEST === "all") begin // if fma is being tested + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested Tests = {Tests, f16fma}; OpCtrl = {OpCtrl, `FMA_OPCTRL}; WriteInt = {WriteInt, 1'b0}; @@ -632,12 +634,194 @@ module testbench_fp; Unit = {Unit, `FMAUNIT}; Fmt = {Fmt, 2'b10}; end - end + end + end + if (P.IDIV_ON_FPU |1'b1) begin + if (P.Q_SUPPORTED) begin + if (TEST === "fdivremsqrt" | TEST === "div_drsu") begin // if division on drsu is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f128div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "fdivremsqrt" | TEST === "sqrt_drsu") begin // if square-root on drsu is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f128sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (P.D_SUPPORTED) begin + if (TEST === "fdivremsqrt" | TEST === "div_drsu") begin // if division on drsu is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f64div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "fdivremsqrt" | TEST === "sqrt_drsu") begin // if square-root on drsu is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f64sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (P.S_SUPPORTED) begin + if (TEST === "fdivremsqrt" | TEST === "div_drsu") begin // if division on drsu is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f32div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "fdivremsqrt" | TEST === "sqrt_drsu") begin // if square-root on drsu is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f32sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + + end + if (P.ZFH_SUPPORTED) begin + if (TEST === "fdivremsqrt" | TEST === "div_drsu") begin // if division on drsu is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f16div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "fdivremsqrt" | TEST === "sqrt_drsu") begin // if square-root on drsu is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f16sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (P.XLEN == 64 & P.IDIV_ON_FPU) begin + if (TEST === "intrem" | TEST === "intdivrem" | TEST === "fdivremsqrt") begin // if integer remainder is being tested + Tests = {Tests, int64rem}; + OpCtrl = {OpCtrl, `INTREM_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdiv" | TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if integer division is being tested + Tests = {Tests, int64div}; + OpCtrl = {OpCtrl, `INTDIV_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intremu"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned integer remainder is being tested + Tests = {Tests, int64remu}; + OpCtrl = {OpCtrl, `INTREMU_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdivu"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned integer division is being tested + Tests = {Tests, int64divu}; + OpCtrl = {OpCtrl, `INTDIVU_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intremw"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if w-type integer remainder is being tested + Tests = {Tests, int64remw}; + OpCtrl = {OpCtrl, `INTREMW_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intremuw"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned w-type integer remainder is being tested + Tests = {Tests, int64remuw}; + OpCtrl = {OpCtrl, `INTREMUW_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdivw"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if w-type integer division is being tested + Tests = {Tests, int64divw}; + OpCtrl = {OpCtrl, `INTDIVW_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdivuw"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned w-type integer divison is being tested + Tests = {Tests, int64divuw}; + OpCtrl = {OpCtrl, `INTDIVUW_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + // RV32 + else if (P.IDIV_ON_FPU) begin + if (TEST === "intrem" | TEST === "intdivrem" | TEST === "fdivremsqrt") begin // if integer remainder is being tested + Tests = {Tests, int32rem}; + OpCtrl = {OpCtrl, `INTREM_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdiv" | TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if integer division is being tested + Tests = {Tests, int32div}; + OpCtrl = {OpCtrl, `INTDIV_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intremu"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned integer remainder is being tested + Tests = {Tests, int32remu}; + OpCtrl = {OpCtrl, `INTREMU_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (TEST === "intdivu"| TEST ==="intdivrem" | TEST === "fdivremsqrt") begin // if unsigned integer division is being tested + Tests = {Tests, int32divu}; + OpCtrl = {OpCtrl, `INTDIVU_OPCTRL}; + WriteInt = {WriteInt, 1'b1}; + Unit = {Unit, `INTDIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end end // check if nothing is being tested + + $display("This simulation for TEST contains %d vectors", Tests.size); if (Tests.size() == 0) begin - $display("TEST %s not supported in this configuration", TEST); - $stop; + $display("TEST %s not supported in this configuration", TEST); + $stop; end end @@ -657,18 +841,17 @@ module testbench_fp; static string pp = `PATH; string testname; string tt0; - tt0 = $sformatf("%s", Tests[TestNum]); + tt0 = $psprintf("%s", Tests[TestNum]); testname = {pp, tt0}; //$display("Here you are %s", testname); - // clear the vectors - for(int i=0; i quad - X = {P.Q_LEN{1'bx}}; + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> quad + X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; - end - 2'b10: begin // int -> quad + end + 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.Q_LEN{1'bx}}; + X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; - end - 2'b01: begin // quad -> long + end + 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; - end - 2'b00: begin // quad -> int + Ans = {TestVector[8+(P.XLEN-1):8]}; + end + 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end endcase end 2'b01: if (P.D_SUPPORTED) begin // double // {Int->Fp?, is the integer a long} - casez ({OpCtrl[2:1]}) - 2'b11: begin // long -> double - X = {P.Q_LEN{1'bx}}; + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> double + X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; - Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; - end - 2'b10: begin // int -> double + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + end + 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.Q_LEN{1'bx}}; + X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; - Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; - end - 2'b01: begin // double -> long - X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + end + 2'b01: begin // double -> long + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; - end - 2'b00: begin // double -> int - X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; + Ans = {TestVector[8+(P.XLEN-1):8]}; + end + 2'b00: begin // double -> int + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end endcase end - 2'b00: if (P.F_SUPPORTED) begin // single + 2'b00: if (P.S_SUPPORTED) begin // single // {is the integer a long, is the opperation to an integer} - casez ({OpCtrl[2:1]}) - 2'b11: begin // long -> single - X = {P.Q_LEN{1'bx}}; + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> single + X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; - Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; - end - 2'b10: begin // int -> single + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + end + 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.Q_LEN{1'bx}}; + X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; - Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; - end - 2'b01: begin // single -> long - X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + end + 2'b01: begin // single -> long + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; - end - 2'b00: begin // single -> int - X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; + Ans = {TestVector[8+(P.XLEN-1):8]}; + end + 2'b00: begin // single -> int + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end endcase end 2'b10: begin // half // {is the integer a long, is the opperation to an integer} - casez ({OpCtrl[2:1]}) - 2'b11: begin // long -> half - X = {P.Q_LEN{1'bx}}; + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> half + X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; - Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; - end - 2'b10: begin // int -> half + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + end + 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.Q_LEN{1'bx}}; + X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; - Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; - end - 2'b01: begin // half -> long - X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + end + 2'b01: begin // half -> long + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; - end - 2'b00: begin // half -> int - X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; + Ans = {TestVector[8+(P.XLEN-1):8]}; + end + 2'b00: begin // half -> int + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; - end + Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + end endcase end endcase @@ -1382,13 +1686,13 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); - assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); + assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]) | ((Unit == `INTDIVUNIT) & OpCtrl === `SQRT_OPCTRL)); assign ZEn = (Unit == `FMAUNIT); assign FPUActive = 1'b1; - unpack #(P) unpack(.X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .Z(Z[P.FLEN-1:0]), .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, + unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, - .XEn, .YEn, .ZEn, .XExpMax, .XPostBox, .Bias(BiasE), .Nf(NfE)); + .XEn, .YEn, .ZEn, .XExpMax, .XPostBox); endmodule diff --git a/testbench/tests-fp.vh b/testbench/tests-fp.vh new file mode 100644 index 000000000..64babccd4 --- /dev/null +++ b/testbench/tests-fp.vh @@ -0,0 +1,639 @@ +////////////////////////////////////////// +// tests0fo.vh +// +// Written: Katherine Parry 2022 +// Modified: +// +// Purpose: List of floating-point tests to apply +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-3 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`define PATH "../../tests/fp/vectors/" +`define ADD_OPCTRL 4'b0110 +`define MUL_OPCTRL 4'b0100 +`define SUB_OPCTRL 4'b0111 +`define FMA_OPCTRL 4'b0000 +`define DIV_OPCTRL 4'b0000 +`define SQRT_OPCTRL 4'b0001 +`define LE_OPCTRL 4'b0011 +`define LT_OPCTRL 4'b0001 +`define EQ_OPCTRL 4'b0010 +`define TO_UI_OPCTRL 4'b0000 +`define TO_I_OPCTRL 4'b0001 +`define TO_UL_OPCTRL 4'b0010 +`define TO_L_OPCTRL 4'b0011 +`define FROM_UI_OPCTRL 4'b0100 +`define FROM_I_OPCTRL 4'b0101 +`define FROM_UL_OPCTRL 4'b0110 +`define FROM_L_OPCTRL 4'b0111 +`define INTREMU_OPCTRL 4'b1001 +`define INTREM_OPCTRL 4'b1010 +`define INTDIV_OPCTRL 4'b1011 +`define INTDIVW_OPCTRL 4'b1100 +`define INTDIVU_OPCTRL 4'b1101 +`define INTREMW_OPCTRL 4'b1110 +`define INTREMUW_OPCTRL 4'b1111 +`define INTDIVUW_OPCTRL 4'b1000 +`define RNE 3'b000 +`define RZ 3'b001 +`define RU 3'b011 +`define RD 3'b010 +`define RNM 3'b100 +`define FMAUNIT 2 +`define DIVUNIT 1 +`define CVTINTUNIT 0 +`define CVTFPUNIT 4 +`define CMPUNIT 3 +`define DIVREMSQRTUNIT 5 +`define INTDIVUNIT 6 + +string f16rv32cvtint[] = '{ + "ui32_to_f16_rne.tv", + "ui32_to_f16_rz.tv", + "ui32_to_f16_ru.tv", + "ui32_to_f16_rd.tv", + "ui32_to_f16_rnm.tv", + "i32_to_f16_rne.tv", + "i32_to_f16_rz.tv", + "i32_to_f16_ru.tv", + "i32_to_f16_rd.tv", + "i32_to_f16_rnm.tv", + "f16_to_ui32_rne.tv", + "f16_to_ui32_rz.tv", + "f16_to_ui32_ru.tv", + "f16_to_ui32_rd.tv", + "f16_to_ui32_rnm.tv", + "f16_to_i32_rne.tv", + "f16_to_i32_rz.tv", + "f16_to_i32_ru.tv", + "f16_to_i32_rd.tv", + "f16_to_i32_rnm.tv" +}; + +string f16rv64cvtint[] = '{ + "ui64_to_f16_rne.tv", + "ui64_to_f16_rz.tv", + "ui64_to_f16_ru.tv", + "ui64_to_f16_rd.tv", + "ui64_to_f16_rnm.tv", + "i64_to_f16_rne.tv", + "i64_to_f16_rz.tv", + "i64_to_f16_ru.tv", + "i64_to_f16_rd.tv", + "i64_to_f16_rnm.tv", + "f16_to_ui64_rne.tv", + "f16_to_ui64_rz.tv", + "f16_to_ui64_ru.tv", + "f16_to_ui64_rd.tv", + "f16_to_ui64_rnm.tv", + "f16_to_i64_rne.tv", + "f16_to_i64_rz.tv", + "f16_to_i64_ru.tv", + "f16_to_i64_rd.tv", + "f16_to_i64_rnm.tv" +}; + +string f32rv32cvtint[] = '{ + "ui32_to_f32_rne.tv", + "ui32_to_f32_rz.tv", + "ui32_to_f32_ru.tv", + "ui32_to_f32_rd.tv", + "ui32_to_f32_rnm.tv", + "i32_to_f32_rne.tv", + "i32_to_f32_rz.tv", + "i32_to_f32_ru.tv", + "i32_to_f32_rd.tv", + "i32_to_f32_rnm.tv", + "f32_to_ui32_rne.tv", + "f32_to_ui32_rz.tv", + "f32_to_ui32_ru.tv", + "f32_to_ui32_rd.tv", + "f32_to_ui32_rnm.tv", + "f32_to_i32_rne.tv", + "f32_to_i32_rz.tv", + "f32_to_i32_ru.tv", + "f32_to_i32_rd.tv", + "f32_to_i32_rnm.tv" +}; + +string f32rv64cvtint[] = '{ + "ui64_to_f32_rne.tv", + "ui64_to_f32_rz.tv", + "ui64_to_f32_ru.tv", + "ui64_to_f32_rd.tv", + "ui64_to_f32_rnm.tv", + "i64_to_f32_rne.tv", + "i64_to_f32_rz.tv", + "i64_to_f32_ru.tv", + "i64_to_f32_rd.tv", + "i64_to_f32_rnm.tv", + "f32_to_ui64_rne.tv", + "f32_to_ui64_rz.tv", + "f32_to_ui64_ru.tv", + "f32_to_ui64_rd.tv", + "f32_to_ui64_rnm.tv", + "f32_to_i64_rne.tv", + "f32_to_i64_rz.tv", + "f32_to_i64_ru.tv", + "f32_to_i64_rd.tv", + "f32_to_i64_rnm.tv" +}; + + +string f64rv32cvtint[] = '{ + "ui32_to_f64_rne.tv", + "ui32_to_f64_rz.tv", + "ui32_to_f64_ru.tv", + "ui32_to_f64_rd.tv", + "ui32_to_f64_rnm.tv", + "i32_to_f64_rne.tv", + "i32_to_f64_rz.tv", + "i32_to_f64_ru.tv", + "i32_to_f64_rd.tv", + "i32_to_f64_rnm.tv", + "f64_to_ui32_rne.tv", + "f64_to_ui32_rz.tv", + "f64_to_ui32_ru.tv", + "f64_to_ui32_rd.tv", + "f64_to_ui32_rnm.tv", + "f64_to_i32_rne.tv", + "f64_to_i32_rz.tv", + "f64_to_i32_ru.tv", + "f64_to_i32_rd.tv", + "f64_to_i32_rnm.tv" +}; + +string f64rv64cvtint[] = '{ + "ui64_to_f64_rne.tv", + "ui64_to_f64_rz.tv", + "ui64_to_f64_ru.tv", + "ui64_to_f64_rd.tv", + "ui64_to_f64_rnm.tv", + "i64_to_f64_rne.tv", + "i64_to_f64_rz.tv", + "i64_to_f64_ru.tv", + "i64_to_f64_rd.tv", + "i64_to_f64_rnm.tv", + "f64_to_ui64_rne.tv", + "f64_to_ui64_rz.tv", + "f64_to_ui64_ru.tv", + "f64_to_ui64_rd.tv", + "f64_to_ui64_rnm.tv", + "f64_to_i64_rne.tv", + "f64_to_i64_rz.tv", + "f64_to_i64_ru.tv", + "f64_to_i64_rd.tv", + "f64_to_i64_rnm.tv" +}; + +string f128rv64cvtint[] = '{ + "ui64_to_f128_rne.tv", + "ui64_to_f128_rz.tv", + "ui64_to_f128_ru.tv", + "ui64_to_f128_rd.tv", + "ui64_to_f128_rnm.tv", + "i64_to_f128_rne.tv", + "i64_to_f128_rz.tv", + "i64_to_f128_ru.tv", + "i64_to_f128_rd.tv", + "i64_to_f128_rnm.tv", + "f128_to_ui64_rne.tv", + "f128_to_ui64_rz.tv", + "f128_to_ui64_ru.tv", + "f128_to_ui64_rd.tv", + "f128_to_ui64_rnm.tv", + "f128_to_i64_rne.tv", + "f128_to_i64_rz.tv", + "f128_to_i64_ru.tv", + "f128_to_i64_rd.tv", + "f128_to_i64_rnm.tv" +}; + +string f128rv32cvtint[] = '{ + "ui32_to_f128_rne.tv", + "ui32_to_f128_rz.tv", + "ui32_to_f128_ru.tv", + "ui32_to_f128_rd.tv", + "ui32_to_f128_rnm.tv", + "i32_to_f128_rne.tv", + "i32_to_f128_rz.tv", + "i32_to_f128_ru.tv", + "i32_to_f128_rd.tv", + "i32_to_f128_rnm.tv", + "f128_to_ui32_rne.tv", + "f128_to_ui32_rz.tv", + "f128_to_ui32_ru.tv", + "f128_to_ui32_rd.tv", + "f128_to_ui32_rnm.tv", + "f128_to_i32_rne.tv", + "f128_to_i32_rz.tv", + "f128_to_i32_ru.tv", + "f128_to_i32_rd.tv", + "f128_to_i32_rnm.tv" +}; + +string f32f16cvt[] = '{ + "f32_to_f16_rne.tv", + "f32_to_f16_rz.tv", + "f32_to_f16_ru.tv", + "f32_to_f16_rd.tv", + "f32_to_f16_rnm.tv", + "f16_to_f32_rne.tv", + "f16_to_f32_rz.tv", + "f16_to_f32_ru.tv", + "f16_to_f32_rd.tv", + "f16_to_f32_rnm.tv" +}; + +string f64f16cvt[] = '{ + "f64_to_f16_rne.tv", + "f64_to_f16_rz.tv", + "f64_to_f16_ru.tv", + "f64_to_f16_rd.tv", + "f64_to_f16_rnm.tv", + "f16_to_f64_rne.tv", + "f16_to_f64_rz.tv", + "f16_to_f64_ru.tv", + "f16_to_f64_rd.tv", + "f16_to_f64_rnm.tv" +}; + +string f128f16cvt[] = '{ + "f128_to_f16_rne.tv", + "f128_to_f16_rz.tv", + "f128_to_f16_ru.tv", + "f128_to_f16_rd.tv", + "f128_to_f16_rnm.tv", + "f16_to_f128_rne.tv", + "f16_to_f128_rz.tv", + "f16_to_f128_ru.tv", + "f16_to_f128_rd.tv", + "f16_to_f128_rnm.tv" +}; + +string f64f32cvt[] = '{ + "f64_to_f32_rne.tv", + "f64_to_f32_rz.tv", + "f64_to_f32_ru.tv", + "f64_to_f32_rd.tv", + "f64_to_f32_rnm.tv", + "f32_to_f64_rne.tv", + "f32_to_f64_rz.tv", + "f32_to_f64_ru.tv", + "f32_to_f64_rd.tv", + "f32_to_f64_rnm.tv" +}; + +string f128f32cvt[] = '{ + "f128_to_f32_rne.tv", + "f128_to_f32_rz.tv", + "f128_to_f32_ru.tv", + "f128_to_f32_rd.tv", + "f128_to_f32_rnm.tv", + "f32_to_f128_rne.tv", + "f32_to_f128_rz.tv", + "f32_to_f128_ru.tv", + "f32_to_f128_rd.tv", + "f32_to_f128_rnm.tv" +}; + +string f128f64cvt[] = '{ + "f128_to_f64_rne.tv", + "f128_to_f64_rz.tv", + "f128_to_f64_ru.tv", + "f128_to_f64_rd.tv", + "f128_to_f64_rnm.tv", + "f64_to_f128_rne.tv", + "f64_to_f128_rz.tv", + "f64_to_f128_ru.tv", + "f64_to_f128_rd.tv", + "f64_to_f128_rnm.tv" +}; + +string f16add[] = '{ + "f16_add_rne.tv", + "f16_add_rz.tv", + "f16_add_ru.tv", + "f16_add_rd.tv", + "f16_add_rnm.tv" +}; + +string f32add[] = '{ + "f32_add_rne.tv", + "f32_add_rz.tv", + "f32_add_ru.tv", + "f32_add_rd.tv", + "f32_add_rnm.tv" +}; + +string f64add[] = '{ + "f64_add_rne.tv", + "f64_add_rz.tv", + "f64_add_ru.tv", + "f64_add_rd.tv", + "f64_add_rnm.tv" +}; + +string f128add[] = '{ + "f128_add_rne.tv", + "f128_add_rz.tv", + "f128_add_ru.tv", + "f128_add_rd.tv", + "f128_add_rnm.tv" +}; + +string f16sub[] = '{ + "f16_sub_rne.tv", + "f16_sub_rz.tv", + "f16_sub_ru.tv", + "f16_sub_rd.tv", + "f16_sub_rnm.tv" +}; + +string f32sub[] = '{ + "f32_sub_rne.tv", + "f32_sub_rz.tv", + "f32_sub_ru.tv", + "f32_sub_rd.tv", + "f32_sub_rnm.tv" +}; + +string f64sub[] = '{ + "f64_sub_rne.tv", + "f64_sub_rz.tv", + "f64_sub_ru.tv", + "f64_sub_rd.tv", + "f64_sub_rnm.tv" +}; + +string f128sub[] = '{ + "f128_sub_rne.tv", + "f128_sub_rz.tv", + "f128_sub_ru.tv", + "f128_sub_rd.tv", + "f128_sub_rnm.tv" +}; + +string f16mul[] = '{ + "f16_mul_rne.tv", + "f16_mul_rz.tv", + "f16_mul_ru.tv", + "f16_mul_rd.tv", + "f16_mul_rnm.tv" +}; + +string f32mul[] = '{ + "f32_mul_rne.tv", + "f32_mul_rz.tv", + "f32_mul_ru.tv", + "f32_mul_rd.tv", + "f32_mul_rnm.tv" +}; + +string f64mul[] = '{ + "f64_mul_rne.tv", + "f64_mul_rz.tv", + "f64_mul_ru.tv", + "f64_mul_rd.tv", + "f64_mul_rnm.tv" +}; + +string f128mul[] = '{ + "f128_mul_rne.tv", + "f128_mul_rz.tv", + "f128_mul_ru.tv", + "f128_mul_rd.tv", + "f128_mul_rnm.tv" +}; + +string f16div[] = '{ + "f16_div_rne.tv", + "f16_div_rz.tv", + "f16_div_ru.tv", + "f16_div_rd.tv", + "f16_div_rnm.tv" +}; + +string f32div[] = '{ + "f32_div_rne.tv", + "f32_div_rz.tv", + "f32_div_ru.tv", + "f32_div_rd.tv", + "f32_div_rnm.tv" +}; + +string f64div[] = '{ + "f64_div_rne.tv", + "f64_div_rz.tv", + "f64_div_ru.tv", + "f64_div_rd.tv", + "f64_div_rnm.tv" +}; + +string f128div[] = '{ + "f128_div_rne.tv", + "f128_div_rz.tv", + "f128_div_ru.tv", + "f128_div_rd.tv", + "f128_div_rnm.tv" +}; + +string f16sqrt[] = '{ + "f16_sqrt_rne.tv", + "f16_sqrt_rz.tv", + "f16_sqrt_ru.tv", + "f16_sqrt_rd.tv", + "f16_sqrt_rnm.tv" +}; + +string f32sqrt[] = '{ + "f32_sqrt_rne.tv", + "f32_sqrt_rz.tv", + "f32_sqrt_ru.tv", + "f32_sqrt_rd.tv", + "f32_sqrt_rnm.tv" +}; + +string f64sqrt[] = '{ + "f64_sqrt_rne.tv", + "f64_sqrt_rz.tv", + "f64_sqrt_ru.tv", + "f64_sqrt_rd.tv", + "f64_sqrt_rnm.tv" +}; + +string f128sqrt[] = '{ + "f128_sqrt_rne.tv", + "f128_sqrt_rz.tv", + "f128_sqrt_ru.tv", + "f128_sqrt_rd.tv", + "f128_sqrt_rnm.tv" +}; + +string f16cmp[] = '{ + "f16_eq_rne.tv", + "f16_eq_rz.tv", + "f16_eq_ru.tv", + "f16_eq_rd.tv", + "f16_eq_rnm.tv", + "f16_le_rne.tv", + "f16_le_rz.tv", + "f16_le_ru.tv", + "f16_le_rd.tv", + "f16_le_rnm.tv", + "f16_lt_rne.tv", + "f16_lt_rz.tv", + "f16_lt_ru.tv", + "f16_lt_rd.tv", + "f16_lt_rnm.tv" +}; + +string f32cmp[] = '{ + "f32_eq_rne.tv", + "f32_eq_rz.tv", + "f32_eq_ru.tv", + "f32_eq_rd.tv", + "f32_eq_rnm.tv", + "f32_le_rne.tv", + "f32_le_rz.tv", + "f32_le_ru.tv", + "f32_le_rd.tv", + "f32_le_rnm.tv", + "f32_lt_rne.tv", + "f32_lt_rz.tv", + "f32_lt_ru.tv", + "f32_lt_rd.tv", + "f32_lt_rnm.tv" +}; + +string f64cmp[] = '{ + "f64_eq_rne.tv", + "f64_eq_rz.tv", + "f64_eq_ru.tv", + "f64_eq_rd.tv", + "f64_eq_rnm.tv", + "f64_le_rne.tv", + "f64_le_rz.tv", + "f64_le_ru.tv", + "f64_le_rd.tv", + "f64_le_rnm.tv", + "f64_lt_rne.tv", + "f64_lt_rz.tv", + "f64_lt_ru.tv", + "f64_lt_rd.tv", + "f64_lt_rnm.tv" +}; + +string f128cmp[] = '{ + "f128_eq_rne.tv", + "f128_eq_rz.tv", + "f128_eq_ru.tv", + "f128_eq_rd.tv", + "f128_eq_rnm.tv", + "f128_le_rne.tv", + "f128_le_rz.tv", + "f128_le_ru.tv", + "f128_le_rd.tv", + "f128_le_rnm.tv", + "f128_lt_rne.tv", + "f128_lt_rz.tv", + "f128_lt_ru.tv", + "f128_lt_rd.tv", + "f128_lt_rnm.tv" +}; + +string f16fma[] = '{ + "f16_mulAdd_rne.tv", + "f16_mulAdd_rz.tv", + "f16_mulAdd_ru.tv", + "f16_mulAdd_rd.tv", + "f16_mulAdd_rnm.tv" +}; + +string f32fma[] = '{ + "f32_mulAdd_rne.tv", + "f32_mulAdd_rz.tv", + "f32_mulAdd_ru.tv", + "f32_mulAdd_rd.tv", + "f32_mulAdd_rnm.tv" +}; + +string f64fma[] = '{ + "f64_mulAdd_rne.tv", + "f64_mulAdd_rz.tv", + "f64_mulAdd_ru.tv", + "f64_mulAdd_rd.tv", + "f64_mulAdd_rnm.tv" +}; + +string f128fma[] = '{ + "f128_mulAdd_rne.tv", + "f128_mulAdd_rz.tv", + "f128_mulAdd_ru.tv", + "f128_mulAdd_rd.tv", + "f128_mulAdd_rnm.tv" +}; + +string int64rem[] = '{ + "cvw_64_rem-01.tv" +}; + +string int64div[] = '{ + "cvw_64_div-01.tv" +}; + +string int64remu[] = '{ + "cvw_64_remu-01.tv" +}; + +string int64divu[] = '{ + "cvw_64_divu-01.tv" +}; + +string int64remw[] = '{ + "cvw_64_remw-01.tv" +}; + +string int64remuw[] = '{ + "cvw_64_remuw-01.tv" +}; + +string int64divuw[] = '{ + "cvw_64_divuw-01.tv" +}; + +string int64divw[] = '{ + "cvw_64_divw-01.tv" +}; + +string int32rem[] = '{ + "cvw_32_rem-01.tv" +}; + +string int32div[] = '{ + "cvw_32_div-01.tv" +}; + +string int32remu[] = '{ + "cvw_32_remu-01.tv" +}; + +string int32divu[] = '{ + "cvw_32_divu-01.tv" +};