Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Cleaned up the IFU and LSU around dtim and irom address calculation.

Browse Source
This commit is contained in:
Ross Thompson 2022-09-21 18:23:56 -05:00
parent f57b0b9950
commit 99e01dd31f
2 changed files with 5 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
pipelined/src/ifu/ifu.sv
View File

@ -186,14 +186,8 @@ module ifu (
// The IROM uses untranslated addresses, so it is not compatible with virtual memory. // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
if (`IROM_SUPPORTED) begin : irom if (`IROM_SUPPORTED) begin : irom
logic [`PA_BITS-1:0] IROMAdr;
logic IROMAccessRW;
/* verilator lint_off WIDTH */
assign IROMAdr = reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */
assign RWF = 2'b10; assign RWF = 2'b10;
irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(IROMAdr[`XLEN-1:0]), .ReadData(FinalInstrRawF)); irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(FinalInstrRawF));
end else begin end else begin
assign RWF = 2'b10; assign RWF = 2'b10;
@ -322,8 +316,10 @@ module ifu (
assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4 based on CompressedF, which arrives later. // choose PC+2 or PC+4 based on CompressedF, which arrives later.
// Speeds up critical path as compared to selecting adder input based on CompressedF // Speeds up critical path as compared to selecting adder input based on CompressedF
// *** consider gating PCPlusUpperF to provide the reset.
always_comb always_comb
if (CompressedF) // add 2 if(reset) PCPlus2or4F = '0;
else if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4

3
pipelined/src/lsu/lsu.sv
View File

@ -212,10 +212,9 @@ module lsu (
// The DTIM uses untranslated addresses, so it is not compatible with virtual memory. // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
// Don't perform size checking on DTIM // Don't perform size checking on DTIM
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
assign MemStage = MemRWM[0] | reset; // 1 = M stage; 0 = E stage assign MemStage = MemRWM[0]; // 1 = M stage; 0 = E stage // **** is reset needed.
assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
// *** add ce to bram1... to remove this extra mux control.
dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM, dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM,
.Adr(DTIMAdr), .Adr(DTIMAdr),