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Updated fpga's bootloader to reflect the changes to the gpio address change.

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This commit is contained in:
Ross Thompson 2022-02-01 10:43:24 -06:00
parent b621eb78fb
commit 99bb281944
3 changed files with 44 additions and 44 deletions
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84
pipelined/src/uncore/ram.sv
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@ -59,48 +59,48 @@ module ram #(parameter BASE=0, RANGE = 65535) (
// *** need to address this preload for fpga. It should work as a preload file // *** need to address this preload for fpga. It should work as a preload file
// but for some reason vivado is not synthesizing the preload. // but for some reason vivado is not synthesizing the preload.
//$readmemh(PRELOAD, RAM); //$readmemh(PRELOAD, RAM);
RAM[0] = 64'h94e1819300002197; RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081; RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301; RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501; RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701; RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901; RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01; RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01; RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01; RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e; RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010; RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b; RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f; RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110012e37; RAM[13] = 64'h4e952e3110060e37;
RAM[14] = 64'hc602829b0053f2b7; RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd; RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e; RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602; RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023; RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0; RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870; RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613; RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe; RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822; RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064505; RAM[24] = 64'h892ee04aec064505;
RAM[25] = 64'h06e000ef07e000ef; RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563; RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204; RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004; RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3; RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004; RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94; RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902; RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783; RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823; RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7; RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89; RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749; RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23; RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082; RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85; RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023; RAM[41] = 64'h0000808210a7a023;
end // initial begin end // initial begin
end // if (FPGA) end // if (FPGA)

2
tests/testsBP/fpga-test-sdc/Makefile
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@ -106,7 +106,7 @@ $(TARGET).memfile: $(TARGET)
@echo 'Making object dump file.' @echo 'Making object dump file.'
@riscv64-unknown-elf-objdump -D $< > $<.objdump @riscv64-unknown-elf-objdump -D $< > $<.objdump
@echo 'Making memory file' @echo 'Making memory file'
exe2memfile0.pl $< riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
extractFunctionRadix.sh $<.objdump extractFunctionRadix.sh $<.objdump
mkdir -p ../../imperas-riscv-tests/work/rv64BP/ mkdir -p ../../imperas-riscv-tests/work/rv64BP/
cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/

2
tests/testsBP/fpga-test-sdc/bios.s
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@ -61,7 +61,7 @@ _start:
# write to gpio # write to gpio
li t2, 0xFF li t2, 0xFF
la t3, 0x1001200C la t3, 0x1006000C
li t4, 5 li t4, 5
loop: loop: