From 9982549057198788541c2ca733d72743e7fcd9f3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 21 Jan 2022 15:42:54 -0600
Subject: [PATCH] Changed the IROM and DTIM memories to behave like
 edge-triggered srams.

---
 pipelined/src/generic/flop/simpleram.sv | 11 +++++----
 pipelined/src/ifu/ifu.sv                | 32 ++++++++++++++++---------
 pipelined/src/lsu/lsu.sv                |  4 ++--
 3 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 78897c443..145a016c0 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -54,23 +54,26 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   logic        memwrite;
   logic [3:0]  busycount;
 
+  assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
+
+  flopenr #(32)   haddrreg(HCLK, 1'b0, 1'b1, HADDR, A);
   
   /* verilator lint_off WIDTH */
   if (`XLEN == 64)  begin:ramrw
     always_ff @(posedge HCLK) begin
-      if (HWRITE & |HTRANS) RAM[HADDR[31:3]] <= #1 HWDATA;
+      if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
     end
   end else begin 
     always_ff @(posedge HCLK) begin:ramrw
-      if (HWRITE & |HTRANS) RAM[HADDR[31:2]] <= #1 HWDATA;
+      if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
     end
   end
 
   // read
   if(`XLEN == 64) begin: ramr
-    assign HREADRam0 = RAM[HADDR[31:3]];
+    assign HREADRam0 = RAM[A[31:3]];
   end else begin
-    assign HREADRam0 = RAM[HADDR[31:2]];
+    assign HREADRam0 = RAM[A[31:2]];
   end
 
   /* verilator lint_on WIDTH */
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 6feb8dbd1..bdf974a2d 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -96,7 +96,7 @@ module ifu (
   logic [`XLEN-1:0]            PCD;
 
   localparam [31:0]            nop = 32'h00000013; // instruction for NOP
-  //logic                        reset_q; // see comment below about PCNextF and icache.
+  logic                        reset_q; // see comment below about PCNextF and icache.
 
   logic                        BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   logic [`XLEN-1:0] 		   PCBPWrongInvalidate;
@@ -236,11 +236,20 @@ module ifu (
     simpleram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .HCLK(clk), .HRESETn(~reset), 
-        .HSELRam(1'b1), .HADDR(PCPF[31:0]),
+        .HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextF[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
         .HWRITE(1'b0), .HREADY(1'b1),
         .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
         .HRESPRam(), .HREADYRam());
 
+/* -----\/----- EXCLUDED -----\/-----
+    ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
+        .HCLK(clk), .HRESETn(~reset), 
+        .HSELRam(1'b1), .HADDR(PCNextF[31:0]),
+        .HWRITE(1'b0), .HREADY(1'b1),
+        .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
+        .HRESPRam(), .HREADYRam());
+ -----/\----- EXCLUDED -----/\----- */
+
 	assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
     assign BusStall = 0;
     assign IFUBusRead = 0;
@@ -354,9 +363,9 @@ module ifu (
   mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
          .d1(PrivilegedNextPCM),
          .s(PrivilegedChangePCM),
-         .y(UnalignedPCNextF));
+         //.y(UnalignedPCNextF));
+         .y(PCNext3F));
 
-         //.y(PCNext3F));
   // This mux is not strictly speaking required.  Because the icache takes in
   // PCNextF rather than PCPF, PCNextF should stay in reset while the cache
   // looks up the addresses.  Without this mux PCNextF will increment + 2/4.
@@ -367,13 +376,14 @@ module ifu (
   // cache line so the mux is not required.  I am leaving this comment and mux
   // a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR
   // during reset becomes a requirement.
-  //mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
-  //       .d1(`RESET_VECTOR),
-  //       .s(reset_q),
-  //       .y(UnalignedPCNextF)); 
-  //flop #(1) resetReg (.clk(clk),
-  //      .d(reset),
-  //      .q(reset_q));
+  mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
+                       .d1(`RESET_VECTOR),
+                       .s(`MEM_IROM ? reset : reset_q),
+                       .y(UnalignedPCNextF));
+
+  flop #(1) resetReg (.clk(clk),
+        .d(reset),
+        .q(reset_q));
 
 
   flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 429a9dd4e..5a6991fd3 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -247,7 +247,7 @@ module lsu (
   if (`MEM_DTIM) begin : dtim
     simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .HCLK(clk), .HRESETn(~reset), 
-        .HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
+        .HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
         .HWRITE(LSURWM[0]), .HREADY(1'b1),
         .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
         .HRESPRam(), .HREADYRam());
@@ -259,7 +259,7 @@ module lsu (
     assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
     assign ReadDataLineSetsM[0] = 0;
     assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
-end else begin : bus  // *** lsubusdp
+  end else begin : bus  // *** lsubusdp
     // Bus Side logic
     // register the fetch data from the next level of memory.
     // This register should be necessary for timing.  There is no register in the uncore or