From aa3bc1025952108dc2141ebea86d0d4e836754ed Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 19 Oct 2023 11:16:02 -0700
Subject: [PATCH 1/2] Modified log2 coding to avoid synthesis warning

---
 src/cache/cacheLRU.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 34ea59612..613dd6de7 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -70,8 +70,10 @@ module cacheLRU
   // coverage off
   // Excluded from coverage b/c it is untestable without varying NUMWAYS.
   function integer log2 (integer value);
-    for (log2=0; value>0; log2=log2+1)
-      value = value>>1;
+    int val;
+    val = value;
+    for (log2 = 0; val > 0; log2 = log2+1)
+      val = val >> 1;
     return log2;
   endfunction // log2
   // coverage on

From 46d16305a49d2db5d93c986ffaa9b698231ab46a Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 19 Oct 2023 13:46:30 -0700
Subject: [PATCH 2/2] Set drive for Sky130

---
 synthDC/scripts/synth.tcl | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 542cb8fc1..bdd868dd1 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -148,18 +148,22 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
 
 # Setting constraints on input ports 
 if {$tech == "sky130"} {
-    set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
+    if {$drive == "INV"} {
+	    set_driving_cell -lib_cell inv -pin Y $all_in_ex_clk
+    } elseif {$drive == "FLOP"} {
+	    set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
+    }
 } elseif {$tech == "sky90"} {
     if {$drive == "INV"} {
-	set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
+	    set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
     } elseif {$drive == "FLOP"} {
-	set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
+	    set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
     }
 } elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} {
     if {$drive == "INV"} {
-	set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
+	    set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
     } elseif {$drive == "FLOP"} {
-    set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
+        set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
     }
 }
 
@@ -174,16 +178,20 @@ if {$drive == "FLOP"} {
 
 # Setting load constraint on output ports 
 if {$tech == "sky130"} {
-    set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
-} elseif {$tech == "sky90"} {
     if {$drive == "INV"} {
-	set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
+	    set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__inv_4/A] * 1] [all_outputs]
+    } elseif {$drive == "FLOP"} {
+        set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
+    }
+ } elseif {$tech == "sky90"} {
+    if {$drive == "INV"} {
+	    set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
     } elseif {$drive == "FLOP"} {
         set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
     }
 } elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
     if {$drive == "INV"} {
-	set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
+	    set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
     } elseif {$drive == "FLOP"} {
         set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs]
     }