From 995cfb1cf345c7b42dfc9ecb08c68066bb5e6129 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 11:21:44 -0600 Subject: [PATCH] Cleaned up some names in dcache and lsu. --- wally-pipelined/src/cache/dcache.sv | 262 +++++++++++-------------- wally-pipelined/src/cache/dcachefsm.sv | 26 +-- wally-pipelined/src/lsu/lrsc.sv | 4 +- wally-pipelined/src/lsu/lsu.sv | 54 ++--- 4 files changed, 152 insertions(+), 194 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 1a41e7aa5..6d13a1a17 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -38,17 +38,17 @@ module dcache input logic FlushDCacheM, input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address - + input logic [`XLEN-1:0] FinalWriteDataM, output logic [`XLEN-1:0] ReadDataWordM, output logic DCacheStall, output logic DCacheMiss, output logic DCacheAccess, - output logic DCCommittedM, - output logic DCWriteLine, - output logic DCFetchLine, - input logic BUSACK, - + output logic DCacheCommittedM, + output logic DCacheWriteLine, + output logic DCacheFetchLine, + input logic DCacheBusAck, + output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], @@ -64,119 +64,105 @@ module dcache input logic IgnoreRequest ); - localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; - localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; - localparam integer NUMWAYS = `DCACHE_NUMWAYS; + localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; + localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; + localparam integer NUMWAYS = `DCACHE_NUMWAYS; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; - localparam integer LOGWPL = $clog2(WORDSPERLINE); - localparam integer LOGXLENBYTES = $clog2(`XLEN/8); + localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer INDEXLEN = $clog2(NUMLINES); + localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; + localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer LOGWPL = $clog2(WORDSPERLINE); + localparam integer LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer FlushAdrThreshold = NUMLINES - 1; + localparam integer FlushAdrThreshold = NUMLINES - 1; - logic [1:0] SelAdrM; - logic [INDEXLEN-1:0] RAdr; - logic [INDEXLEN-1:0] WAdr; - logic [BLOCKLEN-1:0] SRAMWriteData; - logic SetValid, ClearValid; - logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] WayHit; - logic CacheHit; - logic [BLOCKLEN-1:0] ReadDataBlockM; - logic [`XLEN-1:0] ReadDataWordMuxM; - logic [WORDSPERLINE-1:0] SRAMWordEnable; + logic [1:0] SelAdrM; + logic [INDEXLEN-1:0] RAdr; + logic [BLOCKLEN-1:0] SRAMWriteData; + logic SetValid, ClearValid; + logic SetDirty, ClearDirty; + logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; + logic [NUMWAYS-1:0] WayHit; + logic CacheHit; + logic [BLOCKLEN-1:0] ReadDataBlockM; + logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SRAMWordWriteEnableM; - logic SRAMBlockWriteEnableM; - logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; - //logic SRAMWriteEnable; - logic [NUMWAYS-1:0] SRAMWayWriteEnable; + logic SRAMWordWriteEnableM; + logic SRAMBlockWriteEnableM; + logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; + logic [NUMWAYS-1:0] SRAMWayWriteEnable; - logic [NUMWAYS-1:0] VictimWay; - logic [NUMWAYS-1:0] VictimDirtyWay; - logic VictimDirty; + logic [NUMWAYS-1:0] VictimWay; + logic [NUMWAYS-1:0] VictimDirtyWay; + logic VictimDirty; - logic [2**LOGWPL-1:0] MemPAdrDecodedW; + logic [2**LOGWPL-1:0] MemPAdrDecodedW; - logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; - logic [TAGLEN-1:0] VictimTag; + logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; + logic [TAGLEN-1:0] VictimTag; - logic [INDEXLEN-1:0] FlushAdr; - logic [INDEXLEN-1:0] FlushAdrP1; - logic FlushAdrCntEn; - logic FlushAdrCntRst; - logic FlushAdrFlag; + logic [INDEXLEN-1:0] FlushAdr; + logic [INDEXLEN-1:0] FlushAdrP1; + logic FlushAdrCntEn; + logic FlushAdrCntRst; + logic FlushAdrFlag; - logic [NUMWAYS-1:0] FlushWay; - logic [NUMWAYS-1:0] NextFlushWay; - logic FlushWayCntEn; - logic FlushWayCntRst; - - logic VDWriteEnable; - - logic SelEvict; + logic [NUMWAYS-1:0] FlushWay; + logic [NUMWAYS-1:0] NextFlushWay; + logic FlushWayCntEn; + logic FlushWayCntRst; - logic LRUWriteEn; - - logic [NUMWAYS-1:0] VDWriteEnableWay; + logic VDWriteEnable; + logic SelEvict; + logic LRUWriteEn; + logic [NUMWAYS-1:0] VDWriteEnableWay; // Read Path CPU (IEU) side mux3 #(INDEXLEN) AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(FlushAdr), - .s(SelAdrM), - .y(RAdr)); - - mux2 #(INDEXLEN) - WAdrSelMux(.d0(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(FlushAdr), - .s(&SelAdrM), - .y(WAdr)); - - + .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .d2(FlushAdr), + .s(SelAdrM), + .y(RAdr)); cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) MemWay[NUMWAYS-1:0](.clk, - .reset, - .RAdr, - .WAdr, - .PAdr(MemPAdrM), - .WriteEnable(SRAMWayWriteEnable), - .VDWriteEnable(VDWriteEnableWay), - .WriteWordEnable(SRAMWordEnable), - .TagWriteEnable(SRAMBlockWayWriteEnableM), - .WriteData(SRAMWriteData), - .SetValid, - .ClearValid, - .SetDirty, - .ClearDirty, - .SelEvict, - .VictimWay, - .FlushWay, - .SelFlush, - .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), - .WayHit, - .VictimDirtyWay, - .VictimTagWay, - .InvalidateAll(1'b0)); + .reset, + .RAdr, + .WAdr(RAdr), // *** Reduce after addressing in icache also + .PAdr(MemPAdrM), + .WriteEnable(SRAMWayWriteEnable), + .VDWriteEnable(VDWriteEnableWay), + .WriteWordEnable(SRAMWordEnable), + .TagWriteEnable(SRAMBlockWayWriteEnableM), + .WriteData(SRAMWriteData), + .SetValid, + .ClearValid, + .SetDirty, + .ClearDirty, + .SelEvict, + .VictimWay, + .FlushWay, + .SelFlush, + .ReadDataBlockWayMasked(ReadDataBlockWayMaskedM), + .WayHit, + .VictimDirtyWay, + .VictimTagWay, + .InvalidateAll(1'b0)); generate if(NUMWAYS > 1) begin cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(.clk, .reset, - .WayHit, - .VictimWay, - .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .RAdr, - .LRUWriteEn); + .WayHit, + .VictimWay, + .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + .RAdr, + .LRUWriteEn); end else begin assign VictimWay = 1'b1; // one hot. end @@ -207,54 +193,53 @@ module dcache assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; - // Write Path CPU (IEU) side onehotdecoder #(LOGWPL) adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), - .decoded(MemPAdrDecodedW)); + .decoded(MemPAdrDecodedW)); assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0; mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), - .d1(SRAMBlockWayWriteEnableM), - .s(SRAMBlockWriteEnableM), - .y(SRAMWayWriteEnable)); + .d1(SRAMBlockWayWriteEnableM), + .s(SRAMBlockWriteEnableM), + .y(SRAMWayWriteEnable)); mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), - .d1(DCacheMemWriteData), - .s(SRAMBlockWriteEnableM), - .y(SRAMWriteData)); + .d1(DCacheMemWriteData), + .s(SRAMBlockWriteEnableM), + .y(SRAMWriteData)); mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(DCacheBusAdr)); + .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), + .s({SelFlush, SelEvict}), + .y(DCacheBusAdr)); // flush address and way generation. flopenr #(INDEXLEN) FlushAdrReg(.clk, - .reset(reset | FlushAdrCntRst), - .en(FlushAdrCntEn & FlushWay[NUMWAYS-1]), - .d(FlushAdrP1), - .q(FlushAdr)); + .reset(reset | FlushAdrCntRst), + .en(FlushAdrCntEn & FlushWay[NUMWAYS-1]), + .d(FlushAdrP1), + .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; flopenl #(NUMWAYS) FlushWayReg(.clk, - .load(reset | FlushWayCntRst), - .en(FlushWayCntEn), - .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), - .q(FlushWay)); + .load(reset | FlushWayCntRst), + .en(FlushWayCntEn), + .val({{NUMWAYS-1{1'b0}}, 1'b1}), + .d(NextFlushWay), + .q(FlushWay)); assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}}; @@ -262,44 +247,17 @@ module dcache assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; - - //assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; - // controller - dcachefsm dcachefsm(.clk, - .reset, - .DCFetchLine, - .DCWriteLine, - .BUSACK, - .MemRWM, - .AtomicM, - .CPUBusy, - .CacheableM, - .IgnoreRequest, - .CacheHit, - .VictimDirty, - .DCacheStall, - .DCCommittedM, - .DCacheMiss, - .DCacheAccess, - .SelAdrM, - .SetValid, - .ClearValid, - .SetDirty, - .ClearDirty, - .SRAMWordWriteEnableM, - .SRAMBlockWriteEnableM, - .SelEvict, - .SelFlush, - .FlushAdrCntEn, - .FlushWayCntEn, - .FlushAdrCntRst, - .FlushWayCntRst, - .FlushAdrFlag, - .FlushDCacheM, - .VDWriteEnable, - .LRUWriteEn); + dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, + .MemRWM, .AtomicM, .CPUBusy, .CacheableM, .IgnoreRequest, + .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM, + .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid, + .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, + .SRAMBlockWriteEnableM, .SelEvict, .SelFlush, + .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, + .FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM, + .VDWriteEnable, .LRUWriteEn); endmodule // dcache diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 09594ce4d..418a1ad20 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -38,7 +38,7 @@ module dcachefsm // hptw inputs input logic IgnoreRequest, // Bus inputs - input logic BUSACK, + input logic DCacheBusAck, // dcache internals input logic CacheHit, input logic VictimDirty, @@ -50,9 +50,9 @@ module dcachefsm output logic DCacheMiss, output logic DCacheAccess, // Bus outputs - output logic DCCommittedM, - output logic DCWriteLine, - output logic DCFetchLine, + output logic DCacheCommittedM, + output logic DCacheWriteLine, + output logic DCacheFetchLine, // dcache internals output logic [1:0] SelAdrM, @@ -123,8 +123,8 @@ module dcachefsm FlushWayCntRst = 1'b0; VDWriteEnable = 1'b0; NextState = STATE_READY; - DCFetchLine = 1'b0; - DCWriteLine = 1'b0; + DCacheFetchLine = 1'b0; + DCacheWriteLine = 1'b0; case (CurrState) STATE_READY: begin @@ -204,7 +204,7 @@ module dcachefsm else if((|MemRWM) & CacheableM & ~CacheHit) begin NextState = STATE_MISS_FETCH_WDV; DCacheStall = 1'b1; - DCFetchLine = 1'b1; + DCacheFetchLine = 1'b1; end else NextState = STATE_READY; end @@ -213,7 +213,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b01; - if (BUSACK) begin + if (DCacheBusAck) begin NextState = STATE_MISS_FETCH_DONE; end else begin NextState = STATE_MISS_FETCH_WDV; @@ -225,7 +225,7 @@ module dcachefsm SelAdrM = 2'b01; if(VictimDirty) begin NextState = STATE_MISS_EVICT_DIRTY; - DCWriteLine = 1'b1; + DCacheWriteLine = 1'b1; end else begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end @@ -299,7 +299,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b01; SelEvict = 1'b1; - if(BUSACK) begin + if(DCacheBusAck) begin NextState = STATE_MISS_WRITE_CACHE_BLOCK; end else begin NextState = STATE_MISS_EVICT_DIRTY; @@ -344,7 +344,7 @@ module dcachefsm NextState = STATE_FLUSH_WRITE_BACK; FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; - DCWriteLine = 1'b1; + DCacheWriteLine = 1'b1; end else if (FlushAdrFlag) begin NextState = STATE_READY; DCacheStall = 1'b0; @@ -359,7 +359,7 @@ module dcachefsm DCacheStall = 1'b1; SelAdrM = 2'b10; SelFlush = 1'b1; - if(BUSACK) begin + if(DCacheBusAck) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin NextState = STATE_FLUSH_WRITE_BACK; @@ -391,7 +391,7 @@ module dcachefsm endcase end - assign DCCommittedM = CurrState != STATE_READY; + assign DCacheCommittedM = CurrState != STATE_READY; endmodule // dcachefsm diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv index 1bd2c3ca4..77e59cd37 100644 --- a/wally-pipelined/src/lsu/lrsc.sv +++ b/wally-pipelined/src/lsu/lrsc.sv @@ -32,7 +32,7 @@ module lrsc input logic FlushW, CPUBusy, input logic MemReadM, input logic [1:0] LsuRWM, - output logic [1:0] DCRWM, + output logic [1:0] DCacheRWM, input logic [1:0] LsuAtomicM, input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache output logic SquashSCW @@ -47,7 +47,7 @@ module lrsc assign scM = LsuRWM[0] && LsuAtomicM[0]; assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; - assign DCRWM = SquashSCM ? 2'b00 : LsuRWM; + assign DCacheRWM = SquashSCM ? 2'b00 : LsuRWM; always_comb begin // ReservationValidM (next value of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 248793141..da35471f1 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -95,12 +95,12 @@ module lsu logic DTLBMissM; logic DTLBWriteM; - logic [1:0] DCRWM; + logic [1:0] DCacheRWM; logic [1:0] LsuRWM; logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; - logic [11:0] LsuAdrE, DCAdrE; + logic [11:0] LsuAdrE, DCacheAdrE; logic CPUBusy; logic MemReadM; logic DataMisalignedM; @@ -115,7 +115,7 @@ module lsu logic InterlockStall; logic IgnoreRequest; - logic BusCommittedM, DCCommittedM; + logic BusCommittedM, DCacheCommittedM; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); @@ -236,13 +236,13 @@ module lsu assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; - assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; + assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; end // if (`MEM_VIRTMEM) else begin assign InterlockStall = 1'b0; - assign DCAdrE = LsuAdrE; + assign DCacheAdrE = LsuAdrE; assign SelHPTW = 1'b0; assign IgnoreRequest = 1'b0; @@ -263,7 +263,7 @@ module lsu end endgenerate - assign CommittedM = SelHPTW | DCCommittedM | BusCommittedM; + assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, @@ -299,10 +299,10 @@ module lsu if (`A_SUPPORTED) begin assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, - .SquashSCW, .DCRWM); + .SquashSCW, .DCacheRWM); end else begin assign SquashSCW = 0; - assign DCRWM = LsuRWM; + assign DCacheRWM = LsuRWM; end endgenerate @@ -355,9 +355,9 @@ module lsu - logic DCWriteLine; - logic DCFetchLine; - logic BUSACK; + logic DCacheWriteLine; + logic DCacheFetchLine; + logic DCacheBusAck; logic UnCachedLsuBusRead; logic UnCachedLsuBusWrite; @@ -365,23 +365,23 @@ module lsu dcache dcache(.clk, .reset, .CPUBusy, - .MemRWM(DCRWM), + .MemRWM(DCacheRWM), .Funct3M(LsuFunct3M), .Funct7M, .FlushDCacheM, .AtomicM(LsuAtomicM), - .MemAdrE(DCAdrE), + .MemAdrE(DCacheAdrE), .MemPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM(CacheableM), - .DCCommittedM, + .DCacheCommittedM, .DCacheBusAdr, .ReadDataBlockSetsM, .SelFlush, .DCacheMemWriteData, - .DCFetchLine, - .DCWriteLine, - .BUSACK + .DCacheFetchLine, + .DCacheWriteLine, + .DCacheBusAck ); @@ -475,10 +475,10 @@ module lsu case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(DCRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(DCRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; - else if(DCFetchLine) BusNextState = STATE_BUS_FETCH; - else if(DCWriteLine) BusNextState = STATE_BUS_WRITE; + else if(DCacheRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(DCacheRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; + else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; STATE_BUS_UNCACHED_READ: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; @@ -498,24 +498,24 @@ module lsu assign CntReset = BusCurrState == STATE_BUS_READY; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCRWM)) | DCFetchLine | DCWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCacheRWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; - assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCRWM[0])) | + assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCacheRWM[0])) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCRWM[1])) | + assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCacheRWM[1])) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); - assign BUSACK = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | - (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | + (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCRWM & ~CacheableM)) | + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCacheRWM & ~CacheableM)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE |