From 04744032d88cce2dedb9952bdf41526b929d21c0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 2 Jun 2024 16:59:11 -0500 Subject: [PATCH 01/19] Updated more signal names to match book. --- src/ifu/bpred/bpred.sv | 28 +++++++++++------------ src/ifu/bpred/gshare.sv | 38 ++++++++++++++++---------------- src/ifu/bpred/gsharebasic.sv | 22 +++++++++--------- src/ifu/bpred/localaheadbp.sv | 30 ++++++++++++------------- src/ifu/bpred/localbpbasic.sv | 22 +++++++++--------- src/ifu/bpred/localrepairbp.sv | 32 +++++++++++++-------------- src/ifu/bpred/twoBitPredictor.sv | 22 +++++++++--------- src/ifu/ifu.sv | 6 ++--- src/privileged/csr.sv | 4 ++-- src/privileged/csrc.sv | 4 ++-- src/privileged/privileged.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 6 ++--- 12 files changed, 109 insertions(+), 109 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 6080cacb5..146a9c946 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -64,18 +64,18 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // Report branch prediction status output logic BPWrongE, // Prediction is wrong output logic BPWrongM, // Prediction is wrong - output logic BPDirPredWrongM, // Prediction direction is wrong + output logic BPDirWrongM, // Prediction direction is wrong output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong output logic IClassWrongM // Class prediction is wrong ); - logic [1:0] BPDirPredF; + logic [1:0] BPDirF; logic [P.XLEN-1:0] BPBTAF, RASPCF; logic BPPCWrongE; logic IClassWrongE; - logic BPDirPredWrongE; + logic BPDirWrongE; logic BPPCSrcF; logic [P.XLEN-1:0] BPPCF; @@ -104,45 +104,45 @@ module bpred import cvw::*; #(parameter cvw_t P) ( if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GSHARE) begin:Predictor gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GLOBAL) begin:Predictor gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GSHARE_BASIC) begin:Predictor gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GLOBAL_BASIC) begin:Predictor gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_BASIC) begin:Predictor localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_AHEAD) begin:Predictor localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirD(BPDirF), .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin:Predictor localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, + .PCNextF, .PCE, .PCM, .BPDirD(BPDirF), .BPDirWrongE, .BranchD, .BranchE, .BranchM, .PCSrcE); end @@ -185,7 +185,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) BPWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPWrongM); // Output the predicted PC or corrected PC on miss-predict. - assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF; + assign BPPCSrcF = (BPBranchF & BPDirF[1]) | BPJumpF; mux2 #(P.XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF); // Selects the BP or PC+2/4. mux2 #(P.XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF); @@ -217,8 +217,8 @@ module bpred import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPDirPredWrongE, RASPredPCWrongE}, - {BPDirPredWrongM, RASPredPCWrongM}); + {BPDirWrongE, RASPredPCWrongE}, + {BPDirWrongM, RASPredPCWrongM}); assign BTAWrongM = BPBTAWrongM & PCSrcM; diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 9192a7cf5..149b2f353 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -37,8 +37,8 @@ module gshare import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE @@ -47,8 +47,8 @@ module gshare import cvw::*; #(parameter cvw_t P, logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchX; - logic [1:0] PHTBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + logic [1:0] PHTBPDirF, BPDirD, BPDirE, FwdNewDirPredF; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW; @@ -78,33 +78,33 @@ module gshare import cvw::*; #(parameter cvw_t P, assign MatchW = BranchW & ~FlushW & (IndexF == IndexW); assign MatchX = MatchD | MatchE | MatchM | MatchW; - assign FwdNewDirPredF = MatchD ? {2{BPDirPredD[1]}} : - MatchE ? {NewBPDirPredE} : - MatchM ? {NewBPDirPredM} : - NewBPDirPredW ; + assign FwdNewDirPredF = MatchD ? {2{BPDirD[1]}} : + MatchE ? {NewBPDirE} : + MatchM ? {NewBPDirM} : + NewBPDirW ; - assign BPDirPredF = MatchX ? FwdNewDirPredF : PHTBPDirPredF; + assign BPDirF = MatchX ? FwdNewDirPredF : PHTBPDirF; ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(PHTBPDirPredF), + .rd1(PHTBPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; - assign GHRNextF = BPBranchF ? {BPDirPredF[1], GHRF[k-1:1]} : GHRF; - assign GHRF = BranchD ? {BPDirPredD[1], GHRD[k-1:1]} : GHRD; + assign GHRNextF = BPBranchF ? {BPDirF[1], GHRF[k-1:1]} : GHRF; + assign GHRF = BranchD ? {BPDirD[1], GHRD[k-1:1]} : GHRD; assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE; assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM; diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 1fa6f21f6..61c3f55f0 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -36,16 +36,16 @@ module gsharebasic import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; logic [k-1:0] GHRNext; @@ -62,19 +62,19 @@ module gsharebasic import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR; flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR); diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index fd8acbc82..5d290e85e 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -34,18 +34,18 @@ module localaheadbp import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredD, - output logic BPDirPredWrongE, + output logic [1:0] BPDirD, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - //logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] BPDirPredE; - logic [1:0] BPDirPredM; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + //logic [1:0] BPDirD, BPDirE; + logic [1:0] BPDirE; + logic [1:0] BPDirM; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF; logic [k-1:0] LHRNextW; @@ -63,21 +63,21 @@ module localaheadbp import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), - .rd1(BPDirPredD), + .rd1(BPDirD), .wa2(IndexM), - .wd2(NewBPDirPredW), + .wd2(NewBPDirW), .we2(BranchM), .bwe2(1'b1)); - //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); - flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM); + //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); + flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirE, BPDirM); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM)); - //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM)); + //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 5c4485f3f..c2f3fdff3 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -35,16 +35,16 @@ module localbpbasic import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHR; logic [k-1:0] LHRNextW; @@ -60,19 +60,19 @@ module localbpbasic import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index f953da0de..dac13fd44 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -34,17 +34,17 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredD, - output logic BPDirPredWrongE, + output logic [1:0] BPDirD, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCE, PCM, input logic BranchD, BranchE, BranchM, PCSrcE ); - //logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] BPDirPredE; - logic [1:0] BPDirPredM; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + //logic [1:0] BPDirD, BPDirE; + logic [1:0] BPDirE; + logic [1:0] BPDirM; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF; logic [k-1:0] LHRNextW; @@ -62,21 +62,21 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), - .rd1(BPDirPredD), + .rd1(BPDirD), .wa2(LHRW), - .wd2(NewBPDirPredW), + .wd2(NewBPDirW), .we2(BranchM), .bwe2(1'b1)); - //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); - flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM); + //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); + flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirE, BPDirM); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM)); - //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM)); + //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without @@ -100,7 +100,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, .bwe2('1)); assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]}; - assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE; + assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE; // *** replace with a small CAM ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk), .ce1(~StallF), .ce2(~StallE & ~FlushE), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5c054175f..b65fdde7e 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -34,8 +34,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, input logic [XLEN-1:0] PCNextF, PCM, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, input logic BranchE, BranchM, input logic PCSrcE ); @@ -43,8 +43,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, logic [k-1:0] IndexNextF, IndexM; logic [1:0] PredictionMemory; logic DoForwarding, DoForwardingF; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; // hashing function for indexing the PC // We have k bits to index, but XLEN bits as the input. @@ -57,19 +57,19 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); endmodule diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 25ac436af..6a223c099 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -66,7 +66,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] PCM, // Memory stage instruction address // branch predictor output logic [3:0] IClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - output logic BPDirPredWrongM, // Prediction direction is wrong + output logic BPDirWrongM, // Prediction direction is wrong output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong output logic IClassWrongM, // Class prediction is wrong @@ -343,7 +343,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BranchD, .BranchE, .JumpD, .JumpE, .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE, .PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM); + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM); end else begin : bpred mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF)); @@ -359,7 +359,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BPReturnWrongD()); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM); assign RASPredPCWrongM = 1'b0; - assign BPDirPredWrongM = BPWrongM; + assign BPDirWrongM = BPWrongM; assign BTAWrongM = BPWrongM; assign IClassM = {CallM, ReturnM, JumpM, BranchM}; assign NextValidPCE = PCE; diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fac432251..af4dd0dd0 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -57,7 +57,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic LoadStallD, StoreStallD, input logic ICacheStallF, input logic DCacheStallM, - input logic BPDirPredWrongM, + input logic BPDirWrongM, input logic BTAWrongM, input logic RASPredPCWrongM, input logic IClassWrongM, @@ -276,7 +276,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( if (P.ZICNTR_SUPPORTED) begin:counters csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM, .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index f0704d0cf..e28d6c1a9 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -35,7 +35,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( input logic FlushM, input logic InstrValidNotFlushedM, LoadStallD, StoreStallD, input logic CSRMWriteM, CSRWriteM, - input logic BPDirPredWrongM, + input logic BPDirWrongM, input logic BTAWrongM, input logic RASPredPCWrongM, input logic IClassWrongM, @@ -99,7 +99,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[4] = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[5] = IClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong - assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction + assign CounterEvent[7] = BPDirWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c0dffcaa6..4d46b7aed 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -49,7 +49,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic StoreStallD, // store instruction is stalling input logic ICacheStallF, // I cache stalled input logic DCacheStallM, // D cache stalled - input logic BPDirPredWrongM, // branch predictor guessed wrong direction + input logic BPDirWrongM, // branch predictor guessed wrong direction input logic BTAWrongM, // branch predictor guessed wrong target input logic RASPredPCWrongM, // return adddress stack guessed wrong target input logic IClassWrongM, // branch predictor guessed wrong instruction class @@ -137,7 +137,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, .IClassWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 6ef3e2a54..c0bae7af0 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -146,7 +146,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LSUHREADY; logic BPWrongE, BPWrongM; - logic BPDirPredWrongM; + logic BPDirWrongM; logic BTAWrongM; logic RASPredPCWrongM; logic IClassWrongM; @@ -181,7 +181,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM, // Mem .CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirPredWrongM, + .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, // Faults out .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM, @@ -291,7 +291,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, .StoreStallD, - .BPDirPredWrongM, .BTAWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .BPWrongM, .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, From 0ca10e7ee2e3e2feaec797e8b0defcc18f14f9cf Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 2 Jun 2024 17:01:51 -0500 Subject: [PATCH 02/19] Last of the branch predictor signal name updates. --- src/ifu/bpred/RASPredictor.sv | 6 +++--- src/ifu/bpred/gshare.sv | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 5129e9043..f045533e3 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -52,7 +52,7 @@ module RASPredictor import cvw::*; #(parameter cvw_t P)( logic RepairD; logic IncrRepairD, DecRepairD; - logic DecrementPtr; + logic DecPtr; logic FlushedReturnDE; logic WrongPredReturnD; @@ -71,11 +71,11 @@ module RASPredictor import cvw::*; #(parameter cvw_t P)( assign CounterEn = PopF | PushE | RepairD; - assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; + assign DecPtr = (PopF | DecRepairD) & ~IncrRepairD; assign P1 = 1; assign M1 = '1; // -1 - mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr); + mux2 #(Depth) PtrMux(P1, M1, DecPtr, IncDecPtr); logic [Depth-1:0] Sum; assign Sum = Ptr + IncDecPtr; if(|P.RAS_SIZE[Depth-1:0]) diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 149b2f353..f17156c25 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -47,7 +47,7 @@ module gshare import cvw::*; #(parameter cvw_t P, logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchX; - logic [1:0] PHTBPDirF, BPDirD, BPDirE, FwdNewDirPredF; + logic [1:0] PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF; logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW; @@ -78,12 +78,12 @@ module gshare import cvw::*; #(parameter cvw_t P, assign MatchW = BranchW & ~FlushW & (IndexF == IndexW); assign MatchX = MatchD | MatchE | MatchM | MatchW; - assign FwdNewDirPredF = MatchD ? {2{BPDirD[1]}} : + assign FwdNewBPDirF = MatchD ? {2{BPDirD[1]}} : MatchE ? {NewBPDirE} : MatchM ? {NewBPDirM} : NewBPDirW ; - assign BPDirF = MatchX ? FwdNewDirPredF : PHTBPDirF; + assign BPDirF = MatchX ? FwdNewBPDirF : PHTBPDirF; ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), From c5dac4d7750e01dbea0693df4a67873c2142d731 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 09:28:21 -0700 Subject: [PATCH 03/19] Removed *** from fpga top. --- fpga/src/fpgaTop.sv | 3 +-- fpga/src/fpgaTopArtyA7.sv | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index f07bd5240..20ffd4b08 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -496,8 +496,7 @@ module fpgaTop .UARTSin, .UARTSout, .SDCIntr); - // // wally - // // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc + // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented // wallypipelinedsocwrapper wallypipelinedsocwrapper // (.clk(CPUCLK), // .reset_ext(bus_struct_reset), diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 20e8adb81..676eaae79 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -485,7 +485,7 @@ module fpgaTop .peripheral_aresetn(peripheral_aresetn)); // wally - // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc + // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented `include "parameter-defs.vh" From ab1ee3d69b4f72a1d54d13695203467a27fe299b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 09:40:35 -0700 Subject: [PATCH 04/19] Removed *** from IFU, lrcs. --- fpga/src/fpgaTopArtyA7.sv | 1 - sim/vcs/run_vcs | 2 +- src/ebu/buscachefsm.sv | 1 - src/generic/clockgater.sv | 50 --------------------------------------- src/lsu/lrsc.sv | 1 - 5 files changed, 1 insertion(+), 54 deletions(-) delete mode 100644 src/generic/clockgater.sv diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 676eaae79..9ddf958a7 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1048,7 +1048,6 @@ module fpgaTop .sys_rst(resetn), // omg. this is active low?!?!?? .mmcm_locked(mmcm_locked), - // *** What are these? .app_sr_req(1'b0), // reserved command .app_ref_req(1'b0), // refresh command .app_zq_req(1'b0), // recalibrate command diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 597907a8e..5601e57b2 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -86,7 +86,7 @@ INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ") INCLUDE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +incdir+../../tests +define+ +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" # Prepare RTL files avoiding certain paths -RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" +RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")" # Simulation and Coverage Commands OUTPUT="sim_out" diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 5f39e1602..623d17975 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -128,7 +128,6 @@ module buscachefsm #( assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) | - //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. (CurrState == DATA_PHASE) | (CurrState == ATOMIC_PHASE) | (CurrState == ATOMIC_READ_DATA_PHASE) | diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv deleted file mode 100644 index 48282ccfa..000000000 --- a/src/generic/clockgater.sv +++ /dev/null @@ -1,50 +0,0 @@ -/////////////////////////////////////////// -// clockgater.sv -// -// Written: Ross Thompson 9 January 2021 -// Modified: -// -// Purpose: Clock gater model. Must use standard cell for synthesis. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module clockgater #(parameter FPGA) ( - input logic E, - input logic SE, - input logic CLK, - output logic ECLK -); - - if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK)); - else begin - // *** BUG - // VERY IMPORTANT. - // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would. - // Do not use this in synthesis! - logic enable_q; - always_latch begin - if(~CLK) begin - enable_q <= E | SE; - end - end - assign ECLK = enable_q & CLK; - end - -endmodule diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 437907e55..20d3cb8f6 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -45,7 +45,6 @@ module lrsc import cvw::*; #(parameter cvw_t P) ( localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8; localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64 - // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest. // Handle atomic load reserved / store conditional logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] ReservationPAdrW; logic ReservationValidM, ReservationValidW; From cc58bfdcf3a5cde1b5c95a0c8d83b272c4e93a5e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 09:49:17 -0700 Subject: [PATCH 05/19] Removed more *** from the ifu. --- src/ifu/ifu.sv | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 7f70e91a3..4a9281dfc 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -211,9 +211,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // delay the interrupt until the LSU is in a clean state. assign CommittedF = CacheCommittedF | BusCommittedF; - logic IgnoreRequest; // *** unused; RT: is this a bug or delete? - assign IgnoreRequest = ITLBMissF | FlushD; - // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (P.IROM_SUPPORTED) begin : irom logic IROMce; @@ -226,8 +223,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( end if (P.BUS_SUPPORTED) begin : bus // **** must fix words per line vs beats per line as in lsu. - localparam WORDSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.XLEN : 1; - localparam LOGBWPL = P.ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1; + localparam BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1; + localparam AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1; if(P.ICACHE_SUPPORTED) begin : icache localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) @@ -240,7 +237,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // *** RT: PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE. cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), - .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) + .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), @@ -256,7 +253,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, BEATSPERLINE, AHBWLOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), From f0e5bbef0cd5ca29ef57475eaf0237cec808a515 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 09:52:40 -0700 Subject: [PATCH 06/19] Removed remaining *** from IFU. --- src/ifu/ifu.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 4a9281dfc..aba53e198 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -222,7 +222,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign IROMInstrF = '0; end if (P.BUS_SUPPORTED) begin : bus - // **** must fix words per line vs beats per line as in lsu. localparam BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1; localparam AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1; @@ -234,7 +233,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; - // *** RT: PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE. cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) From 4911642427f7c8fe78dc9462aa6ccfb31a4cc1af Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 10:31:44 -0700 Subject: [PATCH 07/19] Removed *** and updated comments for bpred and align. --- src/ifu/bpred/bpred.sv | 1 - src/ifu/bpred/localrepairbp.sv | 4 ++-- src/lsu/align.sv | 9 +++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 470dc649d..da8a7a2a2 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -219,7 +219,6 @@ module bpred import cvw::*; #(parameter cvw_t P) ( assign {BTAWrongM, RASPredPCWrongM} = 0; end - // **** Fix me assign IClassM = {CallM, ReturnM, JumpM, BranchM}; endmodule diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index dac13fd44..7294816a1 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -101,7 +101,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]}; assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE; - // *** replace with a small CAM + // RT: TODO active research: replace with a small CAM, quantify benefit ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk), .ce1(~StallF), .ce2(~StallE & ~FlushE), .ra1(IndexLHRNextF), @@ -110,7 +110,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, .wd2(LHRNextE), .we2(BranchD), .bwe2('1)); - // **** replace with small CAM + // RT: TODO active research: replace with small CAM, quantify benefit logic [2**m-1:0] FlushedBits; always_ff @(posedge clk) begin // Valid bit array, SpeculativeFlushedF <= FlushedBits[IndexLHRNextF]; diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 25a2c99d7..db37f4a66 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -76,6 +76,8 @@ module align import cvw::*; #(parameter cvw_t P) ( logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; logic [$clog2(LLENINBYTES)+2:0] ShiftAmount; logic PotentialSpillM; + logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; + /* verilator lint_off WIDTHEXPAND */ assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; @@ -152,10 +154,9 @@ module align import cvw::*; #(parameter cvw_t P) ( assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount; assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0]; - // write path. Also has the 8:1 shifter muxing for the byteoffset - // then it also has the mux to select when a spill occurs - logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM; // *** RT: Find a better way. I've extending in both directions so we don't shift in zeros. The cache expects the writedata to not have any zero data, but instead replicated data. - + // write path. + // 3*LLEN to 2*LLEN funnel shifter to perform left rotation. + // Vivado correctly optimizes as 2*LLEN log2(LLEN):1 muxes assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount; assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN]; From 5e5ca0809f1b1b4ff52d5d357e0791873756e1eb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 10:52:51 -0700 Subject: [PATCH 08/19] Removed more *** from lsu and updated assertions for dtim. --- src/lsu/dtim.sv | 1 - src/lsu/lsu.sv | 7 ++----- testbench/common/riscvassertions.sv | 3 ++- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 5bd46deb9..f46bcbd20 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -33,7 +33,6 @@ module dtim import cvw::*; #(parameter cvw_t P) ( input logic FlushW, input logic ce, // Chip Enable. 0: Holds ReadDataWordM input logic [1:0] MemRWM, // Read/Write control - input logic [1:0] MemRWE, // Read/Write control input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 58339b0a7..9375645fd 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -245,7 +245,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM), .StoreAmoPageFaultM(LSUStoreAmoPageFaultM), - .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, // *** these faults need to be supressed during hptw. + .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .UpdateDA(DataUpdateDAM), .CMOpM(CMOpM), .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), .WriteAccessM, .ReadAccessM(PreLSURWM[1]), @@ -279,10 +279,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr); assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : 0; - // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. - // **** create config to support DTIM with floating point. - // Add support for cboz - dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE + dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 1f8af3dda..404353909 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -59,12 +59,13 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZIHPM_SUPPORTED == 0) | (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); assert ((P.ZICBOM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED"); assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED"); + assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DTIM_SUPPORTED == 0)) else $fatal(1, "ZICBOZ incompatible with DTIM"); assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA"); assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32"); assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); - assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); + assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); end endmodule From 77523c52c20a2ac835264a5b67b20d8ce17ad2f2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 10:56:07 -0700 Subject: [PATCH 09/19] LSU no longer has ***. --- src/lsu/lsu.sv | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9375645fd..9fed86cc0 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -351,11 +351,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM)); - - // Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM - // Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times. - // *** DTIMReadDataWordM should be increased to LLEN. - // pma should generate exception for LLEN read to periph. mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}), .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}), .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM)); @@ -374,7 +369,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Mux between the 2 sources of read data, 0: Bus, 1: DTIM if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); - else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats. + else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; assign LSUHBURST = 3'b0; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0; end From 71f267a17a5d66ed79a7e226f17b45e685bef468 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 11:09:49 -0700 Subject: [PATCH 10/19] Added InstrUpdateDAF to the HPTW. --- src/mmu/hptw.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 5952266e5..5e6b99e4d 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -49,7 +49,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( input logic ITLBMissF, input logic DTLBMissM, input logic FlushW, - input logic InstrUpdateDAF, // *** unused; RT, can we delete or is this a bug? + input logic InstrUpdateDAF, input logic DataUpdateDAM, output logic [P.XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs @@ -95,6 +95,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic SelHPTWAdr; logic [P.XLEN+1:0] HPTWAdrExt; logic DTLBMissOrUpdateDAM; + logic ITLBMissOrUpdateDAF; logic LSUAccessFaultM; logic [P.PA_BITS-1:0] HPTWAdr; logic [1:0] HPTWRW; @@ -138,7 +139,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0]; - assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissF); + assign TLBMiss = DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF; // Determine which address to translate mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr); @@ -324,6 +325,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); + assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF); // HTPW address/data/control muxing From 24916d42e2fa76c728b33160b7228f68adbf22a5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 11:40:02 -0700 Subject: [PATCH 11/19] Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw. --- src/ifu/ifu.sv | 17 ++++++++++------- src/ifu/spill.sv | 5 ++--- src/lsu/lsu.sv | 11 +++++++---- src/mmu/hptw.sv | 24 +++++++++--------------- src/wally/wallypipelinedcore.sv | 10 ++++------ 5 files changed, 32 insertions(+), 35 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index aba53e198..ed2830868 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -90,8 +90,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_ADUE, // HPTW A/D Update enable input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries - output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk - output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits + output logic ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit output logic InstrAccessFaultF, // Instruction access fault @@ -140,7 +139,9 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic [15:0] InstrRawE, InstrRawM; logic [LINELEN-1:0] FetchBuffer; logic [31:0] ShiftUncachedInstr; - + logic ITLBMissF; + logic InstrUpdateAF; // ITLB hit needs to update dirty or access bits + assign PCFExt = {2'b00, PCSpillF}; ///////////////////////////////////////////////////////////////////////////////////////////// @@ -148,8 +149,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(P.ZCA_SUPPORTED) begin : Spill - spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, - .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); + spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .CacheableF, + .IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCSpillNextF = PCNextF; assign PCSpillF = PCF; @@ -189,15 +190,17 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(), .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(), .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(), - .UpdateDA(InstrUpdateDAF), .CMOpM(4'b0), + .UpdateDA(InstrUpdateAF), .CMOpM(4'b0), .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); + assign ITLBMissOrUpdateAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateAF); end else begin - assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = '0; + assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateAF} = '0; assign PCPF = PCFExt[P.PA_BITS-1:0]; assign CacheableF = 1'b1; assign SelIROM = '0; + assign ITLBMissOrUpdateAF = '0; end //////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 5b82aac76..b2ee6e9e2 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -39,8 +39,7 @@ module spill import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] PCNextF, // The next PCF input logic [31:0] InstrRawF, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed input logic IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched - input logic ITLBMissF, // ITLB miss, ignore memory request - input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) + input logic ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit input logic CacheableF, // Is the instruction from the cache? output logic [P.XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill @@ -86,7 +85,7 @@ module spill import cvw::*; #(parameter cvw_t P) ( end else assign SpillF = PCF[1]; // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits - assign TakeSpillF = SpillF & ~EarlyCompressedF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF)); + assign TakeSpillF = SpillF & ~EarlyCompressedF & ~IFUCacheBusStallF & ~ITLBMissOrUpdateAF; always_ff @(posedge clk) if (reset | FlushD) CurrState <= STATE_READY; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9fed86cc0..7aba958e6 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -86,8 +86,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic ENVCFG_PBMTE, // Page-based memory types enabled input logic ENVCFG_ADUE, // HPTW A/D Update enable input logic [P.XLEN-1:0] PCSpillF, // Fetch PC - input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk - input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits + input logic ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB output logic [1:0] PageType, // Type of page table entry to write to ITLB output logic ITLBWriteF, // Write PTE to ITLB @@ -153,6 +152,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; + logic DTLBMissOrUpdateDAM; + ///////////////////////////////////////////////////////////////////////////////////////////// // Pipeline for IEUAdr E to M @@ -192,8 +193,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(P.VIRTMEM_SUPPORTED) begin : hptw - hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, - .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, + hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF, + .DTLBMissOrUpdateDAM, .DTLBWriteM, .DataUpdateDAM, .FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW, .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN @@ -251,7 +252,9 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .WriteAccessM, .ReadAccessM(PreLSURWM[1]), .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); + assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); end else begin // No MMU, so no PMA/page faults and no address translation + assign DTLBMissOrUpdateDAM = '0; assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0; assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0; assign PAdrM = IHAdrM[P.PA_BITS-1:0]; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 5e6b99e4d..e66ae88fa 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -46,10 +46,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( input logic DCacheBusStallM, // stall from LSU input logic [2:0] Funct3M, input logic [6:0] Funct7M, - input logic ITLBMissF, - input logic DTLBMissM, + input logic ITLBMissOrUpdateAF, + input logic DTLBMissOrUpdateDAM, input logic FlushW, - input logic InstrUpdateDAF, input logic DataUpdateDAM, output logic [P.XLEN-1:0] PTE, // page table entry to TLBs output logic [1:0] PageType, // page type to TLBs @@ -83,7 +82,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic Misaligned, MegapageMisaligned; logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; logic StartWalk; - logic TLBMiss; + logic TLBMissOrUpdateDA; logic PRegEn; logic [1:0] NextPageType; logic [P.SVMODE_BITS-1:0] SvMode; @@ -94,8 +93,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.PA_BITS-1:0] HPTWReadAdr; logic SelHPTWAdr; logic [P.XLEN+1:0] HPTWAdrExt; - logic DTLBMissOrUpdateDAM; - logic ITLBMissOrUpdateDAF; logic LSUAccessFaultM; logic [P.PA_BITS-1:0] HPTWAdr; logic [1:0] HPTWRW; @@ -139,7 +136,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0]; - assign TLBMiss = DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF; + assign TLBMissOrUpdateDA = DTLBMissOrUpdateDAM | ITLBMissOrUpdateAF; // Determine which address to translate mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr); @@ -220,7 +217,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( end // Enable and select signals based on states - assign StartWalk = (WalkerState == IDLE) & TLBMiss; + assign StartWalk = (WalkerState == IDLE) & TLBMissOrUpdateDA; assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD); assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk; assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk; @@ -285,7 +282,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) - IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; + IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; @@ -314,7 +311,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (HPTWFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access. assign SelHPTW = WalkerState != IDLE; // RT 30 May 2023: When there is an access fault caused by the hptw itself, the fsm jumps to FAULT, removes @@ -322,10 +319,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; // *** unused - RT, can we delete? - assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); - - assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); - assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF); + assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); // HTPW address/data/control muxing @@ -349,5 +343,5 @@ module hptw import cvw::*; #(parameter cvw_t P) ( endmodule // another idea. We keep gating the control by ~FlushW, but this adds considerable length to the critical path. -// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives +// should we do this differently? For example TLBMissOrUpdateDA is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives // the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit. diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index a8d30919c..d3589a93a 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -104,7 +104,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // memory management unit signals logic ITLBWriteF; - logic ITLBMissF; + logic ITLBMissOrUpdateAF; logic [P.XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP, STATUS_FS; @@ -162,7 +162,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic DCacheAccess; logic ICacheMiss; logic ICacheAccess; - logic InstrUpdateDAF; logic BigEndianM; logic FCvtIntE; logic CommittedF; @@ -189,9 +188,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM, // mmu management .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, - .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissF, + .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissOrUpdateAF, // pmp/pma (inside mmu) signals. - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF); // integer execution unit: integer register file, datapath and controller ieu #(P) ieu(.clk, .reset, @@ -250,8 +249,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .HPTWInstrPageFaultF, // connects to privilege .StoreAmoMisalignedFaultM, // connects to privilege .StoreAmoAccessFaultM, // connects to privilege - .InstrUpdateDAF, - .PCSpillF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, + .PCSpillF, .ITLBMissOrUpdateAF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu From 9b6b6617afc05e54a3b813cf122e4badb43dcc2e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 12:02:56 -0700 Subject: [PATCH 12/19] Cleaned up hptw. --- src/mmu/hptw.sv | 57 ++++++++++++++++--------------------------------- 1 file changed, 18 insertions(+), 39 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index e66ae88fa..b0835db3f 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -104,7 +104,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay; logic HPTWAccessFaultDelay; logic TakeHPTWFault; - logic [P.XLEN-1:0] ReadDataNoXM; logic PBMTFaultM; logic HPTWFaultM; @@ -171,9 +170,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - //assign ReadDataNoXM = (ReadDataM[0] === 'x) ? 0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. - assign ReadDataNoXM = ReadDataM; // *** temporary fix for synthesis; === and x in line above are not synthesizable. - mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 + mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr); assign SaveHPTWAdr = WalkerState == L0_ADR; @@ -209,7 +206,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 end else begin // block: hptwwrites - assign NextPTE = ReadDataNoXM; + assign NextPTE = ReadDataM; assign HPTWAdr = HPTWReadAdr; assign HPTWUpdateDA = 1'b0; assign UpdatePTE = 1'b0; @@ -265,60 +262,47 @@ module hptw import cvw::*; #(parameter cvw_t P) ( end else begin logic GigapageMisaligned, TerapageMisaligned; assign InitialWalkerState = (SvMode == P.SV48) ? L3_ADR : L2_ADR; - assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0 - assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0 - assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0 + assign TerapageMisaligned = |(CurrentPPN[26:0]); // Must have zero PPN2, PPN1, PPN0 + assign GigapageMisaligned = |(CurrentPPN[17:0]); // Must have zero PPN1 and PPN0 + assign MegapageMisaligned = |(CurrentPPN[8:0]); // Must have zero PPN0 assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned); end // Page Table Walker FSM - // *** there is a bug here (RT). Each memory access needs to be potentially flushed if the PMA/P checkers - // generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation. - // I think the solution is to do 1 of the following - // 1. Allow the HPTW to generate exceptions and stop walking immediately. - // 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back - // to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but - // rather than physical address of the translated instruction/data. So we must generate the exception. flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; - L3_ADR: NextWalkerState = L3_RD; // first access in SV48 + L3_ADR: NextWalkerState = L3_RD; // First access in SV48 L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; - else if(HPTWFaultM) NextWalkerState = FAULT; + else if (HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39 + L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; - else if(HPTWFaultM) NextWalkerState = FAULT; + else if (HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 + L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; - else if(HPTWFaultM) NextWalkerState = FAULT; + else if (HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = L0_ADR; L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (DCacheBusStallM) NextWalkerState = L0_RD; - else if(HPTWFaultM) NextWalkerState = FAULT; + else if (HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = LEAF; LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; - UPDATE_PTE: if(DCacheBusStallM) NextWalkerState = UPDATE_PTE; + UPDATE_PTE: if (DCacheBusStallM) NextWalkerState = UPDATE_PTE; else NextWalkerState = LEAF; FAULT: NextWalkerState = IDLE; - default: NextWalkerState = IDLE; // should never be reached + default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. assign SelHPTW = WalkerState != IDLE; - - // RT 30 May 2023: When there is an access fault caused by the hptw itself, the fsm jumps to FAULT, removes - // stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay. - // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. - - assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; // *** unused - RT, can we delete? assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); // HTPW address/data/control muxing @@ -326,22 +310,17 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // Once the walk is done and it is time to update the TLB we need to switch back // to the orignal data virtual address. assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF); - // always block interrupts when using the hardware page table walker. // multiplex the outputs to LSU - if(P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits - else assign HPTWAdrExt = HPTWAdr; + if (P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // Extend to 66 bits + else assign HPTWAdrExt = HPTWAdr; mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); mux2 #(P.XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM); - if(P.SVADU_SUPPORTED) + if (P.SVADU_SUPPORTED) mux2 #(P.XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM); else assign IHWriteDataM = WriteDataM; endmodule - -// another idea. We keep gating the control by ~FlushW, but this adds considerable length to the critical path. -// should we do this differently? For example TLBMissOrUpdateDA is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives -// the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit. From 576f1b9e5940446703ec8c00f2126703a6a69176 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 12:31:24 -0700 Subject: [PATCH 13/19] Moved the *** from trap to an issue. --- src/privileged/trap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 247bfe678..95ae26e1a 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -88,7 +88,7 @@ module trap import cvw::*; #(parameter cvw_t P) ( BreakpointFaultM | EcallFaultM | LoadAccessFaultM | StoreAmoAccessFaultM; // coverage on - assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter. + assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; /////////////////////////////////////////// // Cause priority defined in privileged spec From 91c844ca450ce66f0c01134831f23d5e0aada9c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 12:31:50 -0700 Subject: [PATCH 14/19] Removed more *** from camline and csrc. --- src/mmu/tlb/tlbcamline.sv | 4 +--- src/privileged/csrc.sv | 14 ++++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 057c8766b..e66c22da2 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -41,7 +41,7 @@ module tlbcamline import cvw::*; #(parameter cvw_t P, input logic PTE_NAPOT, // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000) input logic [1:0] PageTypeWriteVal, input logic TLBFlush, // Flush this line (set valid to 0) - output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one? + output logic [1:0] PageTypeRead, output logic Match ); @@ -102,8 +102,6 @@ module tlbcamline import cvw::*; #(parameter cvw_t P, // On a write, set the valid bit high and update the stored key. // On a flush, zero the valid bit and leave the key unchanged. - // *** Might we want to update stored key right away to output match on the - // write cycle? (using a mux) flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid); flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key); endmodule diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index e992ee526..d8ce0e709 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -95,11 +95,13 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters - assign CounterEvent[3] = IClassM[0] & InstrValidNotFlushedM; // branch instruction - assign CounterEvent[4] = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM; // jump and not return instructions - assign CounterEvent[5] = IClassM[2] & InstrValidNotFlushedM; // return instructions + // Ideally all events would be counted in the M stage, but the pipelining is costly. The counters may + // count an event in a previous pipeline stage. + assign CounterEvent[3] = IClassM[0] & InstrValidNotFlushedM; // branch instruction + assign CounterEvent[4] = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM; // jump and not return instructions + assign CounterEvent[5] = IClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong - assign CounterEvent[7] = BPDirWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction + assign CounterEvent[7] = BPDirWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong @@ -117,8 +119,8 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[22] = InterruptM; // interrupt, InstrValidNotFlushedM will be low assign CounterEvent[23] = ExceptionM; // exceptions, InstrValidNotFlushedM will be low // coverage off - // DivBusyE will never be assert high since this configuration uses the FPU to do integer division - assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle + // DivBusyE will never be asserted high because the RV64GC configuration uses the FPU to do integer division + assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles // coverage on assign CounterEvent[P.COUNTERS-1:25] = '0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end else begin: cevent From 7f0ba8723140d88871252921d732b5b96c7f8255 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 13:51:30 -0700 Subject: [PATCH 15/19] Updated comments in uart. --- src/uncore/uartPC16550D.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index 7b27ef8e7..31172462d 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -149,11 +149,11 @@ module uartPC16550D #(parameter UART_PRESCALE) ( if (~PRESETn) begin // Table 3 Reset Configuration IER <= 4'b0; FCR <= 8'b0; - LCR <= 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed. + LCR <= 8'b11; // PC16550D datasheet resets to 0, but all modern systems will use 8-bit data. Wally resets to 3 for 8-bit data. MCR <= 5'b0; - LSR <= 8'b01100000; + LSR <= 8'b0110_0000; MSR <= 4'b0; - DLL <= 8'd1; // this cannot be zero with DLM also zer0. + DLL <= 8'd1; // this cannot be zero with DLM also zero. DLM <= 8'b0; SCR <= 8'b0; // not strictly necessary to reset end else begin From d368f2e77e20f6601ed4fa08d6e894029bedd705 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 13:51:37 -0700 Subject: [PATCH 16/19] Removed *** from testbench. --- testbench/testbench.sv | 37 ++++++++++++++----------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index eed068f54..22804872e 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -438,12 +438,12 @@ module testbench; // clear signature to prevent contamination from previous tests if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); - else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution + else if (TEST != "embench") begin CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); if(errors > 0) totalerrors = totalerrors + 1; end end - test = test + 1; // *** this probably needs to be moved. + test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); @@ -568,8 +568,8 @@ module testbench; end if(P.SDC_SUPPORTED) begin : sdcard - // *** fix later -/* -----\/----- EXCLUDED -----\/----- + // JP: Add back sd card when sd card AHB implementation done + /* -----\/----- EXCLUDED -----\/----- sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -579,7 +579,7 @@ module testbench; assign SDCCmdIn = SDCCmd; assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; - -----/\----- EXCLUDED -----/\----- */ + -----/\----- EXCLUDED -----/\----- */ assign SDCIntr = 1'b0; end else begin assign SDCIntr = 1'b0; @@ -632,10 +632,8 @@ module testbench; loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST); // track the current function or global label - if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName - FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), - .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); - end + FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), + .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); // Append UART output to file for tests if (P.UART_SUPPORTED) begin: uart_logger @@ -650,21 +648,14 @@ module testbench; end // Termination condition - // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed - // or sw gp,-56(t0) for new Imperas tests - // or sd gp, -56(t0) - // or on a jump to self infinite loop (6f) for RISC-V Arch tests - logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls - if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; - else assign ecf = 0; + // Terminate on + // 1. jump to self loop (0x0000006f) + // 2. a store word writes to the address "tohost" + // 3. or PC is stuck at 0 always_comb begin - TestComplete = ecf & - (dut.core.ieu.dp.regf.rf[3] == 1 | - (dut.core.ieu.dp.regf.we3 & - dut.core.ieu.dp.regf.a3 == 3 & - dut.core.ieu.dp.regf.wd3 == 1)) | - ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" ); + TestComplete = ((InstrM == 32'h6f) & dut.core.InstrValidM ) | + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" ) | + (FunctionName.PCM == 4 & dut.core.ieu.c.InstrValidM); end DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); From 64712d2243fff78642a9468de4ab02e54775b0a4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 13:51:50 -0700 Subject: [PATCH 17/19] Updated wave to match changes in testbench. --- sim/questa/wave.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index e11f7eb02..881100601 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -205,7 +205,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM From 2d8973df1d1f58aae7f91f3bca756392572a9d44 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 13:57:28 -0700 Subject: [PATCH 18/19] Updated wavefile to use new names. --- sim/questa/wave.do | 90 ++++++++++++++++++++++------------------------ 1 file changed, 43 insertions(+), 47 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 881100601..c6cc26f9c 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -73,7 +73,6 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpre add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} @@ -91,7 +90,7 @@ add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST @@ -123,50 +122,50 @@ add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/c add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr @@ -240,7 +239,7 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/z add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask @@ -282,7 +281,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn @@ -297,68 +295,67 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} @@ -387,7 +384,7 @@ add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/d add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM @@ -417,7 +414,6 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hp add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM From 685f4d3807b173ea2ac620e5af069abd709ab120 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jun 2024 14:00:31 -0700 Subject: [PATCH 19/19] Removed the last of the ***. --- src/fpu/fctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 4f1bf042b..8595fd29e 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -242,7 +242,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( // coverage off // Not covered in testing because rv64gc is not RV64Q or RV32D 7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) - ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong + ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.d.x (Zfa) 7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.q.x (Zfa) // coverage on