Fixed lint errors in postprocessing

This commit is contained in:
cturek 2022-11-15 20:31:23 +00:00
parent 3df51716b1
commit 98b66aab9f

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@ -45,12 +45,13 @@ module fdivsqrtpostproc(
output logic DivSM output logic DivSM
); );
logic [`DIVb+3:0] W, Sum; logic [`DIVb+3:0] W, Sum, RemD;
logic [`DIVb:0] PreQmM; logic [`DIVb:0] PreQmM;
logic NegSticky, PostInc; logic NegSticky, PostInc;
logic weq0; logic weq0;
logic [`DIVBLEN:0] NormShift; logic [`DIVBLEN:0] NormShift;
logic [`DIVb:0] IntQuot, IntRem, NormQuot, NormRem; logic [`DIVb:0] IntQuot, NormQuot;
logic [`DIVb+3:0] IntRem, NormRem;
logic [`DIVb:0] PreResult, Result; logic [`DIVb:0] PreResult, Result;
// check for early termination on an exact result. If the result is not exact, the sticky should be set // check for early termination on an exact result. If the result is not exact, the sticky should be set
@ -76,7 +77,7 @@ module fdivsqrtpostproc(
assign Sum = WC + WS; assign Sum = WC + WS;
assign W = $signed(Sum) >>> `LOGR; assign W = $signed(Sum) >>> `LOGR;
assign NegSticky = W[`DIVb+3]; assign NegSticky = W[`DIVb+3];
assign RemD = {4'b0000, D, {(`DIVb-`DIVN){1'b0}}}; assign RemD = {4'b0000, D, {(`DIVb-`DIVN+1){1'b0}}};
always_comb always_comb
if (~As) if (~As)
@ -134,8 +135,8 @@ module fdivsqrtpostproc(
*/ */
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); // assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp);
assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;