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Fixed lint errors in postprocessing
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3df51716b1
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@ -45,12 +45,13 @@ module fdivsqrtpostproc(
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output logic DivSM
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output logic DivSM
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);
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);
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logic [`DIVb+3:0] W, Sum;
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logic [`DIVb+3:0] W, Sum, RemD;
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logic [`DIVb:0] PreQmM;
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logic [`DIVb:0] PreQmM;
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logic NegSticky, PostInc;
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logic NegSticky, PostInc;
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logic weq0;
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logic weq0;
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logic [`DIVBLEN:0] NormShift;
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logic [`DIVBLEN:0] NormShift;
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logic [`DIVb:0] IntQuot, IntRem, NormQuot, NormRem;
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logic [`DIVb:0] IntQuot, NormQuot;
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logic [`DIVb+3:0] IntRem, NormRem;
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logic [`DIVb:0] PreResult, Result;
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logic [`DIVb:0] PreResult, Result;
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// check for early termination on an exact result. If the result is not exact, the sticky should be set
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// check for early termination on an exact result. If the result is not exact, the sticky should be set
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@ -76,7 +77,7 @@ module fdivsqrtpostproc(
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assign Sum = WC + WS;
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assign Sum = WC + WS;
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assign W = $signed(Sum) >>> `LOGR;
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assign W = $signed(Sum) >>> `LOGR;
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assign NegSticky = W[`DIVb+3];
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assign NegSticky = W[`DIVb+3];
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assign RemD = {4'b0000, D, {(`DIVb-`DIVN){1'b0}}};
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assign RemD = {4'b0000, D, {(`DIVb-`DIVN+1){1'b0}}};
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always_comb
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always_comb
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if (~As)
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if (~As)
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@ -134,8 +135,8 @@ module fdivsqrtpostproc(
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*/
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*/
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// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
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assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp);
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// assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp);
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assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
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assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
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assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
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assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
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