mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #1059 from jordancarlin/fetch_buffer
Fetch buffer passes regression!
This commit is contained in:
David Harris
GitHub
commit
98a89d767b
@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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@ -72,130 +72,130 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
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add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
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add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
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add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
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add wave -noupdate -expand -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
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add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
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add wave -noupdate -expand -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
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add wave -noupdate -group ifu -group Bpred -divider {class check}
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add wave -noupdate -expand -group ifu -group Bpred -divider {class check}
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add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -expand -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -expand -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
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add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
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add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
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add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF
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add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
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add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
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add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
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add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
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add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage
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add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
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add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCPF
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess
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add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
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add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
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add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
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add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
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add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage
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add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage
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add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn
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add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn
|
||||||
add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate
|
add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate
|
||||||
add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]}
|
add wave -noupdate -expand -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]}
|
||||||
add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU
|
add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU
|
||||||
add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
|
add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
|
||||||
add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
|
add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
|
add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
|
add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
|
add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
|
add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
|
add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
|
add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
|
add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
|
add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
|
||||||
add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM}
|
add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM}
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
|
||||||
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
|
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
|
||||||
add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
|
add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
|
||||||
add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RdD
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/RdD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs1D
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/Rs1D
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs2D
|
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/c/Rs2D
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||||
@ -215,13 +215,11 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
|||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||||
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||||
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB
|
|
||||||
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW
|
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW
|
||||||
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM
|
add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||||
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||||
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||||
@ -666,9 +664,33 @@ add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge
|
|||||||
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active
|
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active
|
||||||
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData
|
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData
|
||||||
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg
|
add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/StallD
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/FlushD
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/WriteData
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/ReadData
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/FetchBufferStallF
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/Readf1
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/Readf0
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/Readf2
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/ReadFetchBuffer
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} -radix binary /testbench/dut/core/ifu/fetchbuff/ReadPtr
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} -radix binary /testbench/dut/core/ifu/fetchbuff/WritePtr
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/Empty
|
||||||
|
add wave -noupdate -expand -group {fetch buffer} /testbench/dut/core/ifu/fetchbuff/Full
|
||||||
|
add wave -noupdate -expand -group f0 /testbench/dut/core/ifu/fetchbuff/f0/en
|
||||||
|
add wave -noupdate -expand -group f0 /testbench/dut/core/ifu/fetchbuff/f0/d
|
||||||
|
add wave -noupdate -expand -group f0 /testbench/dut/core/ifu/fetchbuff/f0/q
|
||||||
|
add wave -noupdate -expand -group f0 /testbench/dut/core/ifu/fetchbuff/f0/clk
|
||||||
|
add wave -noupdate -expand -group f0 /testbench/dut/core/ifu/fetchbuff/f0/reset
|
||||||
|
add wave -noupdate -expand -group f2 /testbench/dut/core/ifu/fetchbuff/f1/en
|
||||||
|
add wave -noupdate -expand -group f2 /testbench/dut/core/ifu/fetchbuff/f1/d
|
||||||
|
add wave -noupdate -expand -group f2 /testbench/dut/core/ifu/fetchbuff/f1/q
|
||||||
|
add wave -noupdate -expand -group f3 /testbench/dut/core/ifu/fetchbuff/f2/en
|
||||||
|
add wave -noupdate -expand -group f3 /testbench/dut/core/ifu/fetchbuff/f2/d
|
||||||
|
add wave -noupdate -expand -group f3 /testbench/dut/core/ifu/fetchbuff/f2/q
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1}
|
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {392 ns} 1} {{Cursor 4} {223860 ns} 1} {{Cursor 5} {404 ns} 0}
|
||||||
quietly wave cursor active 3
|
quietly wave cursor active 5
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 194
|
configure wave -valuecolwidth 194
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -683,4 +705,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {1130 ns} {1230 ns}
|
WaveRestoreZoom {371 ns} {471 ns}
|
||||||
|
|||||||
@ -2,32 +2,32 @@
|
|||||||
// hazard.sv
|
// hazard.sv
|
||||||
//
|
//
|
||||||
// Written: David_Harris@hmc.edu 9 January 2021
|
// Written: David_Harris@hmc.edu 9 January 2021
|
||||||
// Modified:
|
// Modified:
|
||||||
//
|
//
|
||||||
// Purpose: Determine stalls and flushes
|
// Purpose: Determine stalls and flushes
|
||||||
//
|
//
|
||||||
// Documentation: RISC-V System on Chip Design
|
// Documentation: RISC-V System on Chip Design
|
||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
module hazard import cvw::*; #(parameter cvw_t P) (
|
module hazard import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
|
input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
|
||||||
input logic StructuralStallD,
|
input logic StructuralStallD,
|
||||||
input logic LSUStallM, IFUStallF, FetchBufferStallF,
|
input logic LSUStallM, IFUStallF, FetchBufferStallF,
|
||||||
@ -48,7 +48,7 @@ module hazard import cvw::*; #(parameter cvw_t P) (
|
|||||||
// WFI logic
|
// WFI logic
|
||||||
assign WFIStallM = wfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout
|
assign WFIStallM = wfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout
|
||||||
assign WFIInterruptedM = wfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled.
|
assign WFIInterruptedM = wfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled.
|
||||||
|
|
||||||
// stalls and flushes
|
// stalls and flushes
|
||||||
// loads: stall for one cycle if the subsequent instruction depends on the load
|
// loads: stall for one cycle if the subsequent instruction depends on the load
|
||||||
// branches and jumps: flush the next two instructions if the branch is taken in EXE
|
// branches and jumps: flush the next two instructions if the branch is taken in EXE
|
||||||
@ -62,7 +62,7 @@ module hazard import cvw::*; #(parameter cvw_t P) (
|
|||||||
// If any stages are stalled, the first stage that isn't stalled must flush.
|
// If any stages are stalled, the first stage that isn't stalled must flush.
|
||||||
|
|
||||||
// Flush causes
|
// Flush causes
|
||||||
// Traps (TrapM) flush the entire pipeline.
|
// Traps (TrapM) flush the entire pipeline.
|
||||||
// However, breakpoint and ecall traps must finish the writeback stage (commit their results) because these instructions complete before trapping.
|
// However, breakpoint and ecall traps must finish the writeback stage (commit their results) because these instructions complete before trapping.
|
||||||
// Trap returns (RetM) also flush the entire pipeline after the RetM (all stages except W) because all the subsequent instructions must be discarded.
|
// Trap returns (RetM) also flush the entire pipeline after the RetM (all stages except W) because all the subsequent instructions must be discarded.
|
||||||
// Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
|
// Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
|
||||||
@ -77,14 +77,14 @@ module hazard import cvw::*; #(parameter cvw_t P) (
|
|||||||
// Stall causes
|
// Stall causes
|
||||||
// Most data depenency stalls are identified in the decode stage
|
// Most data depenency stalls are identified in the decode stage
|
||||||
// Division stalls in the execute stage
|
// Division stalls in the execute stage
|
||||||
// Flushing any stage has priority over the corresponding stage stall.
|
// Flushing any stage has priority over the corresponding stage stall.
|
||||||
// Even if the register gave clear priority over enable, various FSMs still need to disable the stall, so it's best to gate the stall here with flush
|
// Even if the register gave clear priority over enable, various FSMs still need to disable the stall, so it's best to gate the stall here with flush
|
||||||
// The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.
|
// The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.
|
||||||
// The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
|
// The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
|
||||||
// A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
|
// A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
|
||||||
assign StallFCause = FetchBufferStallF;
|
assign StallFCause = FetchBufferStallF; // | (IFUStallF & ~FlushDCause);
|
||||||
assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
|
assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
|
||||||
assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
|
assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
|
||||||
assign StallMCause = WFIStallM & ~FlushMCause;
|
assign StallMCause = WFIStallM & ~FlushMCause;
|
||||||
// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
|
// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
|
||||||
// assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
|
// assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
|
||||||
@ -101,13 +101,13 @@ module hazard import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign StallW = StallWCause;
|
assign StallW = StallWCause;
|
||||||
|
|
||||||
// detect the first stage that is not stalled
|
// detect the first stage that is not stalled
|
||||||
assign LatestUnstalledD = ~StallD & StallF;
|
assign LatestUnstalledD = 0;
|
||||||
assign LatestUnstalledE = ~StallE & StallD;
|
assign LatestUnstalledE = ~StallE & StallD;
|
||||||
assign LatestUnstalledM = ~StallM & StallE;
|
assign LatestUnstalledM = ~StallM & StallE;
|
||||||
assign LatestUnstalledW = ~StallW & StallM;
|
assign LatestUnstalledW = ~StallW & StallM;
|
||||||
|
|
||||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||||
assign FlushD = LatestUnstalledD | FlushDCause;
|
assign FlushD = LatestUnstalledD | FlushDCause;
|
||||||
assign FlushE = LatestUnstalledE | FlushECause;
|
assign FlushE = LatestUnstalledE | FlushECause;
|
||||||
assign FlushM = LatestUnstalledM | FlushMCause;
|
assign FlushM = LatestUnstalledM | FlushMCause;
|
||||||
assign FlushW = LatestUnstalledW | FlushWCause;
|
assign FlushW = LatestUnstalledW | FlushWCause;
|
||||||
|
|||||||
@ -6,29 +6,29 @@
|
|||||||
// Modified: 3 October 2024
|
// Modified: 3 October 2024
|
||||||
//
|
//
|
||||||
// Purpose: Store multiple instructions in a cyclic FIFO
|
// Purpose: Store multiple instructions in a cyclic FIFO
|
||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
module fetchbuffer import cvw::*; #(parameter cvw_t P) (
|
module fetchbuffer import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic StallD, FlushD,
|
input logic StallF, StallD, FlushD,
|
||||||
input logic [31:0] WriteData,
|
input logic [31:0] WriteData,
|
||||||
output logic [31:0] ReadData,
|
output logic [31:0] ReadData,
|
||||||
output logic FetchBufferStallF
|
output logic FetchBufferStallF
|
||||||
@ -43,22 +43,9 @@ module fetchbuffer import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign FetchBufferStallF = Full;
|
assign FetchBufferStallF = Full;
|
||||||
|
|
||||||
// will go in a generate block once this is parameterized
|
// will go in a generate block once this is parameterized
|
||||||
flopenr #(32) f0 (.clk, .reset(reset | FlushD), .en(WritePtr[0]), .d(WriteData), .q(Readf0));
|
flopenl #(32) f0 (.clk, .load(reset | FlushD), .en(WritePtr[0]), .d(WriteData), .val(nop), .q(Readf0));
|
||||||
flopenr #(32) f1 (.clk, .reset(reset | FlushD), .en(WritePtr[1]), .d(WriteData), .q(Readf1));
|
flopenl #(32) f1 (.clk, .load(reset | FlushD), .en(WritePtr[1]), .d(WriteData), .val(nop), .q(Readf1));
|
||||||
flopenr #(32) f2 (.clk, .reset(reset | FlushD), .en(WritePtr[2]), .d(WriteData), .q(Readf2));
|
flopenl #(32) f2 (.clk, .load(reset | FlushD), .en(WritePtr[2]), .d(WriteData), .val(nop), .q(Readf2));
|
||||||
|
|
||||||
// always_comb begin : readMuxes
|
|
||||||
// // Mux read data from the three registers
|
|
||||||
// case (ReadPtr)
|
|
||||||
// 3'b001: ReadFetchBuffer = Readf0;
|
|
||||||
// 3'b010: ReadFetchBuffer = Readf1;
|
|
||||||
// 3'b100: ReadFetchBuffer = Readf2;
|
|
||||||
// default: ReadFetchBuffer = nop; // just in case?
|
|
||||||
// endcase
|
|
||||||
// // issue nop when appropriate
|
|
||||||
// ReadData = Empty ? nop : ReadFetchBuffer;
|
|
||||||
// end
|
|
||||||
|
|
||||||
|
|
||||||
// Fetch buffer entries anded with read ptr for AO Muxing
|
// Fetch buffer entries anded with read ptr for AO Muxing
|
||||||
logic [31:0] DaoArr [2:0];
|
logic [31:0] DaoArr [2:0];
|
||||||
@ -77,7 +64,7 @@ module fetchbuffer import cvw::*; #(parameter cvw_t P) (
|
|||||||
WritePtr <= 3'b001;
|
WritePtr <= 3'b001;
|
||||||
ReadPtr <= 3'b001;
|
ReadPtr <= 3'b001;
|
||||||
end else begin
|
end else begin
|
||||||
WritePtr <= ~Full ? {WritePtr[1:0], WritePtr[2]} : WritePtr;
|
WritePtr <= ~(Full | StallF) ? {WritePtr[1:0], WritePtr[2]} : WritePtr;
|
||||||
ReadPtr <= ~(StallD | Empty) ? {ReadPtr[1:0], ReadPtr[2]} : ReadPtr;
|
ReadPtr <= ~(StallD | Empty) ? {ReadPtr[1:0], ReadPtr[2]} : ReadPtr;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
103
src/ifu/ifu.sv
103
src/ifu/ifu.sv
@ -6,35 +6,35 @@
|
|||||||
//
|
//
|
||||||
// Purpose: Instruction Fetch Unit
|
// Purpose: Instruction Fetch Unit
|
||||||
// PC, branch prediction, instruction cache
|
// PC, branch prediction, instruction cache
|
||||||
//
|
//
|
||||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
// https://github.com/openhwgroup/cvw
|
// https://github.com/openhwgroup/cvw
|
||||||
//
|
//
|
||||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
//
|
//
|
||||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
//
|
//
|
||||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
// may obtain a copy of the License at
|
// may obtain a copy of the License at
|
||||||
//
|
//
|
||||||
// https://solderpad.org/licenses/SHL-2.1/
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
//
|
//
|
||||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
// either express or implied. See the License for the specific language governing permissions
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
module ifu import cvw::*; #(parameter cvw_t P) (
|
module ifu import cvw::*; #(parameter cvw_t P) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic StallF, StallD, StallE, StallM, StallW,
|
input logic StallF, StallD, StallE, StallM, StallW,
|
||||||
input logic FlushD, FlushE, FlushM, FlushW,
|
input logic FlushD, FlushE, FlushM, FlushW,
|
||||||
output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
|
output logic IFUStallF, // IFU stalsl pipeline during a multicycle operation
|
||||||
// Command from CPU
|
// Command from CPU
|
||||||
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
input logic InvalidateICacheM, // Clears all instruction cache valid bits
|
||||||
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
|
||||||
input logic InstrValidD, InstrValidE,
|
input logic InstrValidD, InstrValidE,
|
||||||
input logic BranchD, BranchE,
|
input logic BranchD, BranchE,
|
||||||
input logic JumpD, JumpE,
|
input logic JumpD, JumpE,
|
||||||
// Bus interface
|
// Bus interface
|
||||||
@ -74,7 +74,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// Faults
|
// Faults
|
||||||
input logic IllegalBaseInstrD, // Illegal non-compressed instruction
|
input logic IllegalBaseInstrD, // Illegal non-compressed instruction
|
||||||
input logic IllegalFPUInstrD, // Illegal FP instruction
|
input logic IllegalFPUInstrD, // Illegal FP instruction
|
||||||
output logic InstrPageFaultF, // Instruction page fault
|
output logic InstrPageFaultF, // Instruction page fault
|
||||||
output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
|
output logic IllegalIEUFPUInstrD, // Illegal instruction including compressed & FP
|
||||||
output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
output logic InstrMisalignedFaultM, // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||||
// mmu management
|
// mmu management
|
||||||
@ -83,7 +83,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
|
input logic [1:0] PageType, // Hardware page table walker (HPTW) writes PageType to ITLB
|
||||||
input logic ITLBWriteF, // Writes PTE and PageType to ITLB
|
input logic ITLBWriteF, // Writes PTE and PageType to ITLB
|
||||||
input logic [P.XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
|
input logic [P.XLEN-1:0] SATP_REGW, // Location of the root page table and page table configuration
|
||||||
input logic STATUS_MXR, // Status CSR: make executable page readable
|
input logic STATUS_MXR, // Status CSR: make executable page readable
|
||||||
input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
|
input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
|
||||||
input logic STATUS_MPRV, // Status CSR: modify machine privilege
|
input logic STATUS_MPRV, // Status CSR: modify machine privilege
|
||||||
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
|
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
|
||||||
@ -93,7 +93,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
output logic ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
|
output logic ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
|
||||||
input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
|
input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
|
||||||
input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
|
input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
|
||||||
output logic InstrAccessFaultF, // Instruction access fault
|
output logic InstrAccessFaultF, // Instruction access fault
|
||||||
output logic ICacheAccess, // Report I$ read to performance counters
|
output logic ICacheAccess, // Report I$ read to performance counters
|
||||||
output logic ICacheMiss, // Report I$ miss to performance counters
|
output logic ICacheMiss, // Report I$ miss to performance counters
|
||||||
// Fetch Buffer
|
// Fetch Buffer
|
||||||
@ -106,7 +106,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
|
logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
|
||||||
logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
|
logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
|
||||||
logic [P.XLEN-1:0] PC2NextF; // Selected PC between branch prediction and next valid PC if CSRWriteFence
|
logic [P.XLEN-1:0] PC2NextF; // Selected PC between branch prediction and next valid PC if CSRWriteFence
|
||||||
logic [P.XLEN-1:0] UnalignedPCNextF; // The next PCF, but not aligned to 2 bytes.
|
logic [P.XLEN-1:0] UnalignedPCNextF; // The next PCF, but not aligned to 2 bytes.
|
||||||
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||||
logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
|
logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
|
||||||
logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
|
logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
|
||||||
@ -115,7 +115,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
|
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
|
||||||
logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
|
logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
|
||||||
logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
|
logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
|
||||||
logic [P.XLEN+1:0] PCFExt;
|
logic [P.XLEN+1:0] PCFExt;
|
||||||
|
|
||||||
logic [31:0] IROMInstrF; // Instruction from the IROM
|
logic [31:0] IROMInstrF; // Instruction from the IROM
|
||||||
logic [31:0] ICacheInstrF; // Instruction from the I$
|
logic [31:0] ICacheInstrF; // Instruction from the I$
|
||||||
@ -124,7 +124,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||||
logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
|
logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
|
||||||
logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good
|
logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good
|
||||||
|
|
||||||
logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
|
logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
|
||||||
logic [31:0] InstrE; // Instruction in the Execution stage
|
logic [31:0] InstrE; // Instruction in the Execution stage
|
||||||
logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
|
logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
|
||||||
@ -143,7 +143,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
logic [31:0] ShiftUncachedInstr;
|
logic [31:0] ShiftUncachedInstr;
|
||||||
logic ITLBMissF;
|
logic ITLBMissF;
|
||||||
logic InstrUpdateAF; // ITLB hit needs to update dirty or access bits
|
logic InstrUpdateAF; // ITLB hit needs to update dirty or access bits
|
||||||
|
|
||||||
assign PCFExt = {2'b00, PCSpillF};
|
assign PCFExt = {2'b00, PCSpillF};
|
||||||
|
|
||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
@ -151,7 +151,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
if(P.ZCA_SUPPORTED) begin : Spill
|
if(P.ZCA_SUPPORTED) begin : Spill
|
||||||
spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .CacheableF,
|
spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .CacheableF,
|
||||||
.IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
|
.IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
|
||||||
end else begin : NoSpill
|
end else begin : NoSpill
|
||||||
assign PCSpillNextF = PCNextF;
|
assign PCSpillNextF = PCNextF;
|
||||||
@ -170,9 +170,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
|
// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
|
||||||
// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
|
// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
|
||||||
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
|
// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
|
||||||
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
|
// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
|
||||||
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
|
// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
|
||||||
logic StallMQ, TLBFlush;
|
logic StallMQ, TLBFlush;
|
||||||
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
|
flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
|
||||||
assign TLBFlush = sfencevmaM & ~StallMQ;
|
assign TLBFlush = sfencevmaM & ~StallMQ;
|
||||||
@ -196,7 +196,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
.AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
|
.AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
|
||||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
|
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
|
||||||
|
|
||||||
assign ITLBMissOrUpdateAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateAF);
|
assign ITLBMissOrUpdateAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateAF);
|
||||||
end else begin
|
end else begin
|
||||||
assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateAF} = '0;
|
assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateAF} = '0;
|
||||||
assign PCPF = PCFExt[P.PA_BITS-1:0];
|
assign PCPF = PCFExt[P.PA_BITS-1:0];
|
||||||
@ -206,9 +206,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// Memory
|
// Memory
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// CommittedM tells the CPU's privileged unit the current instruction
|
// CommittedM tells the CPU's privileged unit the current instruction
|
||||||
// in the memory stage is a memory operaton and that memory operation is either completed
|
// in the memory stage is a memory operaton and that memory operation is either completed
|
||||||
// or is partially executed. Partially completed memory operations need to prevent an interrupts.
|
// or is partially executed. Partially completed memory operations need to prevent an interrupts.
|
||||||
@ -229,13 +229,13 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
if (P.BUS_SUPPORTED) begin : bus
|
if (P.BUS_SUPPORTED) begin : bus
|
||||||
localparam BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1;
|
localparam BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1;
|
||||||
localparam AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1;
|
localparam AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1;
|
||||||
|
|
||||||
if(P.ICACHE_SUPPORTED) begin : icache
|
if(P.ICACHE_SUPPORTED) begin : icache
|
||||||
localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
localparam LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||||
logic [P.PA_BITS-1:0] ICacheBusAdr;
|
logic [P.PA_BITS-1:0] ICacheBusAdr;
|
||||||
logic ICacheBusAck;
|
logic ICacheBusAck;
|
||||||
logic [1:0] CacheBusRW, BusRW, CacheRWF;
|
logic [1:0] CacheBusRW, BusRW, CacheRWF;
|
||||||
|
|
||||||
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
|
assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
|
||||||
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
|
assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
|
||||||
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
|
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
|
||||||
@ -243,7 +243,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
|
.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
|
||||||
icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
|
icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
|
||||||
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
.FetchBuffer, .CacheBusAck(ICacheBusAck),
|
||||||
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
|
||||||
.CacheBusRW,
|
.CacheBusRW,
|
||||||
.ReadDataWord(ICacheInstrF),
|
.ReadDataWord(ICacheInstrF),
|
||||||
.SelHPTW('0),
|
.SelHPTW('0),
|
||||||
@ -254,9 +254,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
.FlushCache('0),
|
.FlushCache('0),
|
||||||
.NextSet(PCSpillNextF[11:0]),
|
.NextSet(PCSpillNextF[11:0]),
|
||||||
.PAdr(PCPF),
|
.PAdr(PCPF),
|
||||||
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0));
|
.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0));
|
||||||
|
|
||||||
ahbcacheinterface #(P, BEATSPERLINE, AHBWLOGBWPL, LINELEN, LLENPOVERAHBW, 1)
|
ahbcacheinterface #(P, BEATSPERLINE, AHBWLOGBWPL, LINELEN, LLENPOVERAHBW, 1)
|
||||||
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
|
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
|
||||||
.HRDATA,
|
.HRDATA,
|
||||||
.Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
|
.Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
|
||||||
@ -275,7 +275,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : 0;
|
assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : 0;
|
||||||
assign IFUHSIZE = 3'b010;
|
assign IFUHSIZE = 3'b010;
|
||||||
|
|
||||||
ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
|
ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
|
||||||
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
||||||
.HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
|
.HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
|
||||||
.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
|
.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
|
||||||
@ -288,24 +288,23 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
end
|
end
|
||||||
|
|
||||||
// mux between the alignments of uncached reads.
|
// mux between the alignments of uncached reads.
|
||||||
if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16],
|
if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16],
|
||||||
FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
|
FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
|
||||||
PCSpillF[2:1], ShiftUncachedInstr);
|
PCSpillF[2:1], ShiftUncachedInstr);
|
||||||
else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
|
else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
|
||||||
end else begin : nobus // block: bus
|
end else begin : nobus // block: bus
|
||||||
assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS,
|
assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS,
|
||||||
BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;
|
BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;
|
||||||
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
|
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
|
||||||
assign InstrRawF = IROMInstrF;
|
assign InstrRawF = IROMInstrF;
|
||||||
end
|
end
|
||||||
|
|
||||||
assign IFUCacheBusStallF = ICacheStallF | BusStall;
|
assign IFUCacheBusStallF = ICacheStallF | BusStall;
|
||||||
assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
|
assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
|
||||||
assign GatedStallD = StallD & ~SelSpillNextF;
|
assign GatedStallD = StallD & ~SelSpillNextF;
|
||||||
|
|
||||||
// flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
|
// flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
|
||||||
// TODO: Test this?!?!?!
|
fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF);
|
||||||
fetchbuffer #(P) fetchbuff(.clk, .reset, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF); // Figure out what TODO with StallF
|
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// PCNextF logic
|
// PCNextF logic
|
||||||
@ -324,11 +323,11 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
|
assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
|
||||||
|
|
||||||
if (P.ZCA_SUPPORTED) begin: pcadd
|
if (P.ZCA_SUPPORTED) begin: pcadd
|
||||||
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
|
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
|
||||||
// Speeds up critical path as compared to selecting adder input based on CompressedF
|
// Speeds up critical path as compared to selecting adder input based on CompressedF
|
||||||
always_comb
|
always_comb
|
||||||
if (CompressedF) // add 2
|
if (CompressedF) // add 2
|
||||||
if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
|
if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
|
||||||
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
|
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
|
||||||
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
|
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
|
||||||
end else begin: pcadd
|
end else begin: pcadd
|
||||||
@ -341,21 +340,21 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
if (P.BPRED_SUPPORTED) begin : bpred
|
if (P.BPRED_SUPPORTED) begin : bpred
|
||||||
bpred #(P) bpred(.clk, .reset,
|
bpred #(P) bpred(.clk, .reset,
|
||||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||||
.FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
|
.FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
|
||||||
.BranchD, .BranchE, .JumpD, .JumpE,
|
.BranchD, .BranchE, .JumpD, .JumpE,
|
||||||
.InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
|
.InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
|
||||||
.PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
|
.PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
|
||||||
.BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
|
.BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
|
||||||
|
|
||||||
end else begin : bpred
|
end else begin : bpred
|
||||||
mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));
|
mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));
|
||||||
logic BranchM, JumpM, BranchW, JumpW;
|
logic BranchM, JumpM, BranchW, JumpW;
|
||||||
logic CallD, CallE, CallM, CallW;
|
logic CallD, CallE, CallM, CallW;
|
||||||
logic ReturnD, ReturnE, ReturnM, ReturnW;
|
logic ReturnD, ReturnE, ReturnM, ReturnW;
|
||||||
assign BPWrongE = PCSrcE;
|
assign BPWrongE = PCSrcE;
|
||||||
icpred #(P, 0) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM,
|
icpred #(P, 0) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM,
|
||||||
.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
|
.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
|
||||||
.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW,
|
.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW,
|
||||||
.BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0),
|
.BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0),
|
||||||
.BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM,
|
.BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM,
|
||||||
.BPReturnWrongD());
|
.BPReturnWrongD());
|
||||||
@ -365,19 +364,19 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign BTAWrongM = BPWrongM;
|
assign BTAWrongM = BPWrongM;
|
||||||
assign IClassM = {CallM, ReturnM, JumpM, BranchM};
|
assign IClassM = {CallM, ReturnM, JumpM, BranchM};
|
||||||
assign NextValidPCE = PCE;
|
assign NextValidPCE = PCE;
|
||||||
end
|
end
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
// Decode stage pipeline register and compressed instruction decoding.
|
// Decode stage pipeline register and compressed instruction decoding.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// Decode stage pipeline register and logic
|
// Decode stage pipeline register and logic
|
||||||
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
||||||
|
|
||||||
// expand 16-bit compressed instructions to 32 bits
|
// expand 16-bit compressed instructions to 32 bits
|
||||||
if (P.ZCA_SUPPORTED) begin: decomp
|
if (P.ZCA_SUPPORTED) begin: decomp
|
||||||
logic IllegalCompInstrD;
|
logic IllegalCompInstrD;
|
||||||
decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||||
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||||
end else begin: decomp
|
end else begin: decomp
|
||||||
assign InstrD = InstrRawD;
|
assign InstrD = InstrRawD;
|
||||||
@ -390,7 +389,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
// instruction address misalignment is generated by the target of control flow instructions, not
|
// instruction address misalignment is generated by the target of control flow instructions, not
|
||||||
// the fetch itself.
|
// the fetch itself.
|
||||||
// xret and Traps both cannot produce instruction misaligned.
|
// xret and Traps both cannot produce instruction misaligned.
|
||||||
// xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21.
|
// xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21.
|
||||||
// The low bit of mepc (mepc[0]) is always zero. On implementations that support
|
// The low bit of mepc (mepc[0]) is always zero. On implementations that support
|
||||||
// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
|
// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
|
||||||
// Spec 3.1.14
|
// Spec 3.1.14
|
||||||
@ -409,10 +408,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
|
flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
|
||||||
end else assign InstrM = '0;
|
end else assign InstrM = '0;
|
||||||
// PCM is only needed with CSRs or branch prediction
|
// PCM is only needed with CSRs or branch prediction
|
||||||
if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
|
if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
|
||||||
flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
|
flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
|
||||||
else assign PCM = '0;
|
else assign PCM = '0;
|
||||||
|
|
||||||
// If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4
|
// If compressed instructions are supported, increment PCLink by 2 or 4 for a jal. Otherwise, just by 4
|
||||||
if (P.ZCA_SUPPORTED) begin
|
if (P.ZCA_SUPPORTED) begin
|
||||||
logic CompressedD; // instruction is compressed
|
logic CompressedD; // instruction is compressed
|
||||||
@ -423,14 +422,14 @@ module ifu import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign CompressedE = 1'b0;
|
assign CompressedE = 1'b0;
|
||||||
assign PCLinkE = PCE + 'd4;
|
assign PCLinkE = PCE + 'd4;
|
||||||
end
|
end
|
||||||
|
|
||||||
// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
|
// pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
|
||||||
if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
|
if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
|
||||||
logic CompressedM; // instruction is compressed
|
logic CompressedM; // instruction is compressed
|
||||||
flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
|
flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
|
||||||
flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
||||||
flopenrc #(1) CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
|
flopenrc #(1) CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
|
||||||
mux2 #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM);
|
mux2 #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM);
|
||||||
end else
|
end else
|
||||||
assign InstrOrigM = InstrM;
|
assign InstrOrigM = InstrM;
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user