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Manual merge for fctrl.sv, fpu.S, and ifu.S files

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This commit is contained in:
Sydeny 2023-04-03 01:55:23 -07:00
parent 17d41b4d52
commit 981e5bd5f6
3 changed files with 107 additions and 107 deletions
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6
src/fpu/fctrl.sv
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@ -146,10 +146,13 @@ module fctrl (
ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q) ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
// coverage off
// Not covered in testing because rv64gc does not support half or quad precision
7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10) 7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q) ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11) 7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d) ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
// coverage on
7'b1101000: case(Rs2D) 7'b1101000: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
@ -174,6 +177,8 @@ module fctrl (
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
endcase endcase
// coverage off
// Not covered in testing because rv64gc does not support half or quad precision
7'b1101010: case(Rs2D) 7'b1101010: case(Rs2D)
5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h 5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h
5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h 5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
@ -198,6 +203,7 @@ module fctrl (
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
endcase endcase
// coverage on
endcase endcase
endcase endcase
end end

3
tests/coverage/fpu.S
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@ -57,7 +57,6 @@ main:
fcvt.l.q a0, ft3 fcvt.l.q a0, ft3
fcvt.lu.q a0, ft3 fcvt.lu.q a0, ft3
<<<<<<< HEAD
// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
@ -75,8 +74,6 @@ main:
.word 0xd2400053 // Line 168 All False Test case - illegal instruction? .word 0xd2400053 // Line 168 All False Test case - illegal instruction?
.word 0xc2400053 // Line 174 All False Test case - illegal instruction? .word 0xc2400053 // Line 174 All False Test case - illegal instruction?
=======
>>>>>>> d4b7da34dee55ec8394ab391ecd6514c887a9790
# Test illegal instructions are detected # Test illegal instructions are detected
.word 0x00000007 // illegal floating-point load (bad Funct3) .word 0x00000007 // illegal floating-point load (bad Funct3)
.word 0x00000027 // illegal floating-point store (bad Funct3) .word 0x00000027 // illegal floating-point store (bad Funct3)

7
tests/coverage/ifu.S
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@ -36,6 +36,7 @@ main:
// binary version 0000 0000 0000 0000 0010 0000 0000 0000 // binary version 0000 0000 0000 0000 0010 0000 0000 0000
mv s0, sp mv s0, sp
c.fld fs0, 0(s0) c.fld fs0, 0(s0)
c.fsd fs0, 0(s0) c.fsd fs0, 0(s0)
// c.fldsp fs0, 0 // c.fldsp fs0, 0
@ -44,14 +45,10 @@ main:
// c.fsdsp fs0, 0 // c.fsdsp fs0, 0
.hword 0xA002 .hword 0xA002
# set XLEN to 64
li t0, 0x200000000
csrs mstatus, t0
//# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
//.hword 0x9C01 //.hword 0x9C01
# Illegal compressed instruction # Line Illegal compressed instruction
.hword 0x9C41 .hword 0x9C41
j done j done