From 97cbdae6744cc5b4a858be22a04b59083d9c8bb3 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 17 May 2021 16:48:51 -0500 Subject: [PATCH] Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version --- wally-pipelined/regression/bad_vec.txt | 948 ++++++++++++++++++ wally-pipelined/regression/div | Bin 0 -> 16696 bytes wally-pipelined/regression/div.c | 23 + wally-pipelined/regression/div.c~ | 21 + .../regression/sim-wally-batch-muldiv | 2 +- wally-pipelined/regression/sim-wally-muldiv | 1 + wally-pipelined/regression/udiv.c | 22 + .../regression/vish_stacktrace.vstf | 21 + .../wally-pipelined-batch-muldiv.do | 6 +- .../regression/wally-pipelined-muldiv.do | 9 +- .../regression/wave-dos/ahb-muldiv.do | 26 +- .../regression/wave-dos/ahb-waves.do | 2 +- wally-pipelined/src/muldiv/div.sv | 16 +- wally-pipelined/src/muldiv/div/div | Bin 16696 -> 16696 bytes wally-pipelined/src/muldiv/div/div.c | 27 +- wally-pipelined/src/muldiv/div/div64.out | 174 ++-- wally-pipelined/src/muldiv/div/divide4x64.sv | 18 +- .../src/muldiv/div/imperas-riscv-tests | 1 + wally-pipelined/src/muldiv/div/int64div.do | 8 +- wally-pipelined/src/muldiv/div/shift.sv | 151 +++ wally-pipelined/src/muldiv/div/shift_left.do | 55 + wally-pipelined/src/muldiv/div/shift_left.out | 79 ++ .../src/muldiv/div/shift_left_tb.sv | 71 ++ wally-pipelined/src/muldiv/div/shift_right.do | 55 + .../src/muldiv/div/shift_right.out | 24 + .../src/muldiv/div/shift_right_tb.sv | 64 ++ wally-pipelined/src/muldiv/div/shifter.sv | 18 + .../src/muldiv/div/test_int64div.sv | 4 +- wally-pipelined/src/muldiv/div/udiv | Bin 0 -> 16696 bytes wally-pipelined/src/muldiv/div/udiv.c | 24 + wally-pipelined/src/muldiv/muldiv.sv | 62 +- 31 files changed, 1780 insertions(+), 152 deletions(-) create mode 100644 wally-pipelined/regression/bad_vec.txt create mode 100755 wally-pipelined/regression/div create mode 100644 wally-pipelined/regression/div.c create mode 100644 wally-pipelined/regression/div.c~ create mode 100755 wally-pipelined/regression/sim-wally-muldiv create mode 100644 wally-pipelined/regression/udiv.c create mode 160000 wally-pipelined/src/muldiv/div/imperas-riscv-tests create mode 100644 wally-pipelined/src/muldiv/div/shift.sv create mode 100755 wally-pipelined/src/muldiv/div/shift_left.do create mode 100644 wally-pipelined/src/muldiv/div/shift_left.out create mode 100644 wally-pipelined/src/muldiv/div/shift_left_tb.sv create mode 100755 wally-pipelined/src/muldiv/div/shift_right.do create mode 100644 wally-pipelined/src/muldiv/div/shift_right.out create mode 100755 wally-pipelined/src/muldiv/div/shift_right_tb.sv create mode 100644 wally-pipelined/src/muldiv/div/shifter.sv create mode 100755 wally-pipelined/src/muldiv/div/udiv create mode 100644 wally-pipelined/src/muldiv/div/udiv.c diff --git a/wally-pipelined/regression/bad_vec.txt b/wally-pipelined/regression/bad_vec.txt new file mode 100644 index 000000000..7805dce68 --- /dev/null +++ b/wally-pipelined/regression/bad_vec.txt @@ -0,0 +1,948 @@ +do wally-pipelined-batch-muldiv.do ../config/rv64imc rv64imc +# Model Technology ModelSim SE-64 vlog 10.7e Compiler 2019.06 May 30 2019 +# Start time: 08:48:17 on May 17,2021 +# vlog -work work_rv64imc "+incdir+../config/rv64imc" ../testbench/testbench-imperas-div.sv ../src/cache/cache-sram.sv ../src/cache/dmapped.sv ../src/cache/sram1rw.sv ../src/dmem/dcache.sv ../src/dmem/dmem.sv ../src/ebu/ahblite.sv ../src/ebu/amoalu.sv ../src/ebu/subwordread.sv ../src/fpu/add.sv ../src/fpu/adder.sv ../src/fpu/align.sv ../src/fpu/bk128.sv ../src/fpu/bk13.sv ../src/fpu/bk14.sv ../src/fpu/bk15.sv ../src/fpu/black_gray_cells.sv ../src/fpu/booth.sv ../src/fpu/cla12.sv ../src/fpu/cla52.sv ../src/fpu/cla64.sv ../src/fpu/compressors.sv ../src/fpu/convert_inputs.sv ../src/fpu/convert_inputs_div.sv ../src/fpu/csa.sv ../src/fpu/divconv.sv ../src/fpu/exception.sv ../src/fpu/exception_div.sv ../src/fpu/expgen1.sv ../src/fpu/expgen2.sv ../src/fpu/fctrl.sv ../src/fpu/flag1.sv ../src/fpu/flag2.sv ../src/fpu/fma1.sv ../src/fpu/fma2.sv ../src/fpu/fpadd_denorm.sv ../src/fpu/fpdiv.sv ../src/fpu/fpu.sv ../src/fpu/fpuaddcvt1.sv ../src/fpu/fpuaddcvt2.sv ../src/fpu/fpucmp1.sv ../src/fpu/fpucmp2.sv ../src/fpu/freg.sv ../src/fpu/fsgn.sv ../src/fpu/fsm.sv ../src/fpu/ldf128.sv ../src/fpu/ldf64.sv ../src/fpu/ling_bk13.sv ../src/fpu/lza.sv ../src/fpu/lzd_denorm.sv ../src/fpu/mult_R4_64_64_cs.sv ../src/fpu/multiply.sv ../src/fpu/normalize.sv ../src/fpu/round.sv ../src/fpu/rounder_denorm.sv ../src/fpu/rounder_div.sv ../src/fpu/sbtm.sv ../src/fpu/sbtm2.sv ../src/fpu/sbtm_a0.sv ../src/fpu/sbtm_a1.sv ../src/fpu/sbtm_a2.sv ../src/fpu/sbtm_a3.sv ../src/fpu/sbtm_a4.sv ../src/fpu/shifter_denorm.sv ../src/fpu/sign.sv ../src/fpu/sk14.sv ../src/fpu/special.sv ../src/generic/flop.sv ../src/generic/mux.sv ../src/hazard/hazard.sv ../src/ieu/alu.sv ../src/ieu/controller.sv ../src/ieu/datapath.sv ../src/ieu/extend.sv ../src/ieu/forward.sv ../src/ieu/ieu.sv ../src/ieu/regfile.sv ../src/ieu/shifter.sv ../src/ifu/BTBPredictor.sv ../src/ifu/RAsPredictor.sv ../src/ifu/SramModel.sv ../src/ifu/bpred.sv ../src/ifu/decompress.sv ../src/ifu/globalHistoryPredictor.sv ../src/ifu/gshare.sv ../src/ifu/icache.sv ../src/ifu/icacheMem.sv ../src/ifu/ifu.sv ../src/ifu/localHistoryPredictor.sv ../src/ifu/satCounter2.sv ../src/ifu/twoBitPredictor.sv ../src/mmu/cam_line.sv ../src/mmu/decoder.sv ../src/mmu/page_number_mixer.sv ../src/mmu/pagetablewalker.sv ../src/mmu/priority_encoder.sv ../src/mmu/tlb.sv ../src/mmu/tlb_cam.sv ../src/mmu/tlb_lru.sv ../src/mmu/tlb_ram.sv ../src/muldiv/div.sv ../src/muldiv/mul.sv ../src/muldiv/muldiv.sv ../src/privileged/csr.sv ../src/privileged/csrc.sv ../src/privileged/csri.sv ../src/privileged/csrm.sv ../src/privileged/csrn.sv ../src/privileged/csrs.sv ../src/privileged/csrsr.sv ../src/privileged/csru.sv ../src/privileged/pmachecker.sv ../src/privileged/pmpadrdec.sv ../src/privileged/pmpchecker.sv ../src/privileged/privdec.sv ../src/privileged/privileged.sv ../src/privileged/trap.sv ../src/uncore/adrdec.sv ../src/uncore/clint.sv ../src/uncore/dtim.sv ../src/uncore/gpio.sv ../src/uncore/imem.sv ../src/uncore/plic.sv ../src/uncore/subwordwrite.sv ../src/uncore/uart.sv ../src/uncore/uartPC16550D.sv ../src/uncore/uncore.sv ../src/wally/wallypipelinedhart.sv ../src/wally/wallypipelinedsoc.sv -suppress 2583 +# -- Compiling module testbench +# ** Warning: ../testbench/testbench-imperas-div.sv(63): (vlog-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(221): (vlog-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(368): (vlog-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(392): (vlog-2737) '{ }' may only be used with a queue. +# -- Compiling module instrTrackerTB +# -- Compiling module instrNameDecTB +# -- Compiling module Sram1Read1Write +# -- Compiling module rodirectmappedmem +# -- Compiling module wtdirectmappedmem +# -- Compiling module sram1rw +# -- Compiling module dcache +# -- Compiling module dcachecontroller +# -- Compiling module dmem +# -- Compiling package ahbliteState +# -- Compiling module ahblite +# -- Importing package ahbliteState +# -- Compiling module amoalu +# -- Compiling module subwordread +# -- Compiling module add +# -- Compiling module INVBLOCK +# -- Compiling module XXOR1 +# -- Compiling module BLOCK0 +# -- Compiling module BLOCK1 +# -- Compiling module BLOCK2 +# -- Compiling module BLOCK1A +# -- Compiling module BLOCK2A +# -- Compiling module PRESTAGE_64 +# -- Compiling module DBLC_0_64 +# -- Compiling module DBLC_1_64 +# -- Compiling module DBLC_2_64 +# -- Compiling module DBLC_3_64 +# -- Compiling module DBLC_4_64 +# -- Compiling module DBLC_5_64 +# -- Compiling module XORSTAGE_64 +# -- Compiling module DBLCTREE_64 +# -- Compiling module DBLCADDER_64_64 +# -- Compiling module align +# -- Compiling module bk128 +# -- Compiling module brent_kung_cs128 +# -- Compiling module bk13 +# -- Compiling module brent_kung_cs13 +# -- Compiling module bk14 +# -- Compiling module brent_kung14 +# -- Compiling module bk15 +# -- Compiling module kogge_stone +# -- Compiling module black +# -- Compiling module grey +# -- Compiling module rblk +# -- Compiling module rgry +# -- Compiling module booth +# -- Compiling module cla12 +# -- Compiling module cla_sub12 +# -- Compiling module cla52 +# -- Compiling module cla_sub52 +# -- Compiling module cla64 +# -- Compiling module cla_sub64 +# -- Compiling module convert_inputs +# -- Compiling module convert_inputs_div +# -- Compiling module ha +# -- Compiling module FA_array +# -- Compiling module HA_array +# -- Compiling module divconv +# -- Compiling module exception +# -- Compiling module exception_div +# -- Compiling module expgen1 +# -- Compiling module expgen2 +# -- Compiling module fctrl +# -- Compiling module flag1 +# -- Compiling module flag2 +# -- Compiling module fma1 +# -- Compiling module fma2 +# -- Compiling module fpadd +# -- Compiling module fpdiv +# -- Compiling module exp_add +# -- Compiling module brent_kung +# -- Compiling module fpu +# -- Compiling module fpuaddcvt1 +# -- Compiling module fpuaddcvt2 +# -- Compiling module fpucmp1 +# -- Compiling module magcompare2c +# -- Compiling module magcompare64b_1 +# -- Compiling module exception_cmp_1 +# -- Compiling module fpucmp2 +# -- Compiling module magcompare64b_2 +# -- Compiling module exception_cmp_2 +# -- Compiling module freg1adr +# -- Compiling module freg2adr +# -- Compiling module freg3adr +# -- Compiling module fpusgn +# -- Compiling module fsm +# -- Compiling module ldf128 +# -- Compiling module ladner_fischer128 +# -- Compiling module ldf64 +# -- Compiling module ladner_fischer64 +# -- Compiling module ling_bk13 +# -- Compiling module ling_brent_kung +# -- Compiling module lza +# -- Compiling module lz52 +# -- Compiling module mult64 +# -- Compiling module multiplier +# -- Compiling module aaoi +# -- Compiling module halfAdd +# -- Compiling module r4bs +# -- Compiling module r4be +# -- Compiling module fullAdd_xc +# -- Compiling module maj +# -- Compiling module fourtwo_x +# -- Compiling module inverter +# -- Compiling module buffer +# -- Compiling module subxor +# -- Compiling module xnor2 +# -- Compiling module xor2 +# -- Compiling module xor3 +# -- Compiling module xor3c +# -- Compiling module fullAdd_x +# -- Compiling module nand2 +# -- Compiling module nand3 +# -- Compiling module and3 +# -- Compiling module and2 +# -- Compiling module nor2 +# -- Compiling module or2 +# -- Compiling module nor3 +# -- Compiling module nand5 +# -- Compiling module and5 +# -- Compiling module nand4 +# -- Compiling module and4 +# -- Compiling module oai +# -- Compiling module aoi +# -- Compiling module min +# -- Compiling module sum_b +# -- Compiling module fullAdd_i +# -- Compiling module fullAdd +# -- Compiling module blackCell +# -- Compiling module grayCell +# -- Compiling module multiply +# -- Compiling module normalize +# -- Compiling module round +# -- Compiling module rounder +# -- Compiling module rounder_div +# -- Compiling module sbtm +# -- Compiling module sbtm2 +# -- Compiling module sbtm_a0 +# -- Compiling module sbtm_a1 +# -- Compiling module sbtm_a2 +# -- Compiling module sbtm_a3 +# -- Compiling module sbtm_a4 +# -- Compiling module mux21x57 +# -- Compiling module mux21x64 +# -- Compiling module barrel_shifter_l64 +# -- Compiling module barrel_shifter_r57 +# -- Compiling module barrel_shifter_r64 +# -- Compiling module sign +# -- Compiling module sk14 +# -- Compiling module sklansky +# -- Compiling module special +# -- Compiling module flop +# -- Compiling module flopr +# -- Compiling module flopen +# -- Compiling module flopenrc +# -- Compiling module flopenr +# -- Compiling module flopenl +# -- Compiling module floprc +# -- Compiling module mux2 +# -- Compiling module mux3 +# -- Compiling module mux4 +# -- Compiling module mux5 +# -- Compiling module mux6 +# -- Compiling module hazard +# -- Compiling module alu +# -- Compiling module controller +# -- Compiling module datapath +# -- Compiling module extend +# -- Compiling module forward +# -- Compiling module ieu +# -- Compiling module regfile +# -- Compiling module shifter +# -- Compiling module BTBPredictor +# -- Compiling module RASPredictor +# -- Compiling module SRAM2P1R1W +# -- Compiling module bpred +# -- Compiling module decompress +# -- Compiling module globalHistoryPredictor +# -- Compiling module gsharePredictor +# -- Compiling module icache +# -- Compiling module icachecontroller +# -- Compiling module rodirectmappedmemre +# -- Compiling module ifu +# -- Compiling module localHistoryPredictor +# -- Compiling module satCounter2 +# -- Compiling module twoBitPredictor +# -- Compiling module cam_line +# -- Compiling module decoder +# -- Compiling module page_number_mixer +# -- Compiling module pagetablewalker +# -- Compiling module priority_encoder +# -- Compiling module tlb +# -- Compiling module tlb_cam +# -- Compiling module tlb_lru +# -- Compiling module tlb_ram +# -- Compiling module div +# -- Compiling module divide4x64 +# -- Compiling module ls_control +# -- Compiling module otf +# -- Compiling module adder +# -- Compiling module fa +# -- Compiling module csa +# -- Compiling module eqcmp +# -- Compiling module qst4 +# -- Compiling module lz2 +# -- Compiling module lz4 +# -- Compiling module lz8 +# -- Compiling module lz16 +# -- Compiling module lz32 +# -- Compiling module lz64 +# -- Compiling module fsm64 +# -- Compiling module magcompare2b +# -- Compiling module magcompare8 +# -- Compiling module shifter_l64 +# -- Compiling module shifter_r64 +# -- Compiling module shifter_l32 +# -- Compiling module shifter_r32 +# -- Compiling module mul +# -- Compiling module muldiv +# -- Compiling module csr +# -- Compiling module csrc +# -- Compiling module csri +# -- Compiling module csrm +# -- Compiling module csrn +# -- Compiling module csrs +# -- Compiling module csrsr +# -- Compiling module csru +# -- Compiling module pmachecker +# -- Compiling module attributes +# -- Compiling module pmpadrdec +# -- Compiling module pmpchecker +# -- Compiling module privdec +# -- Compiling module privileged +# -- Compiling module trap +# -- Compiling module adrdec +# -- Compiling module clint +# -- Compiling module dtim +# -- Compiling module gpio +# -- Compiling module imem +# -- Compiling module plic +# -- Compiling module subwordwrite +# -- Compiling module uart +# -- Compiling module uartPC16550D +# -- Compiling module uncore +# -- Compiling module wallypipelinedhart +# -- Compiling module wallypipelinedsoc +# +# Top level modules: +# testbench +# rodirectmappedmem +# dcache +# bk128 +# bk13 +# bk14 +# booth +# cla_sub52 +# FA_array +# HA_array +# fpadd +# freg1adr +# freg2adr +# ling_bk13 +# mult64 +# fourtwo_x +# nand2 +# nand3 +# and3 +# nor2 +# or2 +# nor3 +# nand5 +# and5 +# nand4 +# and4 +# oai +# fullAdd +# blackCell +# sbtm_a4 +# barrel_shifter_r64 +# sk14 +# flopen +# eqcmp +# shifter_l32 +# shifter_r32 +# imem +# End time: 08:48:17 on May 17,2021, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 4, Suppressed Warnings: 256 +# Model Technology ModelSim SE-64 vopt 10.7e Compiler 2019.06 May 30 2019 +# Start time: 08:48:17 on May 17,2021 +# vopt work_rv64imc.testbench -work work_rv64imc -o workopt_rv64imc +# +# Top level modules: +# testbench +# +# Analyzing design... +# -- Loading module testbench +# -- Loading module flopenr +# -- Loading module wallypipelinedsoc +# -- Loading module wallypipelinedhart +# -- Loading module ifu +# -- Loading module tlb +# -- Loading module tlb_lru +# -- Loading module decoder +# -- Loading module priority_encoder +# -- Loading module flopenrc +# -- Loading module tlb_ram +# -- Loading module tlb_cam +# -- Loading module page_number_mixer +# -- Loading module icache +# -- Loading module rodirectmappedmemre +# -- Loading module sram1rw +# -- Loading module icachecontroller +# -- Loading module flopr +# -- Loading module flop +# -- Loading module flopenl +# -- Loading module mux2 +# -- Loading module decompress +# -- Loading module ieu +# -- Loading module controller +# -- Loading module datapath +# -- Loading module regfile +# -- Loading module extend +# -- Loading module mux3 +# -- Loading module alu +# -- Loading module shifter +# -- Loading module mux5 +# -- Loading module forward +# -- Loading module dmem +# -- Loading module ahblite +# -- Importing package ahbliteState +# -- Loading module subwordread +# -- Loading module pagetablewalker +# -- Loading module muldiv +# -- Loading module hazard +# -- Loading module privileged +# -- Loading module privdec +# -- Loading module csr +# -- Loading module pmachecker +# -- Loading module attributes +# -- Loading module adrdec +# -- Loading module pmpchecker +# -- Loading module pmpadrdec +# -- Loading module trap +# -- Loading module fpu +# -- Loading module fctrl +# -- Loading module freg3adr +# -- Loading module fma1 +# -- Loading module multiply +# -- Loading module align +# -- Loading module expgen1 +# -- Loading module special +# -- Loading module flag1 +# -- Loading module fpdiv +# -- Loading module convert_inputs_div +# -- Loading module exception_div +# -- Loading module csa +# -- Loading module exp_add +# -- Loading module brent_kung +# -- Loading module grey +# -- Loading module black +# -- Loading module divconv +# -- Loading module sbtm +# -- Loading module sbtm_a0 +# -- Loading module sbtm_a1 +# -- Loading module bk15 +# -- Loading module kogge_stone +# -- Loading module rgry +# -- Loading module rblk +# -- Loading module sbtm2 +# -- Loading module sbtm_a2 +# -- Loading module sbtm_a3 +# -- Loading module mux6 +# -- Loading module multiplier +# -- Loading module buffer +# -- Loading module r4be +# -- Loading module inverter +# -- Loading module r4bs +# -- Loading module aaoi +# -- Loading module xnor2 +# -- Loading module halfAdd +# -- Loading module and2 +# -- Loading module xor2 +# -- Loading module subxor +# -- Loading module fullAdd_x +# -- Loading module xor3c +# -- Loading module maj +# -- Loading module min +# -- Loading module xor3 +# -- Loading module ldf128 +# -- Loading module ladner_fischer128 +# -- Loading module ldf64 +# -- Loading module ladner_fischer64 +# -- Loading module fsm +# -- Loading module rounder_div +# -- Loading module fpuaddcvt1 +# -- Loading module convert_inputs +# -- Loading module exception +# -- Loading module lz52 +# -- Loading module lz32 +# -- Loading module lz16 +# -- Loading module lz8 +# -- Loading module lz2 +# -- Loading module lz4 +# -- Loading module barrel_shifter_r57 +# -- Loading module mux21x57 +# -- Loading module cla64 +# -- Loading module DBLCADDER_64_64 +# -- Loading module PRESTAGE_64 +# -- Loading module BLOCK0 +# -- Loading module INVBLOCK +# -- Loading module DBLCTREE_64 +# -- Loading module DBLC_0_64 +# -- Loading module BLOCK1A +# -- Loading module BLOCK1 +# -- Loading module DBLC_1_64 +# -- Loading module BLOCK2A +# -- Loading module BLOCK2 +# -- Loading module DBLC_2_64 +# -- Loading module DBLC_3_64 +# -- Loading module DBLC_4_64 +# -- Loading module DBLC_5_64 +# -- Loading module XORSTAGE_64 +# -- Loading module XXOR1 +# -- Loading module cla_sub64 +# -- Loading module fpucmp1 +# -- Loading module magcompare64b_1 +# -- Loading module magcompare2b +# -- Loading module magcompare2c +# -- Loading module exception_cmp_1 +# -- Loading module fpusgn +# -- Loading module fma2 +# -- Loading module add +# -- Loading module lza +# -- Loading module normalize +# -- Loading module round +# -- Loading module expgen2 +# -- Loading module sign +# -- Loading module flag2 +# -- Loading module fpuaddcvt2 +# -- Loading module lz64 +# -- Loading module barrel_shifter_l64 +# -- Loading module mux21x64 +# -- Loading module rounder +# -- Loading module cla52 +# -- Loading module cla12 +# -- Loading module cla_sub12 +# -- Loading module fpucmp2 +# -- Loading module magcompare64b_2 +# -- Loading module exception_cmp_2 +# -- Loading module uncore +# -- Loading module subwordwrite +# -- Loading module dtim +# -- Loading module clint +# -- Loading module plic +# -- Loading module gpio +# -- Loading module uart +# -- Loading module uartPC16550D +# -- Loading module instrTrackerTB +# -- Loading module instrNameDecTB +# -- Loading module cam_line +# -- Loading module bpred +# -- Loading module BTBPredictor +# -- Loading module SRAM2P1R1W +# -- Loading module RASPredictor +# -- Loading module satCounter2 +# -- Loading module amoalu +# -- Loading module mul +# -- Loading module div +# -- Loading module shifter_l64 +# -- Loading module adder +# -- Loading module fsm64 +# -- Loading module magcompare8 +# -- Loading module divide4x64 +# -- Loading module qst4 +# -- Loading module mux4 +# -- Loading module ls_control +# -- Loading module otf +# -- Loading module shifter_r64 +# -- Loading module csri +# -- Loading module csrsr +# -- Loading module csrc +# -- Loading module csrm +# -- Loading module csrs +# -- Loading module csrn +# -- Loading module csru +# -- Loading module floprc +# -- Loading module fa +# -- Loading module gsharePredictor +# Optimizing 250 design-units (inlining 28324/28336 module instances): +# -- Inlining module buffer(fast) +# -- Inlining module r4be(fast) +# -- Inlining module inverter(fast) +# -- Inlining module aaoi(fast) +# -- Inlining module xnor2(fast) +# -- Inlining module r4bs(fast) +# -- Inlining module and2(fast) +# -- Inlining module subxor(fast) +# -- Inlining module xor2(fast) +# -- Inlining module halfAdd(fast) +# -- Inlining module xor3c(fast) +# -- Inlining module min(fast) +# -- Inlining module maj(fast) +# -- Inlining module fullAdd_x(fast) +# -- Inlining module xor3(fast) +# -- Optimizing module multiplier(fast) +# -- Inlining module flopenr(fast) +# -- Inlining module flopenr(fast__1) +# -- Inlining module decoder(fast) +# -- Inlining module priority_encoder(fast) +# -- Inlining module flopenrc(fast) +# -- Inlining module tlb_lru(fast) +# -- Inlining module tlb_ram(fast) +# -- Inlining module flopenr(fast__2) +# -- Inlining module flopenrc(fast__1) +# -- Inlining module flopenr(fast__3) +# -- Inlining module mux2(fast) +# -- Inlining module page_number_mixer(fast) +# -- Inlining module cam_line(fast) +# -- Inlining module tlb_cam(fast) +# -- Inlining module page_number_mixer(fast__1) +# -- Inlining module mux2(fast__1) +# -- Inlining module tlb(fast) +# -- Inlining module sram1rw(fast) +# -- Inlining module sram1rw(fast__1) +# -- Inlining module rodirectmappedmemre(fast) +# -- Inlining module flopr(fast) +# -- Inlining module flopenr(fast__4) +# -- Inlining module flopenr(fast__5) +# -- Inlining module flopenr(fast__6) +# -- Inlining module flop(fast) +# -- Inlining module flopenl(fast) +# -- Inlining module flopr(fast__1) +# -- Inlining module mux2(fast__2) +# -- Inlining module icachecontroller(fast) +# -- Inlining module icache(fast) +# -- Inlining module flopenl(fast__1) +# -- Inlining module flopenrc(fast__2) +# -- Inlining module decompress(fast) +# -- Inlining module flopenrc(fast__3) +# -- Inlining module flopenrc(fast__4) +# -- Inlining module flopenr(fast__7) +# -- Inlining module flopenr(fast__8) +# -- Inlining module SRAM2P1R1W(fast) +# -- Inlining module BTBPredictor(fast) +# -- Inlining module flopenr(fast__9) +# -- Inlining module RASPredictor(fast) +# -- Inlining module flopenrc(fast__5) +# -- Inlining module satCounter2(fast) +# -- Inlining module SRAM2P1R1W(fast__1) +# -- Inlining module flopr(fast__2) +# -- Inlining module gsharePredictor(fast) +# -- Inlining module bpred(fast) +# -- Inlining module ifu(fast) +# -- Inlining module flopenrc(fast__6) +# -- Inlining module flopenrc(fast__7) +# -- Inlining module controller(fast) +# -- Inlining module regfile(fast) +# -- Inlining module extend(fast) +# -- Inlining module mux3(fast) +# -- Inlining module shifter(fast) +# -- Inlining module alu(fast) +# -- Inlining module mux5(fast) +# -- Inlining module datapath(fast) +# -- Inlining module forward(fast) +# -- Inlining module ieu(fast) +# -- Inlining module tlb(fast__1) +# -- Inlining module flopenrc(fast__8) +# -- Inlining module dmem(fast) +# -- Inlining module flopenl(fast__2) +# -- Inlining module flop(fast__1) +# -- Inlining module flop(fast__2) +# -- Inlining module flop(fast__3) +# -- Inlining module flopr(fast__3) +# -- Inlining module subwordread(fast) +# -- Inlining module amoalu(fast) +# -- Inlining module ahblite(fast) +# -- Inlining module flopenl(fast__3) +# -- Inlining module pagetablewalker(fast) +# -- Inlining module mul(fast) +# -- Inlining module lz2(fast) +# -- Inlining module lz4(fast) +# -- Inlining module lz8(fast) +# -- Inlining module lz16(fast) +# -- Inlining module lz32(fast) +# -- Inlining module lz64(fast) +# -- Inlining module shifter_l64(fast) +# -- Inlining module adder(fast) +# -- Inlining module magcompare2b(fast) +# -- Inlining module magcompare8(fast) +# -- Inlining module fsm64(fast) +# -- Inlining module mux2(fast__3) +# -- Inlining module qst4(fast) +# -- Inlining module mux4(fast) +# -- Inlining module fa(fast) +# -- Inlining module csa(fast) +# -- Inlining module flopenr(fast__10) +# -- Inlining module ls_control(fast) +# -- Inlining module mux2(fast__4) +# -- Inlining module flopenr(fast__11) +# -- Inlining module otf(fast) +# -- Inlining module adder(fast__1) +# -- Inlining module divide4x64(fast) +# -- Inlining module shifter_r64(fast) +# -- Inlining module div(fast) +# -- Inlining module flopenrc(fast__9) +# -- Inlining module muldiv(fast) +# -- Inlining module hazard(fast) +# -- Inlining module flopenl(fast__4) +# -- Inlining module privdec(fast) +# -- Inlining module adrdec(fast) +# -- Inlining module attributes(fast) +# -- Inlining module pmachecker(fast) +# -- Inlining module trap(fast) +# -- Inlining module privileged(fast) +# -- Inlining module fctrl(fast) +# -- Inlining module floprc(fast) +# -- Inlining module freg3adr(fast) +# -- Inlining module multiply(fast) +# -- Inlining module align(fast) +# -- Inlining module expgen1(fast) +# -- Inlining module special(fast) +# -- Inlining module flag1(fast) +# -- Inlining module fma1(fast) +# -- Inlining module convert_inputs_div(fast) +# -- Inlining module exception_div(fast) +# -- Inlining module csa(fast__1) +# -- Inlining module grey(fast) +# -- Inlining module black(fast) +# -- Inlining module brent_kung(fast) +# -- Inlining module exp_add(fast) +# -- Inlining module sbtm_a0(fast) +# -- Inlining module sbtm_a1(fast) +# -- Inlining module rgry(fast) +# -- Inlining module rblk(fast) +# -- Inlining module kogge_stone(fast) +# -- Inlining module bk15(fast) +# -- Inlining module sbtm(fast) +# -- Inlining module sbtm_a2(fast) +# -- Inlining module sbtm_a3(fast) +# -- Inlining module sbtm2(fast) +# -- Inlining module mux6(fast) +# -- Inlining module mux2(fast__5) +# -- Inlining module csa(fast__2) +# -- Inlining module mux2(fast__6) +# -- Inlining module ladner_fischer128(fast) +# -- Inlining module ldf128(fast) +# -- Inlining module ladner_fischer64(fast) +# -- Inlining module ldf64(fast) +# -- Inlining module flopenr(fast__12) +# -- Inlining module divconv(fast) +# -- Inlining module fsm(fast) +# -- Inlining module rounder_div(fast) +# -- Inlining module flopenr(fast__13) +# -- Inlining module fpdiv(fast) +# -- Inlining module convert_inputs(fast) +# -- Inlining module exception(fast) +# -- Inlining module lz52(fast) +# -- Inlining module mux21x57(fast) +# -- Inlining module barrel_shifter_r57(fast) +# -- Inlining module BLOCK0(fast) +# -- Inlining module INVBLOCK(fast) +# -- Inlining module PRESTAGE_64(fast) +# -- Inlining module BLOCK1A(fast) +# -- Inlining module BLOCK1(fast) +# -- Inlining module DBLC_0_64(fast) +# -- Inlining module BLOCK2A(fast) +# -- Inlining module BLOCK2(fast) +# -- Inlining module DBLC_1_64(fast) +# -- Inlining module DBLC_2_64(fast) +# -- Inlining module DBLC_3_64(fast) +# -- Inlining module DBLC_4_64(fast) +# -- Inlining module DBLC_5_64(fast) +# -- Inlining module DBLCTREE_64(fast) +# -- Inlining module XXOR1(fast) +# -- Inlining module XORSTAGE_64(fast) +# -- Inlining module DBLCADDER_64_64(fast) +# -- Inlining module cla64(fast) +# -- Inlining module cla_sub64(fast) +# -- Inlining module fpuaddcvt1(fast) +# -- Inlining module magcompare2c(fast) +# -- Inlining module magcompare64b_1(fast) +# -- Inlining module exception_cmp_1(fast) +# -- Inlining module fpucmp1(fast) +# -- Inlining module fpusgn(fast) +# -- Inlining module flopenrc(fast__10) +# -- Inlining module flopenrc(fast__11) +# -- Inlining module flopenrc(fast__12) +# -- Inlining module flopenrc(fast__13) +# -- Inlining module flopenrc(fast__14) +# -- Inlining module flopenrc(fast__15) +# -- Inlining module add(fast) +# -- Inlining module lza(fast) +# -- Inlining module normalize(fast) +# -- Inlining module round(fast) +# -- Inlining module expgen2(fast) +# -- Inlining module sign(fast) +# -- Inlining module flag2(fast) +# -- Inlining module fma2(fast) +# -- Inlining module mux21x64(fast) +# -- Inlining module barrel_shifter_l64(fast) +# -- Inlining module cla52(fast) +# -- Inlining module cla12(fast) +# -- Inlining module cla_sub12(fast) +# -- Inlining module rounder(fast) +# -- Inlining module fpuaddcvt2(fast) +# -- Inlining module magcompare64b_2(fast) +# -- Inlining module exception_cmp_2(fast) +# -- Inlining module fpucmp2(fast) +# -- Inlining module fpu(fast) +# -- Inlining module wallypipelinedhart(fast) +# -- Inlining module subwordwrite(fast) +# -- Inlining module dtim(fast) +# -- Inlining module dtim(fast__1) +# -- Inlining module clint(fast) +# -- Inlining module flopr(fast__4) +# -- Inlining module flopr(fast__5) +# -- Inlining module plic(fast) +# -- Inlining module flopr(fast__6) +# -- Inlining module flop(fast__4) +# -- Inlining module gpio(fast) +# -- Inlining module flopr(fast__7) +# -- Inlining module uartPC16550D(fast) +# -- Inlining module uart(fast) +# -- Inlining module uncore(fast) +# -- Inlining module wallypipelinedsoc(fast) +# -- Optimizing module testbench(fast) +# ** Warning: ../testbench/testbench-imperas-div.sv(63): (vopt-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(221): (vopt-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(368): (vopt-2737) '{ }' may only be used with a queue. +# ** Warning: ../testbench/testbench-imperas-div.sv(392): (vopt-2737) '{ }' may only be used with a queue. +# -- Inlining module mux2(fast__1) +# -- Inlining module csri(fast) +# -- Inlining module csrsr(fast) +# -- Inlining module flopenr(fast) +# -- Inlining module csrc(fast) +# -- Inlining module flopenl(fast__1) +# -- Inlining module flopenl(fast) +# -- Inlining module csrs(fast) +# -- Inlining module flopenr(fast__4) +# -- Inlining module flopr(fast) +# -- Inlining module csru(fast) +# -- Inlining module flopenrc(fast__2) +# -- Optimizing module csr(fast) +# -- Inlining module adrdec(fast) +# -- Inlining module pmpadrdec(fast) +# -- Optimizing module pmpchecker(fast) +# -- Inlining module flopenl(fast__1) +# -- Inlining module flopenr(fast) +# -- Inlining module flopenl(fast) +# -- Optimizing module csrm(fast) +# -- Optimizing module instrNameDecTB(fast) +# -- Optimizing module csrn(fast) +# -- Optimizing module instrTrackerTB(fast) +# -- Optimizing package ahbliteState(fast) +# Optimized design name is workopt_rv64imc +# End time: 08:48:19 on May 17,2021, Elapsed time: 0:00:02 +# Errors: 0, Warnings: 4 +# vsim -lib work_rv64imc workopt_rv64imc +# Start time: 08:48:19 on May 17,2021 +# // ModelSim SE-64 10.7e May 30 2019 Linux 5.4.0-73-generic +# // +# // Copyright 1991-2019 Mentor Graphics Corporation +# // All Rights Reserved. +# // +# // ModelSim SE-64 and its associated documentation contain trade +# // secrets and commercial or financial information that are the property of +# // Mentor Graphics Corporation and are privileged, confidential, +# // and exempt from disclosure under the Freedom of Information Act, +# // 5 U.S.C. Section 552. Furthermore, this information +# // is prohibited from disclosure under the Trade Secrets Act, +# // 18 U.S.C. Section 1905. +# // +# Loading sv_std.std +# Loading work.ahbliteState(fast) +# Loading work.testbench(fast) +# Loading work.csr(fast) +# Loading work.csrm(fast) +# Loading work.csrn(fast) +# Loading work.pmpchecker(fast) +# Loading work.multiplier(fast) +# Loading work.instrTrackerTB(fast) +# Loading work.instrNameDecTB(fast) +# Read memfile ../../imperas-riscv-tests/work/rv64i/WALLY-PIPELINE-100K.elf.memfile +# Code ended with ecall with gp = 1 +# rv64i/WALLY-PIPELINE-100K succeeded. Brilliant!!! +# Read memfile ../../imperas-riscv-tests/work/rv64i/I-ADD-01.elf.memfile +# Code ended with ecall with gp = 1 +# rv64i/I-ADD-01 succeeded. Brilliant!!! +# Read memfile ../../imperas-riscv-tests/work/rv64ic/I-C-ADD-01.elf.memfile +# Code ended with ecall with gp = 1 +# rv64ic/I-C-ADD-01 succeeded. Brilliant!!! +# Read memfile ../../imperas-riscv-tests/work/rv64m/I-MUL-01.elf.memfile +# Code ended with ecall with gp = 1 +# rv64m/I-MUL-01 succeeded. Brilliant!!! +# Read memfile ../../imperas-riscv-tests/work/rv64m/I-DIVU-01.elf.memfile +# Code ended with ecall with gp = 1 +# Error on test rv64m/I-DIVU-01 result 75: adr = 0000000080003258 sim = 9ffffffffffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 140: adr = 0000000080003460 sim = 0000000000000001, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 141: adr = 0000000080003468 sim = 0000000000000001, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 142: adr = 0000000080003470 sim = 0000000000000006, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 143: adr = 0000000080003478 sim = 0000000000000006, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 144: adr = 0000000080003480 sim = 0000000000000019, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 145: adr = 0000000080003488 sim = 0000000000000018, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 146: adr = 0000000080003490 sim = 0000000000000068, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 147: adr = 0000000080003498 sim = 0000000000000060, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 148: adr = 00000000800034a0 sim = 00000000000001a0, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 149: adr = 00000000800034a8 sim = 0000000000000180, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 150: adr = 00000000800034b0 sim = 0000000000000680, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 151: adr = 00000000800034b8 sim = 0000000000000600, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 152: adr = 00000000800034c0 sim = 0000000000001a00, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 153: adr = 00000000800034c8 sim = 0000000000001800, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 154: adr = 00000000800034d0 sim = 0000000000006800, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 155: adr = 00000000800034d8 sim = 0000000000006000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 156: adr = 00000000800034e0 sim = 000000000001a000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 157: adr = 00000000800034e8 sim = 0000000000018000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 158: adr = 00000000800034f0 sim = 0000000000068000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 159: adr = 00000000800034f8 sim = 0000000000060000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 160: adr = 0000000080003500 sim = 00000000001a0000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 161: adr = 0000000080003508 sim = 0000000000180000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 162: adr = 0000000080003510 sim = 0000000000680000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 163: adr = 0000000080003518 sim = 0000000000600000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 164: adr = 0000000080003520 sim = 0000000001a00000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 165: adr = 0000000080003528 sim = 0000000001800000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 166: adr = 0000000080003530 sim = 0000000006800000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 167: adr = 0000000080003538 sim = 0000000006000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 168: adr = 0000000080003540 sim = 000000001a000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 169: adr = 0000000080003548 sim = 0000000018000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 170: adr = 0000000080003550 sim = 0000000068000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 171: adr = 0000000080003558 sim = 0000000060000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 172: adr = 0000000080003560 sim = 00000001a0000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 173: adr = 0000000080003568 sim = 0000000180000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 174: adr = 0000000080003570 sim = 0000000680000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 175: adr = 0000000080003578 sim = 0000000600000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 176: adr = 0000000080003580 sim = 0000001a00000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 177: adr = 0000000080003588 sim = 0000001800000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 178: adr = 0000000080003590 sim = 0000006800000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 179: adr = 0000000080003598 sim = 0000006000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 180: adr = 00000000800035a0 sim = 000001a000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 181: adr = 00000000800035a8 sim = 0000018000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 182: adr = 00000000800035b0 sim = 0000068000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 183: adr = 00000000800035b8 sim = 0000060000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 184: adr = 00000000800035c0 sim = 00001a0000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 185: adr = 00000000800035c8 sim = 0000180000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 186: adr = 00000000800035d0 sim = 0000680000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 187: adr = 00000000800035d8 sim = 0000600000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 188: adr = 00000000800035e0 sim = 0001a00000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 189: adr = 00000000800035e8 sim = 0001800000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 190: adr = 00000000800035f0 sim = 0006800000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 191: adr = 00000000800035f8 sim = 0006000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 192: adr = 0000000080003600 sim = 001a000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 193: adr = 0000000080003608 sim = 0018000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 194: adr = 0000000080003610 sim = 0068000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 195: adr = 0000000080003618 sim = 0060000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 196: adr = 0000000080003620 sim = 01a0000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 197: adr = 0000000080003628 sim = 0180000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 198: adr = 0000000080003630 sim = 0680000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 199: adr = 0000000080003638 sim = 0600000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 200: adr = 0000000080003640 sim = 1a00000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 201: adr = 0000000080003648 sim = 1800000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 202: adr = 0000000080003650 sim = 6800000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 203: adr = 0000000080003658 sim = 6000000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 204: adr = 0000000080003660 sim = 0000000000000000, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 205: adr = 0000000080003668 sim = 9ffffffffffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 206: adr = 0000000080003670 sim = 9ffffffffffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 207: adr = 0000000080003678 sim = 9ffffffffffffff9, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 208: adr = 0000000080003680 sim = 9ffffffffffffff9, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 209: adr = 0000000080003688 sim = 9fffffffffffffea, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 210: adr = 0000000080003690 sim = 9fffffffffffffe7, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 211: adr = 0000000080003698 sim = 9fffffffffffffa6, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 212: adr = 00000000800036a0 sim = 9fffffffffffff9f, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 213: adr = 00000000800036a8 sim = 9ffffffffffffe9e, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 214: adr = 00000000800036b0 sim = 9ffffffffffffe7f, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 215: adr = 00000000800036b8 sim = 9ffffffffffffa7e, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 216: adr = 00000000800036c0 sim = 9ffffffffffff9ff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 217: adr = 00000000800036c8 sim = 9fffffffffffe9fe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 218: adr = 00000000800036d0 sim = 9fffffffffffe7ff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 219: adr = 00000000800036d8 sim = 9fffffffffffa7fe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 220: adr = 00000000800036e0 sim = 9fffffffffff9fff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 221: adr = 00000000800036e8 sim = 9ffffffffffe9ffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 222: adr = 00000000800036f0 sim = 9ffffffffffe7fff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 223: adr = 00000000800036f8 sim = 9ffffffffffa7ffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 224: adr = 0000000080003700 sim = 9ffffffffff9ffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 225: adr = 0000000080003708 sim = 9fffffffffe9fffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 226: adr = 0000000080003710 sim = 9fffffffffe7ffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 227: adr = 0000000080003718 sim = 9fffffffffa7fffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 228: adr = 0000000080003720 sim = 9fffffffff9fffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 229: adr = 0000000080003728 sim = 9ffffffffe9ffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 230: adr = 0000000080003730 sim = 9ffffffffe7fffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 231: adr = 0000000080003738 sim = 9ffffffffa7ffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 232: adr = 0000000080003740 sim = 9ffffffff9ffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 233: adr = 0000000080003748 sim = 9fffffffe9fffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 234: adr = 0000000080003750 sim = 9fffffffe7ffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 235: adr = 0000000080003758 sim = 9fffffffa7fffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 236: adr = 0000000080003760 sim = 9fffffff9fffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 237: adr = 0000000080003768 sim = 9ffffffe9ffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 238: adr = 0000000080003770 sim = 9ffffffe7fffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 239: adr = 0000000080003778 sim = 9ffffffa7ffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 240: adr = 0000000080003780 sim = 9ffffff9ffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 241: adr = 0000000080003788 sim = 9fffffe9fffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 242: adr = 0000000080003790 sim = 9fffffe7ffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 243: adr = 0000000080003798 sim = 9fffffa7fffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 244: adr = 00000000800037a0 sim = 9fffff9fffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 245: adr = 00000000800037a8 sim = 9ffffe9ffffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 246: adr = 00000000800037b0 sim = 9ffffe7fffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 247: adr = 00000000800037b8 sim = 9ffffa7ffffffffe, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 248: adr = 00000000800037c0 sim = 9ffff9ffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 249: adr = 00000000800037c8 sim = 9fffe9ffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 250: adr = 00000000800037d0 sim = 9fffe7ffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 251: adr = 00000000800037d8 sim = 9fffa7ffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 252: adr = 00000000800037e0 sim = 9fff9fffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 253: adr = 00000000800037e8 sim = 9ffe9fffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 254: adr = 00000000800037f0 sim = 9ffe7fffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 255: adr = 00000000800037f8 sim = 9ffa7fffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 256: adr = 0000000080003800 sim = 9ff9ffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 257: adr = 0000000080003808 sim = 9fe9ffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 258: adr = 0000000080003810 sim = 9fe7ffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 259: adr = 0000000080003818 sim = 9fa7ffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 260: adr = 0000000080003820 sim = 9f9fffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 261: adr = 0000000080003828 sim = 9e9fffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 262: adr = 0000000080003830 sim = 9e7fffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 263: adr = 0000000080003838 sim = 9a7fffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 264: adr = 0000000080003840 sim = 99ffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 265: adr = 0000000080003848 sim = 99ffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 266: adr = 0000000080003850 sim = 97ffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 267: adr = 0000000080003858 sim = 67ffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 268: adr = 0000000080003860 sim = 5fffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 269: adr = 0000000080003868 sim = 9fffffffffffffff, signature = ffffffffffffffff +# Error on test rv64m/I-DIVU-01 result 272: adr = 0000000080003880 sim = 9a59a6656a996a65, signature = ffffffffffffffff +# rv64m/I-DIVU-01 failed with 132 errors. :( +# Read memfile ../../imperas-riscv-tests/work/rv64mmu/WALLY-VIRTUALMEMORY.elf.memfile +# Code ended with ecall with gp = 1 +# rv64mmu/WALLY-VIRTUALMEMORY succeeded. Brilliant!!! +# FAIL: 1 test programs had errors +# ** Note: $stop : ../testbench/testbench-imperas-div.sv(572) +# Time: 15284605 ns Iteration: 0 Instance: /testbench +# Break at ../testbench/testbench-imperas-div.sv line 572 +# Stopped at ../testbench/testbench-imperas-div.sv line 572 +# End time: 08:48:38 on May 17,2021, Elapsed time: 0:00:19 +# Errors: 0, Warnings: 0 diff --git a/wally-pipelined/regression/div b/wally-pipelined/regression/div new file mode 100755 index 0000000000000000000000000000000000000000..46110cb429522d9fa376287c85948d35a0a495c8 GIT binary patch literal 16696 zcmeHOZ)_Y#6`#9{>=l$W0RmX*_?f6`>Ok6 z?)KVq1x=9Cpi^oHAF3j#An*l5snliOm z!K0Pp=|ly}Fe&mZgwyU2**P&n`ixiyrUO@v_{XVlAK5i3(v5H;*Tcy5?FT!)rKaVb z&wQJEsJ{8`gGTXZr0|MOsbqi4woR#cQ!1G$6q|~zEln-k)O=RmA}hvrVIA0~cJ1jC z;ARpz3ZuLiD@n%kyYnrld@p?E$kd-ddUM+!YF|J4V*5(=fpww|CbZ`+fim|8)G@FB zt4LS6_oc+|(vq0xv=exxO4$R<#0XG6}1l$PxUq#@rb?ZLT#@_X7r)yr`B!u?Fq~R@3X=5+?&&xQJ zw|^Vx>*agD15no>P=6RpuD|_yxm-SjGL$|iOCv&-gIuu6o8OC;E*;fMZ)jtGn%URe zJzn!641KlnWydA7odb8}RXt#GH=E{qH>YUfZo8NHf~6JEuXt3^;=qqMZhf(gnDVLID0_GZj`aSU^Mh(#!%0*XgYy1`4|b2YJ$t_p z;V(o>e+>6UOCN-L!=-=rY2!`L0DYi)<1OqX)4#t3?K*eMXEbbnh2q~`y53!SKT>)t zTweK_Hg?{l?Rd5D4)&kJN5T(E0IJ2KKJ)H5Z^?e4W%>ut4-TX_r zTm-D2DVNUzHUi?*vK8k*z}(6e@Ft^W*^ zA&=ksr@%K(#zmwSKd*`naBPF42)qI)0>Q38{pahJJnBCocCLBwzO5VNXGXMt2#yiZ zlZL1Z33&sKVF!>G30>N*1qk;Ob z`#J;4_=3(r0ZUo#2{3j9M^@qIPkfv9aHHAyr2~CEUkzAxj zpQ}mcb&YFD=JkqeNapp8IA6lV#B#56U8`9_kt-IJsTi#ugvf9ptQy?>O=>w~yT z3cjAo>-CdA_<}2Cjyp^frF?^~|L-L8b&&i28t{5>r^9CJ%V2)KvPPU4NnAerM-v1@})o?-zXE?EE6Z_uI}d7TmAw{E|xlv-9vYR=F=e*hQgK z z8+QIKQLW$l;4Q$6QFq|d(_QiRjXGBdaTybCnw&(a(oC3p~bw8Pom*B&o-8x!9`6MDRmPLG0#Mbbgju&KtAk3frby{jj@yHoGn6VYL(h+Qo%^vD?Lwb z3Q(|BNAJ|ggBIx#`mXN1?cr{HZ&%lW&R)GY+}_=ZUgbuXfqX$W_|98b67iT3qa87! zkZs3{b3cr;7%k0BFHog@2aF!iXZ7J&CXTyfqI*Frp3LZld;%_UwsjaIko)s_awB)$ z=sIk!;Q-;To2pxB?3;J&O%rNViKZ)FkP%~L0p$=sV>PRj-lE@jO z7OKCHgzZkCQmLC>sd^7`9m}un8l1CD`d@`G{2|ASJ5~&y(P;Mk; z2vuIW3R!h13nFIni2H8hWhrQTaGB{?fst2k%fb@i>c-$LmxqbvciC4;3uLVJ zhiH7pxPcW3`Mt(;)M3x#J4S^S37z%_f&UQ3*nIsw4`Jl`c@LDc{V}k|ISAYHc#-i( zR4-m5#+mJTzK{eCFPZImT*-J6%B%@}Sksq4z&Qll^Z1hy$03-w{jA6MIF#X>gk>J5 zGAd{c$=QCB6=EDR7*n?A@hsycDRTYJ>wlW;+evSleyABaPH2yLr~UVV!n!#>{+(V`kXiij}@+(G8KqdU`Q@8p>2SxIO${Sp*!n h-C`~d;SUoepTjxVYnI}eySn}1R#Rh*!@wbme*u1SeFgvk literal 0 HcmV?d00001 diff --git a/wally-pipelined/regression/div.c b/wally-pipelined/regression/div.c new file mode 100644 index 000000000..c1d6438bf --- /dev/null +++ b/wally-pipelined/regression/div.c @@ -0,0 +1,23 @@ +#include +#include +#include + +int main() { + + uint64_t N; + uint64_t D; + uint64_t Q; + + N = 0xdf7f3844121bcc23; + D = 0x10fd3dedadea5195; + N = 0xffffffffffffffff; + D = 0x0000000000000000; + + printf("N = %" PRIx64 "\n", N); + printf("D = %" PRIx64 "\n", D); + printf("Q = %" PRIx64 "\n", Q); + printf("R = %" PRIx64 "\n", N%D); + + + +} diff --git a/wally-pipelined/regression/div.c~ b/wally-pipelined/regression/div.c~ new file mode 100644 index 000000000..895f2102f --- /dev/null +++ b/wally-pipelined/regression/div.c~ @@ -0,0 +1,21 @@ +#include +#include +#include + +int main() { + + uint64_t N; + uint64_t D; + uint64_t Q; + + N = 0xdf7f3844121bcc23; + D = 0x10fd3dedadea5195; + + printf("N = %" PRIx64 "\n", N); + printf("D = %" PRIx64 "\n", D); + printf("Q = %" PRIx64 "\n", Q); + printf("R = %" PRIx64 "\n", N%D); + + + +} diff --git a/wally-pipelined/regression/sim-wally-batch-muldiv b/wally-pipelined/regression/sim-wally-batch-muldiv index c9db7ed18..2c8089ef5 100755 --- a/wally-pipelined/regression/sim-wally-batch-muldiv +++ b/wally-pipelined/regression/sim-wally-batch-muldiv @@ -1,3 +1,3 @@ vsim -c < +#include +#include + +int main() { + + uint64_t N; + uint64_t D; + uint64_t Q; + + D = 0xdf7f3844121bcc23; + N = 0x10fd3dedadea5195; + Q = N/D; + + printf("N = %" PRIx64 "\n", N); + printf("D = %" PRIx64 "\n", D); + printf("Q = %" PRIx64 "\n", Q); + printf("R = %" PRIx64 "\n", N%D); + + + +} diff --git a/wally-pipelined/regression/vish_stacktrace.vstf b/wally-pipelined/regression/vish_stacktrace.vstf index 671bfd098..a48421878 100644 --- a/wally-pipelined/regression/vish_stacktrace.vstf +++ b/wally-pipelined/regression/vish_stacktrace.vstf @@ -1,3 +1,24 @@ # transcript error: error writing "stdout": broken pipe while executing "puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" +# transcript error: error writing "stdout": broken pipe + while executing +"puts -nonewline stdout $s" diff --git a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do index 5e1410b92..47d9d8122 100644 --- a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do +++ b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do @@ -30,9 +30,9 @@ vlib work_$2 # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32ic rv32ic switch $argc { - 0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} - 1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} - 2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} + 0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583} + 1 {vlog +incdir+$1 ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583} + 2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583} } # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals diff --git a/wally-pipelined/regression/wally-pipelined-muldiv.do b/wally-pipelined/regression/wally-pipelined-muldiv.do index b897e0278..8c55956bc 100644 --- a/wally-pipelined/regression/wally-pipelined-muldiv.do +++ b/wally-pipelined/regression/wally-pipelined-muldiv.do @@ -30,15 +30,14 @@ vlib work # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined.do ../config/rv32ic switch $argc { - 0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} - 1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} + 0 {vlog +incdir+../config/rv64imc ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583} + 1 {vlog +incdir+$1 ../testbench/testbench-imperas-div.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} } # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt +acc work.testbench -o workopt vsim workopt - view wave -- display input and output signals as hexidecimal values @@ -47,8 +46,8 @@ do ./wave-dos/ahb-muldiv.do -- Set Wave Output Items TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 140 +configure wave -namecolwidth 350 +configure wave -valuecolwidth 240 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 diff --git a/wally-pipelined/regression/wave-dos/ahb-muldiv.do b/wally-pipelined/regression/wave-dos/ahb-muldiv.do index 68d2a213b..dedf0ba50 100644 --- a/wally-pipelined/regression/wave-dos/ahb-muldiv.do +++ b/wally-pipelined/regression/wave-dos/ahb-muldiv.do @@ -6,12 +6,13 @@ add wave /testbench/clk add wave /testbench/reset add wave -divider +# new #add wave /testbench/dut/hart/ebu/IReadF -add wave -noupdate -divider -height 32 "Stalls" add wave /testbench/dut/hart/DataStall -add wave /testbench/dut/hart/InstrStall +add wave /testbench/dut/hart/ICacheStallF add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallD + add wave /testbench/dut/hart/StallE add wave /testbench/dut/hart/StallM add wave /testbench/dut/hart/StallW @@ -28,27 +29,15 @@ add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE add wave -hex /testbench/dut/hart/mdu/genblk1/div/fsm1/NEXT_STATE add wave -hex /testbench/dut/hart/mdu/genblk1/div/* - - add wave -noupdate -divider -height 32 "RF" add wave -hex /testbench/dut/hart/ieu/dp/regf/* add wave -hex /testbench/dut/hart/ieu/dp/regf/rf - add wave -divider add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD - add wave /testbench/InstrDName -add wave -hex /testbench/dut/hart/ifu/ic/InstrRawD -add wave -hex /testbench/dut/hart/ifu/ic/AlignedInstrD -add wave -divider -add wave -hex /testbench/dut/hart/ifu/ic/InstrPAdrF -add wave /testbench/dut/hart/ifu/ic/DelayF -add wave /testbench/dut/hart/ifu/ic/DelaySideF -add wave /testbench/dut/hart/ifu/ic/DelayD -add wave -hex /testbench/dut/hart/ifu/ic/MisalignedHalfInstrD add wave -divider add wave -hex /testbench/dut/hart/ifu/PCE @@ -79,7 +68,6 @@ add wave -hex /testbench/dut/hart/ebu/HRDATA add wave -hex /testbench/dut/hart/ebu/HWRITE add wave -hex /testbench/dut/hart/ebu/HWDATA add wave -hex /testbench/dut/hart/ebu/CaptureDataM -add wave -hex /testbench/dut/hart/ebu/InstrStall add wave -divider add wave -hex /testbench/dut/uncore/dtim/* @@ -97,17 +85,15 @@ add wave -divider add wave -hex /testbench/dut/uncore/dtim/* add wave -divider -add wave -hex -r /testbench/* - # appearance TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 150 +configure wave -namecolwidth 350 +configure wave -valuecolwidth 250 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 -set DefaultRadix hexadecimal \ No newline at end of file +set DefaultRadix hexadecimal diff --git a/wally-pipelined/regression/wave-dos/ahb-waves.do b/wally-pipelined/regression/wave-dos/ahb-waves.do index 48b89b6b5..add1ab22b 100644 --- a/wally-pipelined/regression/wave-dos/ahb-waves.do +++ b/wally-pipelined/regression/wave-dos/ahb-waves.do @@ -86,4 +86,4 @@ configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 configure wave -childrowmargin 2 -set DefaultRadix hexadecimal \ No newline at end of file +set DefaultRadix hexadecimal diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 4040fdc3e..308a934ae 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -30,15 +30,15 @@ /* verilator lint_off IMPLICIT */ -module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start); +module div (Qf, remf, done, divBusy, div0, N, D, clk, reset, start); input logic [63:0] N, D; input logic clk; input logic reset; input logic start; - output logic [63:0] Q; - output logic [63:0] rem0; + output logic [63:0] Qf; + output logic [63:0] remf; output logic div0; output logic done; output logic divBusy; @@ -51,10 +51,11 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start); logic [5:0] P, NumIter, RemShift; logic [63:0] op1, op2, op1shift, Rem5; logic [64:0] Qd, Rd, Qd2, Rd2; + logic [63:0] Q, rem0; logic [3:0] quotient; logic otfzero; logic shiftResult; - logic enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp; + logic enablev, state0v, donev, divdonev, oftzerov, divBusyv, ulp; // Divider goes the distance to 37 cycles // (thanks the evil divisor for D = 0x1) @@ -112,9 +113,6 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start); // shifting N right by v+s so that (m+v+s) mod k = 0. And, // the quotient has to be aligned to the integer position. - // Used a Brent-Kung for no reason (just wanted prefix -- might - // have gotten away with a RCA) - // Actual divider unit FIXME: r16 (jes) divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, enable, otfzero, shiftResult); @@ -131,6 +129,10 @@ module div (Q, rem0, done, divBusy, div0, N, D, clk, reset, start); // n ln(r) shifter_r64 p4 (rem0, Rem5, RemShift); + // RISC-V has exceptions for divide by 0 (Table 6.1 of SPEC) + mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf); + mux2 #(64) exc2 (rem0, op1, div0, remf); + endmodule // int32div module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, diff --git a/wally-pipelined/src/muldiv/div/div b/wally-pipelined/src/muldiv/div/div index 35202318fe6d76f55c1e2438964866be86baf90e..e0bbf726502af2947a56ee033ab0096d048a17d1 100755 GIT binary patch delta 691 zcmdnd#JHo0aRUb<=TRmGFgQ9{kWrs=0waVsVY4TrKBJ(60)z{vCwDU47rFM@E%LHi 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0x10fd3dedadea5195; - //D = 0xdf7f3844121bcc23; - N = 0x4; - D = 0xbfffffffffffffff; - Q = N/D; + int exponent; + int base; + + base = 2; + exponent = 32; + val2 = 1; + while (exponent != 0) { + val2 *= base; + exponent --; + } + + val = pow(2.0, 64) - 1; + N = 0xdf7f3844121bcc23; + D = 0x10fd3dedadea5195; printf("N = %" PRIx64 "\n", N); printf("D = %" PRIx64 "\n", D); printf("Q = %" PRIx64 "\n", Q); - printf("R = %" PRIx64 "\n", N%D); + printf("R = %" PRIx64 "\n", N%D); + + printf("val = %" PRIx64 "\n", val2-1); diff --git a/wally-pipelined/src/muldiv/div/div64.out b/wally-pipelined/src/muldiv/div/div64.out index 4c7315926..6bfa9dd9d 100644 --- a/wally-pipelined/src/muldiv/div/div64.out +++ b/wally-pipelined/src/muldiv/div/div64.out @@ -1,67 +1,107 @@ -0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1 -0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 | 0000000000000000 0000000000000000 1 1 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+ffffffffffffffff 0000000000000000 | ffffffffffffffff ffffffffffffffff | 0000000000000000 0000000000000000 0 0 diff --git a/wally-pipelined/src/muldiv/div/divide4x64.sv b/wally-pipelined/src/muldiv/div/divide4x64.sv index 2f56f0eb7..4b474c654 100755 --- a/wally-pipelined/src/muldiv/div/divide4x64.sv +++ b/wally-pipelined/src/muldiv/div/divide4x64.sv @@ -1,12 +1,12 @@ -module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); +module int64div (Qf, done, divdone, remf, div0, N, D, clk, reset, start); input logic [63:0] N, D; input logic clk; input logic reset; input logic start; - output logic [63:0] Q; - output logic [63:0] rem0; + output logic [63:0] Qf; + output logic [63:0] remf; output logic div0; output logic done; output logic divdone; @@ -18,6 +18,7 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); logic [5:0] P, NumIter, RemShift; logic [63:0] op1, op2, op1shift, Rem5; logic [64:0] Qd, Rd, Qd2, Rd2; + logic [63:0] Q, rem0; logic [3:0] quotient; logic otfzero; logic shiftResult; @@ -80,9 +81,6 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); // shifting N right by v+s so that (m+v+s) mod k = 0. And, // the quotient has to be aligned to the integer position. - // Used a Brent-Kung for no reason (just wanted prefix -- might - // have gotten away with a RCA) - // Actual divider unit FIXME: r16 (jes) divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, enable, otfzero, shiftResult); @@ -96,9 +94,13 @@ module int64div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); assign Rem5 = Rd2[64:1]; // Adjust remainder by m (no need to adjust by - // n ln(r) + // n lg(r) shifter_r64 p4 (rem0, Rem5, RemShift); + // RISC-V has exceptions for divide by 0 (see Table 6.1 of spec) + mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf); + mux2 #(64) exc2 (rem0, op1, div0, remf); + endmodule // int32div module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, @@ -252,7 +254,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, endgenerate assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0}; -endmodule // adder +endmodule // csa module flopenr #(parameter WIDTH = 8) (input logic clk, reset, en, diff --git a/wally-pipelined/src/muldiv/div/imperas-riscv-tests b/wally-pipelined/src/muldiv/div/imperas-riscv-tests new file mode 160000 index 000000000..c171bf199 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/imperas-riscv-tests @@ -0,0 +1 @@ +Subproject commit c171bf1999a3cf7e8cd26511dfcf794d1498e5a1 diff --git a/wally-pipelined/src/muldiv/div/int64div.do b/wally-pipelined/src/muldiv/div/int64div.do index 4e01c6872..dc83d046f 100755 --- a/wally-pipelined/src/muldiv/div/int64div.do +++ b/wally-pipelined/src/muldiv/div/int64div.do @@ -70,6 +70,8 @@ add wave -hex /tb/dut/N add wave -hex /tb/dut/D add wave -hex /tb/dut/reset add wave -hex /tb/dut/start +add wave -hex /tb/dut/Qf +add wave -hex /tb/dut/remf add wave -hex /tb/dut/Q add wave -hex /tb/dut/rem0 add wave -hex /tb/dut/div0 @@ -99,8 +101,8 @@ add wave -hex -r /tb/dut/p3/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 +configure wave -namecolwidth 350 +configure wave -valuecolwidth 200 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 @@ -109,6 +111,6 @@ configure wave -rowmargin 4 configure wave -childrowmargin 2 -- Run the Simulation -run 338ns +run 538ns diff --git a/wally-pipelined/src/muldiv/div/shift.sv b/wally-pipelined/src/muldiv/div/shift.sv new file mode 100644 index 000000000..412cee32f --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift.sv @@ -0,0 +1,151 @@ +module shifter_l64 (Z, A, Shift); + + input logic [63:0] A; + input logic [5:0] Shift; + + logic [63:0] stage1; + logic [63:0] stage2; + logic [63:0] stage3; + logic [63:0] stage4; + logic [63:0] stage5; + logic [31:0] thirtytwozeros = 32'h0; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [63:0] Z; + + mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); + +endmodule // shifter_l64 + +module shifter_r64 (Z, A, Shift); + + input logic [63:0] A; + input logic [5:0] Shift; + + logic [63:0] stage1; + logic [63:0] stage2; + logic [63:0] stage3; + logic [63:0] stage4; + logic [63:0] stage5; + logic [31:0] thirtytwozeros = 32'h0; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [63:0] Z; + + mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); + +endmodule // shifter_r64 + +module shifter_l32 (Z, A, Shift); + + input logic [31:0] A; + input logic [4:0] Shift; + + logic [31:0] stage1; + logic [31:0] stage2; + logic [31:0] stage3; + logic [31:0] stage4; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [31:0] Z; + + mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); + +endmodule // shifter_l32 + +module shifter_r32 (Z, A, Shift); + + input logic [31:0] A; + input logic [4:0] Shift; + + logic [31:0] stage1; + logic [31:0] stage2; + logic [31:0] stage3; + logic [31:0] stage4; + logic [15:0] sixteenzeros = 16'h0; + logic [ 7:0] eightzeros = 8'h0; + logic [ 3:0] fourzeros = 4'h0; + logic [ 1:0] twozeros = 2'b00; + logic onezero = 1'b0; + + output logic [31:0] Z; + + mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); + +endmodule // shifter_r32 + +`define XLEN 32 +module shift_right #(parameter WIDTH=8) (input logic [`XLEN-1:0] A, + input logic [$clog2(`XLEN)-1:0] Shift, + output logic [`XLEN-1:0] Z); + + logic [`XLEN-1:0] stage [$clog2(`XLEN):0]; + genvar i; + + assign stage[0] = A; + generate + for (i=0;i<$clog2(`XLEN);i=i+1) + begin : genbit + mux2 #(`XLEN) mux_inst (stage[i], + {{(`XLEN/(2**(i+1))){1'b0}}, stage[i][`XLEN-1:`XLEN/(2**(i+1))]}, + Shift[$clog2(`XLEN)-i-1], + stage[i+1]); + end + endgenerate + assign Z = stage[$clog2(`XLEN)]; + +endmodule // shift_right + +module shift_left #(parameter WIDTH=8) (input logic [`XLEN-1:0] A, + input logic [$clog2(`XLEN)-1:0] Shift, + output logic [`XLEN-1:0] Z); + + logic [`XLEN-1:0] stage [$clog2(`XLEN):0]; + genvar i; + + assign stage[0] = A; + generate + for (i=0;i<$clog2(`XLEN);i=i+1) + begin : genbit + mux2 #(`XLEN) mux_inst (stage[i], + {stage[i][`XLEN-1-`XLEN/(2**(i+1)):0], {(`XLEN/(2**(i+1))){1'b0}}}, + Shift[$clog2(`XLEN)-i-1], + stage[i+1]); + end + endgenerate + assign Z = stage[$clog2(`XLEN)]; + +endmodule // shift_right + + + diff --git a/wally-pipelined/src/muldiv/div/shift_left.do b/wally-pipelined/src/muldiv/div/shift_left.do new file mode 100755 index 000000000..0b0ce9850 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_left.do @@ -0,0 +1,55 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux_div.sv shift.sv shift_left_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 800ns +quit diff --git a/wally-pipelined/src/muldiv/div/shift_left.out b/wally-pipelined/src/muldiv/div/shift_left.out new file mode 100644 index 000000000..67fedc18f --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_left.out @@ -0,0 +1,79 @@ +12153524 01 || 242a6a48 242a6a48 | 1 +8484d609 03 || 2426b048 2426b048 | 1 +06b97b0d 0d || 2f61a000 2f61a000 | 1 +b2c28465 12 || 11940000 11940000 | 1 +00f3e301 0d || 7c602000 7c602000 | 1 +3b23f176 1d || c0000000 c0000000 | 1 +76d457ed 0c || 457ed000 457ed000 | 1 +7cfde9f9 06 || 3f7a7e40 3f7a7e40 | 1 +e2f784c5 0a || de131400 de131400 | 1 +72aff7e5 17 || f2800000 f2800000 | 1 +8932d612 0f || 6b090000 6b090000 | 1 +793069f2 0e || 1a7c8000 1a7c8000 | 1 +f4007ae8 05 || 800f5d00 800f5d00 | 1 +2e58495c 1d || 80000000 80000000 | 1 +96ab582d 05 || d56b05a0 d56b05a0 | 1 +b1ef6263 0a || bd898c00 bd898c00 | 1 +c03b2280 00 || c03b2280 c03b2280 | 1 +557845aa 1d || 40000000 40000000 | 1 +cb203e96 13 || f4b00000 f4b00000 | 1 +86bc380d 13 || c0680000 c0680000 | 1 +359fdd6b 15 || ad600000 ad600000 | 1 +81174a02 0e || d2808000 d2808000 | 1 +0effe91d 0f || f48e8000 f48e8000 | 1 +11844923 0a || 11248c00 11248c00 | 1 +e5730aca 1c || a0000000 a0000000 | 1 +7968bdf2 0a || a2f7c800 a2f7c800 | 1 +20c4b341 18 || 41000000 41000000 | 1 +3c20f378 09 || 41e6f000 41e6f000 | 1 +75c50deb 16 || 7ac00000 7ac00000 | 1 +634bf9c6 0e || fe718000 fe718000 | 1 +de7502bc 0a || d40af000 d40af000 | 1 +85d79a0b 11 || 34160000 34160000 | 1 +42f24185 0f || 20c28000 20c28000 | 1 +9dcc603b 1a || ec000000 ec000000 | 1 +bf23327e 15 || 4fc00000 4fc00000 | 1 +78d99bf1 19 || e2000000 e2000000 | 1 +31230762 0c || 30762000 30762000 | 1 +4fa1559f 0f || aacf8000 aacf8000 | 1 +7c6da9f8 17 || fc000000 fc000000 | 1 +cfc4569f 1c || f0000000 f0000000 | 1 +adcbc05b 09 || 9780b600 9780b600 | 1 +a4ae3249 10 || 32490000 32490000 | 1 +ebfec0d7 11 || 81ae0000 81ae0000 | 1 +4b212f96 0c || 12f96000 12f96000 | 1 +e12ccec2 08 || 2ccec200 2ccec200 | 1 +bb825a77 1d || e0000000 e0000000 | 1 +090cdb12 1e || 80000000 80000000 | 1 +36e5816d 19 || da000000 da000000 | 1 +0fd28f1f 13 || 78f80000 78f80000 | 1 +42d92f85 18 || 85000000 85000000 | 1 +2dda595b 09 || b4b2b600 b4b2b600 | 1 +9ff2ae3f 0a || cab8fc00 cab8fc00 | 1 +2c156358 06 || 0558d600 0558d600 | 1 +c71a0c8e 1c || e0000000 e0000000 | 1 +7d3599fa 06 || 4d667e80 4d667e80 | 1 +39961773 03 || ccb0bb98 ccb0bb98 | 1 +9799a82f 13 || 41780000 41780000 | 1 +afd8565f 04 || fd8565f0 fd8565f0 | 1 +7bf8fdf7 0b || c7efb800 c7efb800 | 1 +f3091ae6 1a || 98000000 98000000 | 1 +14cfc129 0d || f8252000 f8252000 | 1 +ed536cda 05 || aa6d9b40 aa6d9b40 | 1 +da8ae2b5 1f || 80000000 80000000 | 1 +3cf11979 04 || cf119790 cf119790 | 1 +e8740cd0 0a || d0334000 d0334000 | 1 +55f6adab 0e || ab6ac000 ab6ac000 | 1 +6e5daddc 1a || 70000000 70000000 | 1 +fedf72fd 03 || f6fb97e8 f6fb97e8 | 1 +2b0eed56 0e || bb558000 bb558000 | 1 +b3d97667 0a || 65d99c00 65d99c00 | 1 +5b6fb9b6 18 || b6000000 b6000000 | 1 +3cd18779 18 || 79000000 79000000 | 1 +4a74bf94 13 || fca00000 fca00000 | 1 +823f2c04 19 || 08000000 08000000 | 1 +6dcb69db 0d || 6d3b6000 6d3b6000 | 1 +6cb0b7d9 0d || 16fb2000 16fb2000 | 1 +bb45e276 0a || 1789d800 1789d800 | 1 +5b172db6 15 || b6c00000 b6c00000 | 1 +a3071a46 04 || 3071a460 3071a460 | 1 diff --git a/wally-pipelined/src/muldiv/div/shift_left_tb.sv b/wally-pipelined/src/muldiv/div/shift_left_tb.sv new file mode 100644 index 000000000..2d5d3dad8 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_left_tb.sv @@ -0,0 +1,71 @@ +// +// File name : tb +// Title : test +// project : HW3 +// Library : test +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +// Top level stimulus module + +`timescale 1ns/1ps + +`define XLEN 32 +module stimulus; + + logic [`XLEN-1:0] A; + logic [$clog2(`XLEN)-1:0] Shift; + logic [`XLEN-1:0] Z; + logic [`XLEN-1:0] Z_corr; + + //logic [63:0] A; + //logic [5:0] Shift; + //logic [63:0] Z; + //logic [63:0] Z_corr; + //logic [63:0] Z_orig; + + + logic clk; + + integer handle3; + integer desc3; + integer i; + + // instatiate part to test + shift_left dut1 (A, Shift, Z); + assign Z_corr = (A << Shift); + + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + handle3 = $fopen("shift_left.out"); + desc3 = handle3; + end + + initial + begin + for (i=0; i < 256; i=i+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + A = $random; + Shift = $random; + end + @(negedge clk) + begin + $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); + end + end // for (i=0; i < 256; i=i+1) + $finish;// + end // initial begin + +endmodule // stimulus diff --git a/wally-pipelined/src/muldiv/div/shift_right.do b/wally-pipelined/src/muldiv/div/shift_right.do new file mode 100755 index 000000000..a41b7bfa7 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_right.do @@ -0,0 +1,55 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux_div.sv shift.sv shift_right_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 800ns +quit diff --git a/wally-pipelined/src/muldiv/div/shift_right.out b/wally-pipelined/src/muldiv/div/shift_right.out new file mode 100644 index 000000000..42202ab57 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_right.out @@ -0,0 +1,24 @@ +12153524 01 || 090a9a92 090a9a92 | 1 +8484d609 03 || 10909ac1 10909ac1 | 1 +06b97b0d 0d || 000035cb 000035cb | 1 +b2c28465 12 || 00002cb0 00002cb0 | 1 +00f3e301 0d || 0000079f 0000079f | 1 +3b23f176 1d || 00000001 00000001 | 1 +76d457ed 0c || 00076d45 00076d45 | 1 +7cfde9f9 06 || 01f3f7a7 01f3f7a7 | 1 +e2f784c5 0a || 0038bde1 0038bde1 | 1 +72aff7e5 17 || 000000e5 000000e5 | 1 +8932d612 0f || 00011265 00011265 | 1 +793069f2 0e || 0001e4c1 0001e4c1 | 1 +f4007ae8 05 || 07a003d7 07a003d7 | 1 +2e58495c 1d || 00000001 00000001 | 1 +96ab582d 05 || 04b55ac1 04b55ac1 | 1 +b1ef6263 0a || 002c7bd8 002c7bd8 | 1 +c03b2280 00 || c03b2280 c03b2280 | 1 +557845aa 1d || 00000002 00000002 | 1 +cb203e96 13 || 00001964 00001964 | 1 +86bc380d 13 || 000010d7 000010d7 | 1 +359fdd6b 15 || 000001ac 000001ac | 1 +81174a02 0e || 0002045d 0002045d | 1 +0effe91d 0f || 00001dff 00001dff | 1 +11844923 0a || 00046112 00046112 | 1 diff --git a/wally-pipelined/src/muldiv/div/shift_right_tb.sv b/wally-pipelined/src/muldiv/div/shift_right_tb.sv new file mode 100755 index 000000000..b35277484 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shift_right_tb.sv @@ -0,0 +1,64 @@ +// +// File name : tb +// Title : test +// project : HW3 +// Library : test +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +// Top level stimulus module + +`timescale 1ns/1ps + +`define XLEN 32 +module stimulus; + + logic [`XLEN-1:0] A; + logic [$clog2(`XLEN)-1:0] Shift; + logic [`XLEN-1:0] Z; + logic [`XLEN-1:0] Z_corr; + + logic clk; + + integer handle3; + integer desc3; + integer i; + + // instatiate part to test + shift_right dut1 (A, Shift, Z); + assign Z_corr = (A >> Shift); + + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + handle3 = $fopen("shift_right.out"); + desc3 = handle3; + #250 $finish; + end + + initial + begin + for (i=0; i < 128; i=i+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + A = $random; + Shift = $random; + end + @(negedge clk) + begin + $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); + end + end // @(negedge clk) + end // for (j=0; j < 32; j=j+1) + +endmodule // stimulus diff --git a/wally-pipelined/src/muldiv/div/shifter.sv b/wally-pipelined/src/muldiv/div/shifter.sv new file mode 100644 index 000000000..779a02a47 --- /dev/null +++ b/wally-pipelined/src/muldiv/div/shifter.sv @@ -0,0 +1,18 @@ +module shifter_right(input logic signed [63:0] a, + input logic [ 5:0] shamt, + output logic signed [63:0] y); + + + y = a >> shamt; + +endmodule // shifter_right + +module shifter_left(input logic signed [63:0] a, + input logic [ 5:0] shamt, + output logic signed [63:0] y); + + + y = a << shamt; + +endmodule // shifter_right + diff --git a/wally-pipelined/src/muldiv/div/test_int64div.sv b/wally-pipelined/src/muldiv/div/test_int64div.sv index 995c26ffc..8e7f4cc2b 100644 --- a/wally-pipelined/src/muldiv/div/test_int64div.sv +++ b/wally-pipelined/src/muldiv/div/test_int64div.sv @@ -60,8 +60,8 @@ module tb; #0 start = 1'b0; #0 reset = 1'b1; #22 reset = 1'b0; - #25 N = 64'h10fd_3ded_adea_5195; - #0 D = 64'hdf7f_3844_121b_cc23; + #25 N = 64'hffff_ffff_ffff_ffff; + #0 D = 64'h0000_0000_0000_0000; #0 start = 1'b1; #50 start = 1'b0; diff --git a/wally-pipelined/src/muldiv/div/udiv b/wally-pipelined/src/muldiv/div/udiv new file mode 100755 index 0000000000000000000000000000000000000000..8b1ac689b125bcbebc7b536ebf471dadd896c360 GIT binary patch literal 16696 zcmeHOeQaA-6~DHVH2sLr7L+&zp`{F)K22`c}l<1gcYsbs}nnk!Lft= z+&LB6iqcJ3ZMF(&0x={u2?0{61md57fTa|=BEi)Dg9g*IGEwj*TGG-%_-M^J_nqUs z_u>>Z?LXd)?B6}V^KtJx@4n}I^WJ?X+|%v#cmx-p_>@5DSioe0q{#203P4b_i8}ah z6zfC{$W@Xv^+6LrYnC^>cC01d2Z(+RSgC*?HEF@fJw!ym1q*fv3nLu|`c)%OvJ+pV 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b/wally-pipelined/src/muldiv/muldiv.sv index 8d6619922..0df7e5d72 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -47,44 +47,52 @@ module muldiv ( logic [`XLEN-1:0] MulDivResultE, MulDivResultM; logic [`XLEN-1:0] PrelimResultE; logic [`XLEN-1:0] QuotE, RemE; - logic [`XLEN*2-1:0] ProdE; - + //logic [`XLEN-1:0] Q, R; + logic [`XLEN*2-1:0] ProdE; + + logic enable_q; + logic [2:0] Funct3E_Q; + logic div0error; + logic [`XLEN-1:0] N, D; + + logic gclk; logic DivStartE; - logic startDivideE; - - logic enable_q, gclk; - - logic [2:0] Funct3E_Q; - logic div0error; - - + logic startDivideE; + // Multiplier mul mul(.*); // Divide // *** replace this clock gater - always @(negedge clk) begin - enable_q <= ~StallM; - end - assign gclk = enable_q & clk; - - div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, SrcAE, SrcBE, gclk, reset, startDivideE); + always @(negedge clk) begin + enable_q <= ~StallM; + end + assign gclk = enable_q & clk; + + // capture the Numerator/Denominator + flopenrc #(`XLEN) reg_num (.d(SrcAE), .q(N), + .en(startDivideE), .clear(DivDoneE), + .reset(reset), .clk(~gclk)); + flopenrc #(`XLEN) reg_den (.d(SrcBE), .q(D), + .en(startDivideE), .clear(DivDoneE), + .reset(reset), .clk(~gclk)); + + div div (QuotE, RemE, DivDoneE, DivBusyE, div0error, N, D, gclk, reset, startDivideE); // Added for debugging of start signal for divide assign startDivideE = MulDivE&DivStartE&~DivBusyE; - - // capture the start control signals since they are not held constant. - flopenrc #(3) funct3ereg (.d(Funct3E), - .q(Funct3E_Q), - .en(DivStartE), - .clear(DivDoneE), - .reset(reset), - .clk(clk)); - - + + // capture the start control signals since they are not held constant. + flopenrc #(3) funct3ereg (.d(Funct3E), + .q(Funct3E_Q), + .en(DivStartE), + .clear(DivDoneE), + .reset(reset), + .clk(clk)); + // Select result always_comb -// case (DivDoneE ? Funct3E_Q : Funct3E) + // case (DivDoneE ? Funct3E_Q : Funct3E) case (Funct3E) 3'b000: PrelimResultE = ProdE[`XLEN-1:0]; 3'b001: PrelimResultE = ProdE[`XLEN*2-1:`XLEN];