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csr cleanup
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e4f4b31896
commit
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@ -209,13 +209,6 @@ module csr #(parameter
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_FS, .BigEndianM);
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.STATUS_FS, .BigEndianM);
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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@ -236,6 +229,18 @@ module csr #(parameter
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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.IllegalCSRUAccessM);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1; // counters aren't enabled
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end
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// merge CSR Reads
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// merge CSR Reads
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assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM;
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assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM;
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@ -61,7 +61,6 @@ module csrc #(parameter
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output logic IllegalCSRCAccessM
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output logic IllegalCSRCAccessM
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);
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);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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logic [4:0] CounterNumM;
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logic [4:0] CounterNumM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
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(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
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@ -156,10 +155,6 @@ module csrc #(parameter
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CSRCReadValM = 0;
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // no privileges for this csr
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IllegalCSRCAccessM = 1; // no privileges for this csr
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end
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end
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1; // counters aren't enabled
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end
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endmodule
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endmodule
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// To Do:
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// To Do:
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