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Update ram_ahb.sv

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Program clean up
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Harshini Srinath 2023-06-15 10:10:38 -07:00 committed by GitHub
parent a9495e8595
commit 97917c2a44
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1 changed files with 19 additions and 21 deletions
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src/uncore/ram_ahb.sv
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@ -30,33 +30,33 @@
module ram_ahb import cvw::*; #(parameter cvw_t P, module ram_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535) ( parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSELRam, input logic HSELRam,
input logic [P.PA_BITS-1:0] HADDR, input logic [P.PA_BITS-1:0] HADDR,
input logic HWRITE, input logic HWRITE,
input logic HREADY, input logic HREADY,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
input logic [P.XLEN-1:0] HWDATA, input logic [P.XLEN-1:0] HWDATA,
input logic [P.XLEN/8-1:0] HWSTRB, input logic [P.XLEN/8-1:0] HWSTRB,
output logic [P.XLEN-1:0] HREADRam, output logic [P.XLEN-1:0] HREADRam,
output logic HRESPRam, HREADYRam output logic HRESPRam, HREADYRam
); );
localparam ADDR_WIDTH = $clog2(RANGE/8); localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(P.XLEN/8); localparam OFFSET = $clog2(P.XLEN/8);
logic [P.XLEN/8-1:0] ByteMask; logic [P.XLEN/8-1:0] ByteMask;
logic [P.PA_BITS-1:0] HADDRD, RamAddr; logic [P.PA_BITS-1:0] HADDRD, RamAddr;
logic initTrans; logic initTrans;
logic memwrite, memwriteD, memread; logic memwrite, memwriteD, memread;
logic nextHREADYRam; logic nextHREADYRam;
logic DelayReady; logic DelayReady;
// a new AHB transactions starts when HTRANS requests a transaction, // a new AHB transactions starts when HTRANS requests a transaction,
// the peripheral is selected, and the previous transaction is completing // the peripheral is selected, and the previous transaction is completing
assign initTrans = HREADY & HSELRam & HTRANS[1] ; assign initTrans = HREADY & HSELRam & HTRANS[1] ;
assign memwrite = initTrans & HWRITE; assign memwrite = initTrans & HWRITE;
assign memread = initTrans & ~HWRITE; assign memread = initTrans & ~HWRITE;
flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD);
flopenr #(P.PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD); flopenr #(P.PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
@ -74,7 +74,6 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1),
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
// use this to add arbitrary latency to ram. Helps test AHB controller correctness // use this to add arbitrary latency to ram. Helps test AHB controller correctness
if(`RAM_LATENCY > 0) begin if(`RAM_LATENCY > 0) begin
logic [7:0] NextCycle, Cycle; logic [7:0] NextCycle, Cycle;
@ -89,15 +88,15 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
if (~HRESETn) CurrState <= #1 READY; if (~HRESETn) CurrState <= #1 READY;
else CurrState <= #1 NextState; else CurrState <= #1 NextState;
always_comb begin always_comb begin
case(CurrState) case(CurrState)
READY: if(initTrans & ~CycleFlag) NextState = DELAY; READY: if(initTrans & ~CycleFlag) NextState = DELAY;
else NextState = READY; else NextState = READY;
DELAY: if(CycleFlag) NextState = READY; DELAY: if(CycleFlag) NextState = READY;
else NextState = DELAY; else NextState = DELAY;
default: NextState = READY; default: NextState = READY;
endcase endcase
end end
@ -110,4 +109,3 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
end end
endmodule endmodule