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HPTW: factored out PageTableENtry

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This commit is contained in:
David Harris 2021-07-17 04:40:01 -04:00
parent f168bd6749
commit 9775294a6f
1 changed files with 10 additions and 8 deletions
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18
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -91,7 +91,7 @@ module pagetablewalker
logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE; logic ValidPTE, ADPageFault, MegapageMisaligned, BadMegapage, LeafPTE;
// Outputs of walker // Outputs of walker
logic [`XLEN-1:0] PageTableEntry; //logic [`XLEN-1:0] PageTableEntry;
logic StartWalk; logic StartWalk;
logic EndWalk; logic EndWalk;
@ -153,11 +153,13 @@ module pagetablewalker
assign ADPageFault = ~Accessed | (MemStore & ~Dirty); assign ADPageFault = ~Accessed | (MemStore & ~Dirty);
// Assign specific outputs to general outputs // Assign specific outputs to general outputs
assign PageTableEntryF = PageTableEntry; // *** try to eliminate this duplication, but attempts caused MMU to hang
assign PageTableEntryM = PageTableEntry; assign PageTableEntryF = CurrentPTE;
assign PageTableEntryM = CurrentPTE;
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT); assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
assign DTLBWriteM = (WalkerState == LEAF) & DTLBMissMQ;
assign DTLBWriteM = (WalkerState == LEAF) & ~DTLBMissMQ;
// *** is there a way to speed up HPTW? // *** is there a way to speed up HPTW?
@ -216,7 +218,7 @@ module pagetablewalker
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
HPTWRead = 1'b0; HPTWRead = 1'b0;
PageTableEntry = '0; //PageTableEntry = '0;
PageType = '0; PageType = '0;
DTLBWriteM = '0; DTLBWriteM = '0;
ITLBWriteF = '0; ITLBWriteF = '0;
@ -259,7 +261,7 @@ module pagetablewalker
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEAF: begin // *** pull out datapath stuff LEAF: begin // *** pull out datapath stuff
NextWalkerState = IDLE; NextWalkerState = IDLE;
PageTableEntry = CurrentPTE; //PageTableEntry = CurrentPTE;
PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
DTLBWriteM = DTLBMissMQ; DTLBWriteM = DTLBMissMQ;
ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions
@ -301,7 +303,7 @@ module pagetablewalker
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
HPTWRead = 1'b0; HPTWRead = 1'b0;
PageTableEntry = '0; //PageTableEntry = '0;
PageType = '0; PageType = '0;
DTLBWriteM = '0; DTLBWriteM = '0;
ITLBWriteF = '0; ITLBWriteF = '0;
@ -365,7 +367,7 @@ module pagetablewalker
if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF; if (ValidPTE && LeafPTE && ~ADPageFault) NextWalkerState = LEAF;
else NextWalkerState = FAULT; else NextWalkerState = FAULT;
LEAF: begin LEAF: begin
PageTableEntry = CurrentPTE; //PageTableEntry = CurrentPTE;
PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux? PageType = (PreviousWalkerState == LEVEL3) ? 2'b11 : // *** not sure about this mux?
((PreviousWalkerState == LEVEL2) ? 2'b10 : ((PreviousWalkerState == LEVEL2) ? 2'b10 :
((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00)); ((PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00));