From 97593e8a6f4d81026ee7a6ba2fa72c67d7fd130d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 17:55:45 -0600 Subject: [PATCH] Moved privileged pc logic into privileged unit. --- pipelined/src/ifu/ifu.sv | 14 +++++--------- pipelined/src/privileged/csr.sv | 10 ++++++++-- pipelined/src/privileged/privileged.sv | 8 ++++---- pipelined/src/wally/wallypipelinedcore.sv | 12 ++++++------ 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 7f1f10f35..913abf710 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -54,7 +54,8 @@ module ifu ( // Mem input logic RetM, TrapM, output logic CommittedF, - input logic [`XLEN-1:0] PrivilegedNextPCM, + input logic [`XLEN-1:0] UnalignedPCNextF, + output logic [`XLEN-1:0] PCNext2F, input logic CSRWriteFenceM, input logic InvalidateICacheM, output logic [31:0] InstrD, InstrM, @@ -85,7 +86,7 @@ module ifu ( output logic ICacheAccess, output logic ICacheMiss ); - (* mark_debug = "true" *) logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; + (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; logic BranchMisalignedFaultE; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; @@ -116,7 +117,7 @@ module ifu ( logic GatedStallF; (* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // branch predictor signal - logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; + logic [`XLEN-1:0] PCNext1F, PCNext0F; logic BusCommittedF, CacheCommittedF; logic SelIROM; @@ -289,12 +290,7 @@ module ifu ( mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); else assign PCNext2F = PCNext1F; - if(`ZICSR_SUPPORTED) begin - logic PrivilegedChangePCM; - assign PrivilegedChangePCM = RetM | TrapM; - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), - .y(UnalignedPCNextF)); - end else assign UnalignedPCNextF = PCNext2F; + assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index d12bd1004..fc9a9f683 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -40,7 +40,7 @@ module csr #(parameter input logic FlushE, FlushM, FlushW, input logic StallE, StallM, StallW, input logic [31:0] InstrM, - input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, + input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F, input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, @@ -70,7 +70,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM, + output logic [`XLEN-1:0] CSRReadValW, UnalignedPCNextF, output logic IllegalCSRAccessM, BigEndianM ); @@ -100,6 +100,8 @@ module csr #(parameter logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; + logic [`XLEN-1:0] PrivilegedNextPCM; + logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -149,6 +151,10 @@ module csr #(parameter else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; + logic PrivilegedChangePCM; + assign PrivilegedChangePCM = mretM | sretM | TrapM; + mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + /////////////////////////////////////////// // CSRWriteValM /////////////////////////////////////////// diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 74e0c8ac6..ef805a8a9 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -33,10 +33,10 @@ module privileged ( input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, input logic [`XLEN-1:0] SrcAM, - input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] PCM, PCNext2F, input logic [31:0] InstrM, output logic [`XLEN-1:0] CSRReadValW, - output logic [`XLEN-1:0] PrivilegedNextPCM, + output logic [`XLEN-1:0] UnalignedPCNextF, output logic RetM, TrapM, output logic sfencevmaM, input logic InstrValidM, CommittedM, CommittedF, @@ -122,7 +122,7 @@ module privileged ( csr csr(.clk, .reset, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, .IEUAdrM, + .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, @@ -142,7 +142,7 @@ module privileged ( .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, - .CSRReadValW,.PrivilegedNextPCM, + .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM); privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index ef6cdc1e3..f33d0f4a9 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -69,7 +69,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] PrivilegedNextPCM; + logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; (* mark_debug = "true" *) logic [1:0] MemRWM; (* mark_debug = "true" *) logic InstrValidM; logic InstrMisalignedFaultM; @@ -173,7 +173,7 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .FlushW, // Fetch - .HRDATA, .PCF, .IFUHADDR, + .HRDATA, .PCF, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, @@ -183,7 +183,7 @@ module wallypipelinedcore ( .BPPredWrongE, // Mem - .RetM, .TrapM, .CommittedF, .PrivilegedNextPCM, .InvalidateICacheM, .CSRWriteFenceM, + .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, @@ -334,8 +334,8 @@ module wallypipelinedcore ( .clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, - .CSRReadM, .CSRWriteM, .SrcAM, .PCM, - .InstrM, .CSRReadValW, .PrivilegedNextPCM, + .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, + .InstrM, .CSRReadValW, .UnalignedPCNextF, .RetM, .TrapM, .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, @@ -362,7 +362,7 @@ module wallypipelinedcore ( ); end else begin assign CSRReadValW = 0; - assign PrivilegedNextPCM = 0; + assign UnalignedPCNextF = PCNext2F; assign RetM = 0; assign TrapM = 0; assign wfiM = 0;