From a899be7deb9ff9238629b580443bcf0af466f155 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Aug 2023 17:51:51 -0500 Subject: [PATCH 1/6] Fixed bug with the cbo.inval clearing already cleared lines. --- src/cache/cachefsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 5be35a1a8..8f0e7aa2d 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -156,7 +156,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE | (CurrState == STATE_READY & CMOp[3]); // *** RT: NOT completely right has to be a hit - assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) | + assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) | (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck)); // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | From e8bc3396380cf9f909ab8ab840e86c91a3fb3c92 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Aug 2023 09:28:53 -0500 Subject: [PATCH 2/6] Oups there was a bug in the SATP fix. RV32GC was broken by the changes. --- src/privileged/csrs.sv | 4 ++-- testbench/testbench-linux.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index ff4d551a0..fbe40c13c 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -88,8 +88,8 @@ module csrs import cvw::*; #(parameter cvw_t P) ( assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)); assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)); assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)); - // assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM); - assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & (CSRWriteValM[63:60] != 4'hA); + if(P.XLEN == 64) assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & (CSRWriteValM[63:60] != 4'hA); + else assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM); assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN); assign WriteSENVCFGM = CSRSWriteM & (CSRAdrM == SENVCFG); assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE; diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index af6a123db..683f55952 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -153,7 +153,7 @@ module testbench; `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q `define MTVEC `CSR_BASE.csrm.MTVECreg.q `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q - `define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q + `define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW From 3adaaf47514c69248673f630ea0c2896229339ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 24 Aug 2023 04:54:09 -0700 Subject: [PATCH 3/6] Some fixes for synthesis scripts after parameterization --- synthDC/Makefile | 32 ++++++++++++++++---------------- synthDC/scripts/synth.tcl | 6 ++++-- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 5a723d4c3..6fd185ffd 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -55,11 +55,11 @@ $(CONFIG): # adjust DTIM and IROM to reasonable values depending on config ifneq ($(filter $(CONFIG), $(DIRS32)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 34\'h01FF/g" $(CONFIGDIR)/config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/config.vh + sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh else ifneq ($(filter $(CONFIG), $(DIRS64)),) - sed -i "s/DTIM_RANGE.*/DTIM_RANGE 56\'h01FF/g" $(CONFIGDIR)/config.vh - sed -i "s/IROM_RANGE.*/IROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/config.vh + sed -i "s/DTIM_RANGE.*/DTIM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh + sed -i "s/IROM_RANGE.*/IROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh else $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64)) @echo "Config not in list, RAM_RANGE will be unmodified" @@ -67,18 +67,18 @@ endif # if USESRAM = 1, set that in the config file, otherwise reduce sizes ifeq ($(USESRAM), 1) - sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/config.vh + sed -i 's/USE_SRAM.*/USE_SRAM = 1;/g' $(CONFIGDIR)/config.vh else - sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/config.vh - sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/config.vh - sed -i 's/BTB_SIZE.*/BTB_SIZE 5/g' $(CONFIGDIR)/config.vh + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES = 512;/g' $(CONFIGDIR)/config.vh + sed -i 's/NUMWAYS.*/NUMWAYS = 1;/g' $(CONFIGDIR)/config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE = 5;/g' $(CONFIGDIR)/config.vh + sed -i 's/BTB_SIZE.*/BTB_SIZE = 5;/g' $(CONFIGDIR)/config.vh ifneq ($(filter $(CONFIG), $(DIRS32)),) - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 34\'h01FF/g" $(CONFIGDIR)/config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh else ifneq ($(filter $(CONFIG), $(DIRS64)),) - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE 56\'h01FF/g" $(CONFIGDIR)/config.vh - sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/config.vh + sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh + sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh endif endif @@ -94,10 +94,10 @@ endif ifneq ($(MOD), orig) # PMP 0 - sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh ifneq ($(MOD), PMP0) # no priv - sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/config.vh + sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh ifneq ($(MOD), noPriv) # turn off FPU sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/config.vh @@ -128,7 +128,7 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkdirecs configs rundc clean +synth: mkdirecs configs rundc # clean rundc: ifeq ($(TECH), tsmc28psyn) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index a7ae6ef09..7a8c2e7bf 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -25,7 +25,9 @@ set maxopt $::env(MAXOPT) set drive $::env(DRIVE) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} -eval file copy -force [glob ${hdl_src}/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} @@ -74,7 +76,7 @@ if { [shell_is_in_topographical_mode] } { #set alib_library_analysis_path ./$outputDir define_design_lib WORK -path ./$outputDir/WORK analyze -f sverilog -lib WORK $my_verilog_files -elaborate $my_toplevel -lib WORK +elaborate $my_toplevel -parameter P -lib WORK # Set the current_design current_design $my_toplevel From aad722ffb131cc16acd9af895dcab3195eaadb0f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 24 Aug 2023 05:18:04 -0700 Subject: [PATCH 4/6] Check for legal SATP mode values --- src/privileged/csrs.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index fbe40c13c..95599e3a0 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -88,8 +88,12 @@ module csrs import cvw::*; #(parameter cvw_t P) ( assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)); assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)); assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)); - if(P.XLEN == 64) assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & (CSRWriteValM[63:60] != 4'hA); - else assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM); + if(P.XLEN == 64) begin + logic LegalSatpModeM; + assign LegalSatpModeM = P.VIRTMEM_SUPPORTED & (CSRWriteValM[63:60] == 0 | CSRWriteValM[63:60] == 8 | CSRWriteValM[63:60] == 9); // supports SV39 and 48 + assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & LegalSatpModeM; + end else // RV32 + assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & P.VIRTMEM_SUPPORTED; assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN); assign WriteSENVCFGM = CSRSWriteM & (CSRAdrM == SENVCFG); assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE; From 8fb09b8f0cdb61beee0e544686e00bfbd7ef0c6b Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 24 Aug 2023 05:21:15 -0700 Subject: [PATCH 5/6] ??? on synthesis Makefile --- synthDC/Makefile | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index ea3cdda47..64dd497a7 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -69,26 +69,15 @@ endif ifeq ($(USESRAM), 1) sed -i 's/USE_SRAM.*/USE_SRAM = 1;/g' $(CONFIGDIR)/config.vh else -<<<<<<< HEAD - sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES = 512;/g' $(CONFIGDIR)/config.vh - sed -i 's/NUMWAYS.*/NUMWAYS = 1;/g' $(CONFIGDIR)/config.vh - sed -i 's/BPRED_SIZE.*/BPRED_SIZE = 5;/g' $(CONFIGDIR)/config.vh - sed -i 's/BTB_SIZE.*/BTB_SIZE = 5;/g' $(CONFIGDIR)/config.vh -======= sed -i "s/WAYSIZEINBYTES.*/WAYSIZEINBYTES = 32\'d512;/g" $(CONFIGDIR)/config.vh sed -i "s/NUMWAYS.*/NUMWAYS =32\'d1;/g" $(CONFIGDIR)/config.vh sed -i "s/BPRED_SIZE.*/BPRED_SIZE =32\'d5;/g" $(CONFIGDIR)/config.vh sed -i "s/BTB_SIZE.*/BTB_SIZE = 32\'d5;/g" $(CONFIGDIR)/config.vh ->>>>>>> dcef4cc9cee704ec78c6c5118bb769405cedc499 ifneq ($(filter $(CONFIG), $(DIRS32)),) sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 34\'h01FF;/g" $(CONFIGDIR)/config.vh else ifneq ($(filter $(CONFIG), $(DIRS64)),) -<<<<<<< HEAD - sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh -======= sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh ->>>>>>> dcef4cc9cee704ec78c6c5118bb769405cedc499 sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 56\'h01FF;/g" $(CONFIGDIR)/config.vh endif endif From 92302331b735e563b2a281d84a201262a0a36d98 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 24 Aug 2023 09:04:41 -0500 Subject: [PATCH 6/6] Oups forgot to include the 32-bit cbom test in previous commit. --- .../references/WALLY-cbom-01.reference_output | 428 ++++++++++++++++ .../rv32i_m/privilege/src/WALLY-cbom-01.S | 472 ++++++++++++++++++ 2 files changed, 900 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output new file mode 100644 index 000000000..faf3bf658 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output @@ -0,0 +1,428 @@ +deadbeef # begin_signature +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef # destination 1 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +00000000 # destination 2 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000018 +00000019 +0000001a +0000001b +0000001c +0000001d +0000001e +0000001f +00000020 +00000021 +00000022 +00000023 +00000024 +00000025 +00000026 +00000027 +00000028 +00000029 +0000002a +0000002b +0000002c +0000002d +0000002e +0000002f +00000030 +00000031 +00000032 +00000033 +00000034 +00000035 +00000036 +00000037 +00000038 +00000039 +0000003a +0000003b +0000003c +0000003d +0000003e +0000003f +00000040 +00000041 +00000042 +00000043 +00000044 +00000045 +00000046 +00000047 +00000048 +00000049 +0000004a +0000004b +0000004c +0000004d +0000004e +0000004f +00000050 +00000051 +00000052 +00000053 +00000054 +00000055 +00000056 +00000057 +00000058 +00000059 +0000005a +0000005b +0000005c +0000005d +0000005e +0000005f +00000060 +00000061 +00000062 +00000063 +00000064 +00000065 +00000066 +00000067 +00000068 +00000069 +0000006a +0000006b +0000006c +0000006d +0000006e +0000006f +00000070 +00000071 +00000072 +00000073 +00000074 +00000075 +00000076 +00000077 +00000078 +00000079 +0000007a +0000007b +0000007c +0000007d +0000007e +0000007f +00000000 # destination 3 +00000001 +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000018 +00000019 +0000001a +0000001b +0000001c +0000001d +0000001e +0000001f +00000020 +00000021 +00000022 +00000023 +00000024 +00000025 +00000026 +00000027 +00000028 +00000029 +0000002a +0000002b +0000002c +0000002d +0000002e +0000002f +00000030 +00000031 +00000032 +00000033 +00000034 +00000035 +00000036 +00000037 +00000038 +00000039 +0000003a +0000003b +0000003c +0000003d +0000003e +0000003f +00000040 +00000041 +00000042 +00000043 +00000044 +00000045 +00000046 +00000047 +00000048 +00000049 +0000004a +0000004b +0000004c +0000004d +0000004e +0000004f +00000050 +00000051 +00000052 +00000053 +00000054 +00000055 +00000056 +00000057 +00000058 +00000059 +0000005a +0000005b +0000005c +0000005d +0000005e +0000005f +00000060 +00000061 +00000062 +00000063 +00000064 +00000065 +00000066 +00000067 +00000068 +00000069 +0000006a +0000006b +0000006c +0000006d +0000006e +0000006f +00000070 +00000071 +00000072 +00000073 +00000074 +00000075 +00000076 +00000077 +00000078 +00000079 +0000007a +0000007b +0000007c +0000007d +0000007e +0000007f +ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies. +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +0bad0bad # controls +0bad0bad +0bad0bad diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S new file mode 100644 index 000000000..3c129b998 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S @@ -0,0 +1,472 @@ +/////////////////////////////////////////// +// +// WALLY-cache-management-tests +// invalidate, clean, and flush +// +// Author: Rose Thompson +// +// Created 18 August 2023 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline +# granularity blocks of memory. Invalidate: Clears valid and dirty bits +# and does not write back. Clean: Writes back dirty cacheline if needed +# and clears dirty bit. Does NOT clear valid bit. Flush: Cleans and then +# Invalidates. These operations apply to all caches in the memory system. +# The tests are divided into three parts one for the data cache, instruction cache +# and checks to verify the uncached regions of memory cause exceptions. +# ----------- +# Copyright (c) 2020. RISC-V International. All rights reserved. +# SPDX-License-Identifier: BSD-3-Clause +# ----------- +# +# This assembly file tests the cbo.inval, cbo.clean, and cbo.flush instructions of the RISC-V Zicbom extension. +# + +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I_Zicbom") +# Test code region +.section .text.init +.globl rvtest_entry_point + +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.inval) + +RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n") + +CBOMTest: + # *** TODO + # first need to discover the length of the cacheline. + # for now assume it is 64 bytes + + #addi sp, sp, -16 + #sd s0, 0(sp) + #sd ra, 8(sp) + + la s0, signature + + ################################################################################ + # INVALIDATE D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_inval_step1: + la a0, SourceData + la a1, Destination1 + li a2, 128 + jal ra, memcpy4 + + # step 2 +CBOMTest_inval_step2: + la a0, SourceData + la a1, Destination1 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 3 +CBOMTest_inval_step3: + la a1, Destination1 + cbo.inval (a1) + # step 4 (should be Invalid) + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 16 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 4 next line (should still be valid) +CBOMTest_inval_step4: + la a0, SourceData+64 + la a1, Destination1+64 + li a2, 16 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 3 (Invalidate all remaining lines) +CBOMTest_inval_step3_all: + la a1, Destination1+64 + cbo.inval (a1) + cbo.inval (a1) # verify invalidating an already non present line does not cause an issue. + la a1, Destination1+128 + cbo.inval (a1) + la a1, Destination1+192 + cbo.inval (a1) + la a1, Destination1+256 + cbo.inval (a1) + la a1, Destination1+320 + cbo.inval (a1) + la a1, Destination1+384 + cbo.inval (a1) + la a1, Destination1+448 + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_inval_step4_all: + la a0, DeadBeafData1 + la a1, Destination1 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + ################################################################################ + # Clean D$ + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. Invalidate the second region + # 4. Verify the second region has the original invalid data + # 5. Repeat step 1 + # 6. Clean cachelines + # 7. Verify the second region has the same data + # 8. Invalidate the second region + # 9. Verify again but this time it should contain the same data + # DON'T batch each step. We want to see the transition between cachelines. The current should be invalidated + # but the next should have the copied data. + + # step 1 +CBOMTest_clean_step1: + la a0, SourceData + la a1, Destination2 + li a2, 128 + jal ra, memcpy4 + + # step 2 +CBOMTest_clean_step2: + la a0, SourceData + la a1, Destination2 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 3 +CBOMTest_clean_step3: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + cbo.inval (a1) + + # step 4 All should be invalid +CBOMTest_clean_step4: + la a0, DeadBeafData1 + la a1, Destination2 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 5 +CBOMTest_clean_step5: + la a0, SourceData + la a1, Destination2 + li a2, 128 + jal ra, memcpy4 + + # step 6 only clean 1 line +CBOMTest_clean_step6: + la a1, Destination2 + cbo.clean (a1) + + # step 7 only check that 1 line +CBOMTest_clean_step7: + la a0, SourceData + la a1, Destination2 + li a2, 16 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 8 invalidate that 1 line and the next +CBOMTest_clean_step8: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + + # step 9 that 1 line should contain the valid data +CBOMTest_clean_step9_line1: + la a0, SourceData + la a1, Destination2 + li a2, 16 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 9 the next should contain the invalid data +CBOMTest_clean_step9_line2: + la a0, DeadBeafData1 + la a1, Destination2+64 + li a2, 16 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 5 # now recopy the one we just corrupted +CBOMTest_clean_step5_recopy_line2: + la a0, SourceData+64 + la a1, Destination2+64 + li a2, 16 + jal ra, memcpy4 + + # step 6 # clean the remaining +CBOMTest_clean_step6_clean_all: + la a1, Destination2+64 + cbo.clean (a1) + la a1, Destination2+128 + cbo.clean (a1) + la a1, Destination2+192 + cbo.clean (a1) + la a1, Destination2+256 + cbo.clean (a1) + la a1, Destination2+320 + cbo.clean (a1) + la a1, Destination2+384 + cbo.clean (a1) + la a1, Destination2+448 + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + cbo.clean (a1) + + # step 8 # invalidate all remaining +CBOMTest_clean_step7_invalidate_all: + la a1, Destination2 + cbo.inval (a1) + la a1, Destination2+64 + cbo.inval (a1) + la a1, Destination2+128 + cbo.inval (a1) + la a1, Destination2+192 + cbo.inval (a1) + la a1, Destination2+256 + cbo.inval (a1) + la a1, Destination2+320 + cbo.inval (a1) + la a1, Destination2+384 + cbo.inval (a1) + la a1, Destination2+448 + cbo.inval (a1) + + # step 9 # check all +CBOMTest_clean_step9_check_all: + la a0, SourceData + la a1, Destination2 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + ################################################################################ + # Flush D$ line + ################################################################################ + + # theory of operation + # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory + # 2. Then verify the second region has the same data + # 3. For flush there is no way to create a negative control. We will flush 1 cache line + # 4. Verify whole region + # 5. Flush the remaining lines + # 6. Verify whole region + + # step 1 +CBOMTest_flush_step1: + la a0, SourceData + la a1, Destination3 + li a2, 128 + jal ra, memcpy4 + + # step 2 All should be valid +CBOMTest_flush_step2_verify: + la a0, SourceData + la a1, Destination3 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 3 # flush 1 line +CBOMTest_flush_step3: + la a1, Destination3 + cbo.flush (a1) + + # step 4 +CBOMTest_flush_step4_verify: + la a0, SourceData + la a1, Destination3 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + # step 5 +CBOMTest_flush_step5_flush_all: + la a1, Destination3 + cbo.flush (a1) + la a1, Destination3+64 + cbo.flush (a1) + la a1, Destination3+128 + cbo.flush (a1) + la a1, Destination3+192 + cbo.flush (a1) + la a1, Destination3+256 + cbo.flush (a1) + la a1, Destination3+320 + cbo.flush (a1) + la a1, Destination3+384 + cbo.flush (a1) + la a1, Destination3+448 + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + cbo.flush (a1) + + # step 6 +CBOMTest_flush_step6_verify: + la a0, SourceData + la a1, Destination3 + li a2, 128 + jal ra, memcmp4 + sw a0, 0(s0) # should be -1 + addi s0, s0, 4 + + + #lw s0, 0(sp) + #lw ra, 8(sp) + #addi sp, sp, 16 + #ret +RVMODEL_HALT + + +.type memcpy4, @function +memcpy4: + # a0 is the source + # a1 is the dst + # a2 is the number of 4 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcpy4_loop: + lw t3, 0(t0) + sw t3, 0(t1) + addi t0, t0, 4 + addi t1, t1, 4 + addi t2, t2, 1 + blt t2, a2, memcpy4_loop + ret + +.type memcmp4, @function +# returns which index mismatch, -1 if none +memcmp4: + # a0 is the source1 + # a1 is the source2 + # a2 is the number of 4 byte words + mv t0, a0 + mv t1, a1 + li t2, 0 +memcmp4_loop: + lw t3, 0(t0) + lw t4, 0(t1) + bne t3, t4, memcmp4_ne + addi t0, t0, 4 + addi t1, t1, 4 + addi t2, t2, 1 + blt t2, a2, memcmp4_loop + li a0, -1 + ret +memcmp4_ne: + mv a0, t2 + ret + +RVTEST_CODE_END + + +RVTEST_DATA_BEGIN +# Input data section. +#.data +.align 7 + +DeadBeafData1: + .fill 128, 4, 0xdeadbeef +SourceData: + .int 0, 1, 2, 3, 4, 5, 6, 7 + .int 8, 9, 10, 11, 12, 13, 14, 15 + .int 16, 17, 18, 19, 20, 21, 22, 23 + .int 24, 25, 26, 27, 28, 29, 30, 31 + .int 32, 33, 34, 35, 36, 37, 38, 39 + .int 40, 41, 42, 43, 44, 45, 46, 47 + .int 48, 49, 50, 51, 52, 53, 54, 55 + .int 56, 57, 58, 59, 60, 61, 62, 63 + .int 64, 65, 66, 67, 68, 69, 70, 71 + .int 72, 73, 74, 75, 76, 77, 78, 79 + .int 80, 81, 82, 83, 84, 85, 86, 87 + .int 88, 89, 90, 91, 92, 93, 94, 95 + .int 96, 97, 98, 99, 100, 101, 102, 103 + .int 104, 105, 106, 107, 108, 109, 110, 111 + .int 112, 113, 114, 115, 116, 117, 118, 119 + .int 120, 121, 122, 123, 124, 125, 126, 127 + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + .fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert + # 4 bytes. This needs to be aligned to a cacheline + + .align 6 +Destination1: + .fill 128, 4, 0xdeadbeef +Destination2: + .fill 128, 4, 0xdeadbeef +Destination3: + .fill 128, 4, 0xdeadbeef +signature: + .fill 16, 4, 0x0bad0bad + +RVMODEL_DATA_END +