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Moved X-1 to preproc

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cturek 2022-09-14 17:26:56 +00:00
parent 0f5b38a6f0
commit 9757d8ce3e
3 changed files with 5 additions and 5 deletions
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2
pipelined/src/fpu/fdivsqrt.sv
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@ -56,7 +56,7 @@ module fdivsqrt(
logic [`DIVb+3:0] NextWSN, NextWCN; logic [`DIVb+3:0] NextWSN, NextWCN;
logic [`DIVb+3:0] WS, WC; logic [`DIVb+3:0] WS, WC;
logic [`DIVb+3:0] StickyWSA; logic [`DIVb+3:0] StickyWSA;
logic [`DIVb:0] X; logic [`DIVb+3:0] X;
logic [`DIVN-2:0] D; // U0.N-1 logic [`DIVN-2:0] D; // U0.N-1
logic [`DIVN-2:0] Dpreproc; logic [`DIVN-2:0] Dpreproc;
logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM; logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;

4
pipelined/src/fpu/fdivsqrtiter.sv
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@ -38,7 +38,7 @@ module fdivsqrtiter(
input logic XZeroE, YZeroE, input logic XZeroE, YZeroE,
input logic SqrtE, input logic SqrtE,
input logic SqrtM, input logic SqrtM,
input logic [`DIVb:0] X, input logic [`DIVb+3:0] X,
input logic [`DIVN-2:0] Dpreproc, input logic [`DIVN-2:0] Dpreproc,
output logic [`DIVN-2:0] D, // U0.N-1 output logic [`DIVN-2:0] D, // U0.N-1
output logic [`DIVb+3:0] NextWSN, NextWCN, output logic [`DIVb+3:0] NextWSN, NextWCN,
@ -106,7 +106,7 @@ module fdivsqrtiter(
assign initC = 0; assign initC = 0;
// mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN); // mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
mux2 #(`DIVb+4) wsmux(NextWSN, {{3{SqrtE}}, X}, DivStart, WSN); mux2 #(`DIVb+4) wsmux(NextWSN, X, DivStart, WSN);
flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]); flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN); mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]); flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);

4
pipelined/src/fpu/fdivsqrtpreproc.sv
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@ -39,7 +39,7 @@ module fdivsqrtpreproc (
input logic Sqrt, input logic Sqrt,
input logic XZero, input logic XZero,
output logic [`NE+1:0] QeM, output logic [`NE+1:0] QeM,
output logic [`DIVb:0] X, output logic [`DIVb+3:0] X,
output logic [`DIVN-2:0] Dpreproc output logic [`DIVN-2:0] Dpreproc
); );
// logic [`XLEN-1:0] PosA, PosB; // logic [`XLEN-1:0] PosA, PosB;
@ -70,7 +70,7 @@ module fdivsqrtpreproc (
assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0}; assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}}; assign X = Sqrt ? {3'b111, SqrtX, {`DIVb-1-`NF{1'b0}}} : {3'b000, ~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}}; assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
// radix 2 radix 4 // radix 2 radix 4