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Clarified interlockfsm.

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Ross Thompson 2022-02-22 11:31:28 -06:00
parent 1ab2e7590b
commit 971dd494f6
2 changed files with 50 additions and 40 deletions
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87
pipelined/src/lsu/interlockfsm.sv
View File

@ -31,33 +31,44 @@
`include "wally-config.vh" `include "wally-config.vh"
module interlockfsm module interlockfsm(
(input logic clk, input logic clk,
input logic reset, input logic reset,
input logic AnyCPUReqM, input logic [1:0] MemRWM,
input logic ITLBMissOrDAFaultF, input logic [1:0] AtomicM,
input logic ITLBWriteF, input logic ITLBMissOrDAFaultF,
input logic DTLBMissOrDAFaultM, input logic ITLBWriteF,
input logic DTLBWriteM, input logic DTLBMissOrDAFaultM,
input logic TrapM, input logic DTLBWriteM,
input logic DCacheStallM, input logic TrapM,
input logic DCacheStallM,
output logic InterlockStall, output logic InterlockStall,
output logic SelReplayCPURequest, output logic SelReplayCPURequest,
output logic SelHPTW, output logic SelHPTW,
output logic IgnoreRequestTLB, output logic IgnoreRequestTLB,
output logic IgnoreRequestTrapM); output logic IgnoreRequestTrapM);
logic ToITLBMiss;
logic ToITLBMissNoReplay;
logic ToDTLBMiss;
logic ToBoth;
logic AnyCPUReqM;
typedef enum logic[2:0] {STATE_T0_READY, typedef enum logic[2:0] {STATE_T0_READY,
STATE_T0_REPLAY, STATE_T0_REPLAY,
STATE_T3_DTLB_MISS, STATE_T3_DTLB_MISS,
STATE_T4_ITLB_MISS, STATE_T4_ITLB_MISS,
STATE_T5_ITLB_MISS, STATE_T5_ITLB_MISS,
STATE_T7_DITLB_MISS} statetype; STATE_T7_DITLB_MISS} statetype;
(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState; (* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ToITLBMiss = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM;
assign ToITLBMissNoReplay = ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM;
assign ToDTLBMiss = ~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
assign ToBoth = ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM;
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) InterlockCurrState <= #1 STATE_T0_READY; if (reset) InterlockCurrState <= #1 STATE_T0_READY;
@ -65,23 +76,23 @@ module interlockfsm
always_comb begin always_comb begin
case(InterlockCurrState) case(InterlockCurrState)
STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY; STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY;
else if(~ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS; else if(ToDTLBMiss) InterlockNextState = STATE_T3_DTLB_MISS;
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS; else if(ToITLBMissNoReplay) InterlockNextState = STATE_T4_ITLB_MISS;
else if(ITLBMissOrDAFaultF & ~DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS; else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ITLBMissOrDAFaultF & DTLBMissOrDAFaultM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS; else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
else InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T0_READY;
STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY; STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T0_READY;
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY; STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T3_DTLB_MISS; else InterlockNextState = STATE_T3_DTLB_MISS;
STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY; STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
else InterlockNextState = STATE_T4_ITLB_MISS; else InterlockNextState = STATE_T4_ITLB_MISS;
STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY; STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
else InterlockNextState = STATE_T5_ITLB_MISS; else InterlockNextState = STATE_T5_ITLB_MISS;
STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS; STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
else InterlockNextState = STATE_T7_DITLB_MISS; else InterlockNextState = STATE_T7_DITLB_MISS;
default: InterlockNextState = STATE_T0_READY; default: InterlockNextState = STATE_T0_READY;
endcase endcase
end // always_comb end // always_comb

3
pipelined/src/lsu/lsuvirtmen.sv
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@ -78,13 +78,12 @@ module lsuvirtmem(
logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF; logic ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM; logic DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF); assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM); assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);
assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM; assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;
assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM; assign DTLBMissOrDAFaultNoTrapM = DTLBMissOrDAFaultM & ~TrapM;
interlockfsm interlockfsm ( interlockfsm interlockfsm (
.clk, .reset, .AnyCPUReqM, .ITLBMissOrDAFaultF, .ITLBWriteF, .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
.DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
.InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); .InterlockStall, .SelReplayCPURequest, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM);
hptw hptw( // *** remove logic from (), mention this in style guide CH3 hptw hptw( // *** remove logic from (), mention this in style guide CH3