diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 6c19436e0..734fec9a2 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -31,37 +31,37 @@
`include "wally-config.vh"
module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, DCACHE) (
- input logic clk,
- input logic reset,
+ input logic clk,
+ input logic reset,
// cpu side
- input logic CPUBusy,
- input logic [1:0] RW,
- input logic [1:0] Atomic,
- input logic FlushCache,
- input logic InvalidateCache,
- input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
- input logic [`PA_BITS-1:0] PAdr, // physical address
+ input logic CPUBusy,
+ input logic [1:0] RW,
+ input logic [1:0] Atomic,
+ input logic FlushCache,
+ input logic InvalidateCache,
+ input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
+ input logic [`PA_BITS-1:0] PAdr, // physical address
input logic [(WORDLEN-1)/8:0] ByteMask,
- input logic [WORDLEN-1:0] FinalWriteData,
- output logic CacheCommitted,
- output logic CacheStall,
+ input logic [WORDLEN-1:0] FinalWriteData,
+ output logic CacheCommitted,
+ output logic CacheStall,
// to performance counters to cpu
- output logic CacheMiss,
- output logic CacheAccess,
+ output logic CacheMiss,
+ output logic CacheAccess,
// lsu control
- input logic IgnoreRequestTLB,
- input logic IgnoreRequestTrapM,
- input logic TrapM,
- input logic Cacheable,
+ input logic IgnoreRequestTLB,
+ input logic IgnoreRequestTrapM,
+ input logic TrapM,
+ input logic Cacheable,
// Bus fsm interface
- output logic CacheFetchLine,
- output logic CacheWriteLine,
- input logic CacheBusAck,
- input logic [LOGBWPL-1:0] WordCount,
- input logic LSUBusWriteCrit,
- output logic [`PA_BITS-1:0] CacheBusAdr,
- input logic [LINELEN-1:0] CacheBusWriteData,
- output logic [WORDLEN-1:0] ReadDataWord);
+ output logic CacheFetchLine,
+ output logic CacheWriteLine,
+ input logic CacheBusAck,
+ input logic SelLSUBusWord,
+ input logic [LOGBWPL-1:0] WordCount,
+ input logic [LINELEN-1:0] CacheBusWriteData,
+ output logic [`PA_BITS-1:0] CacheBusAdr,
+ output logic [WORDLEN-1:0] ReadDataWord);
// Cache parameters
localparam LINEBYTELEN = LINELEN/8;
@@ -147,7 +147,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// like to fix this.
if(DCACHE)
mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]),
- .d1(WordCount), .s(LSUBusWriteCrit),
+ .d1(WordCount), .s(SelLSUBusWord),
.y(WordOffsetAddr));
else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index b4b160289..18ceabfa8 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -204,7 +204,7 @@ module ifu (
busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED)
busdp(.clk, .reset,
- .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .LSUBusWriteCrit(),
+ .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(),
.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(),
@@ -230,7 +230,7 @@ module ifu (
.CacheWriteLine(), .ReadDataWord(FinalInstrRawF),
.Cacheable(CacheableF),
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
- .ByteMask('0), .WordCount('0), .LSUBusWriteCrit('0),
+ .ByteMask('0), .WordCount('0), .SelLSUBusWord('0),
.FinalWriteData('0),
.RW(2'b10),
.Atomic('0), .FlushCache('0),
diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv
index 5139efdc1..af543f0ad 100644
--- a/pipelined/src/lsu/busdp.sv
+++ b/pipelined/src/lsu/busdp.sv
@@ -64,7 +64,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
input logic [1:0] LSURWM,
input logic CPUBusy,
input logic CacheableM,
- output logic LSUBusWriteCrit,
+ output logic SelLSUBusWord,
output logic BusStall,
output logic BusCommittedM);
@@ -89,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
- .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
+ .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead,
.LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule
diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index 75c4d006b..00c561423 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -47,7 +47,7 @@ module busfsm #(parameter integer WordCountThreshold,
output logic BusStall,
output logic LSUBusWrite,
- output logic LSUBusWriteCrit,
+ output logic SelLSUBusWord,
output logic LSUBusRead,
output logic [2:0] LSUBurstType,
output logic LSUTransComplete,
@@ -166,7 +166,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE);
- assign LSUBusWriteCrit = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) |
+ assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_WRITE);
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 08d217e17..c5711ca91 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -109,7 +109,7 @@ module lsu (
logic InterlockStall;
logic IgnoreRequestTLB, IgnoreRequestTrapM;
logic BusCommittedM, DCacheCommittedM;
- logic LSUBusWriteCrit;
+ logic SelLSUBusWord;
logic DataDAPageFaultM;
logic [`XLEN-1:0] LSUWriteDataM;
logic [`XLEN-1:0] WriteDataM;
@@ -222,7 +222,7 @@ module lsu (
busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED) busdp(
.clk, .reset,
.LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
- .WordCount, .LSUBusWriteCrit,
+ .WordCount, .SelLSUBusWord,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,
.SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
@@ -240,7 +240,7 @@ module lsu (
assign FinalWriteDataM = {{`LLEN-`XLEN{1'b0}}, IEUWriteDataM};
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
- .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM),
+ .clk, .reset, .CPUBusy, .SelLSUBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.ByteMask(FinalByteMaskM), .WordCount,
.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),