The FPGA is synthesizing with the rvvi and ethernet hardware.

fpga/constraints/constraints-ArtyA7.xdc

@@ -9,6 +9,32 @@
 set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
 set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
 
+##### RVVI Ethernet ####
+# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
+set_property -dict {LOC F15  IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
+set_property -dict {LOC D18  IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
+set_property -dict {LOC E17  IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
+set_property -dict {LOC E18  IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
+set_property -dict {LOC G17  IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
+set_property -dict {LOC G16  IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
+set_property -dict {LOC C17  IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
+set_property -dict {LOC H16  IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
+set_property -dict {LOC H14  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
+set_property -dict {LOC J14  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
+set_property -dict {LOC J13  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
+set_property -dict {LOC H17  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
+set_property -dict {LOC H15  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
+set_property -dict {LOC D17  IOSTANDARD LVCMOS33} [get_ports phy_col]
+set_property -dict {LOC G14  IOSTANDARD LVCMOS33} [get_ports phy_crs]
+set_property -dict {LOC G18  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
+set_property -dict {LOC C16  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
+
+create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
+create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
+
+set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
+set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}]
+
 ##### GPI ####
 set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
 set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]

fpga/generator/xlnx_mmcm.tcl

@@ -12,10 +12,11 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
                         CONFIG.NUM_OUT_CLKS {3} \
                         CONFIG.CLKOUT2_USED {true} \
                         CONFIG.CLKOUT3_USED {true} \
-                        CONFIG.CLKOUT4_USED {false} \
+                        CONFIG.CLKOUT4_USED {true} \
                         CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
                         CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
                         CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
+                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
                         CONFIG.CLKIN1_JITTER_PS {10.0} \
                        ] [get_ips $ipName]
 

fpga/src/fpgaTopArtyA7.sv

@@ -44,6 +44,21 @@ module fpgaTop
    inout           SDCCmd,
    input           SDCCD,
 
+ /*
+     * Ethernet: 100BASE-T MII
+     */
+    output       phy_ref_clk,
+    input        phy_rx_clk,
+    input  [3:0] phy_rxd,
+    input        phy_rx_dv,
+    input        phy_rx_er,
+    input        phy_tx_clk,
+    output [3:0] phy_txd,
+    output       phy_tx_en,
+    input        phy_col, // nc
+    input        phy_crs, // nc
+    output       phy_reset_n,
+
    inout [15:0]    ddr3_dq,
    inout [1:0]     ddr3_dqs_n,
    inout [1:0]     ddr3_dqs_p,
@@ -428,7 +443,8 @@ module fpgaTop
     wire             mmcm_locked;
   wire [11:0]      device_temp;
     wire             mmcm1_locked;
-  
+
+  logic              RVVIStall;
 
   assign GPIOIN = {28'b0, GPI};
   assign GPO = GPIOOUT[4:0];
@@ -446,6 +462,7 @@ module fpgaTop
   xlnx_mmcm xln_mmcm(.clk_out1(clk167),
                      .clk_out2(clk200),
                      .clk_out3(CPUCLK),
+                     .clk_out4(phy_ref_clk),
                      .reset(1'b0),
                      .locked(mmcm1_locked),
                      .clk_in1(default_100mhz_clk));
@@ -496,7 +513,7 @@ module fpgaTop
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
                     .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIntr); 
+                    .UARTSin, .UARTSout, .SDCIntr, .RVVIStall); 
 
 
   // ahb lite to axi bridge
@@ -1098,6 +1115,47 @@ module fpgaTop
      .init_calib_complete(c0_init_calib_complete),
      .device_temp(device_temp));
   
+  localparam MAX_CSRS = 3;
+  logic                       valid;
+  logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
+
+  rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .valid, .rvvi);
+
+  // axi 4 write data channel
+  logic [31:0]                                      RvviAxiWdata;
+  logic [3:0]                                       RvviAxiWstrb;
+  logic                                             RvviAxiWlast;
+  logic                                             RvviAxiWvalid;
+  logic                                             RvviAxiWready;
+
+  logic                                             tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
+  logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
+
+    packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
+      .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
+
+    eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),
+      .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
+      .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
+      .rx_axis_tlast(), .rx_axis_tuser(),
+
+      // *** update these
+      .mii_rx_clk(phy_rx_clk),
+      .mii_rxd(phy_rxd),
+      .mii_rx_dv(phy_rx_dv),
+      .mii_rx_er(phy_rx_er),
+      .mii_tx_clk(phy_tx_clk),
+      .mii_txd(phy_txd),
+      .mii_tx_en(phy_tx_en),
+      .mii_tx_er(),
+
+      // status
+      .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
+      .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, 
+      .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
+      );
+
+  assign phy_reset_n = ~bus_struct_reset;
 
 endmodule
 

src/rvvi/rvvisynth.sv

@@ -62,64 +62,64 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
   logic [MAX_CSRS*(P.XLEN+12)-1:0]       CSRs;
      
   // get signals from the core.
-  assign StallE         = dut.core.StallE;
+  assign StallE         = fpgaTop.wallypipelinedsoc.core.StallE;
-  assign StallM         = dut.core.StallM;
+  assign StallM         = fpgaTop.wallypipelinedsoc.core.StallM;
-  assign StallW         = dut.core.StallW;
+  assign StallW         = fpgaTop.wallypipelinedsoc.core.StallW;
-  assign FlushE         = dut.core.FlushE;
+  assign FlushE         = fpgaTop.wallypipelinedsoc.core.FlushE;
-  assign FlushM         = dut.core.FlushM;
+  assign FlushM         = fpgaTop.wallypipelinedsoc.core.FlushM;
-  assign FlushW         = dut.core.FlushW;
+  assign FlushW         = fpgaTop.wallypipelinedsoc.core.FlushW;
-  assign InstrValidM    = dut.core.ieu.InstrValidM;
+  assign InstrValidM    = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
-  assign InstrRawD      = dut.core.ifu.InstrRawD;
+  assign InstrRawD      = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
-  assign PCM            = dut.core.ifu.PCM;
+  assign PCM            = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
-  assign Mcycle         = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
+  assign Mcycle         = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
-  assign Minstret       = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
+  assign Minstret       = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-  assign TrapM          = dut.core.TrapM;
+  assign TrapM          = fpgaTop.wallypipelinedsoc.core.TrapM;
-  assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
+  assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
-  assign GPRAddr        = dut.core.ieu.dp.regf.a3;
+  assign GPRAddr        = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
-  assign GPRWen         = dut.core.ieu.dp.regf.we3;
+  assign GPRWen         = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
-  assign GPRValue       = dut.core.ieu.dp.regf.wd3;
+  assign GPRValue       = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
-  assign FPRAddr        = dut.core.fpu.fpu.fregfile.a4;
+  assign FPRAddr        = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
-  assign FPRWen         = dut.core.fpu.fpu.fregfile.we4;
+  assign FPRWen         = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
-  assign FPRValue       = dut.core.fpu.fpu.fregfile.wd4;
+  assign FPRValue       = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
 
-  assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
+  assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
-  assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
+  assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
-  assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
+  assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
-  assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
+  assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
-  assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
+  assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
-  assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
+  assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
-  assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
+  assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
-  assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
+  assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
-  assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
+  assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
-  assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
+  assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
-  assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
+  assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
-  assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
+  assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
-  assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
+  assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
-  assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
+  assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
-  assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
+  assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
-  assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
+  assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
   assign CSRArray[16] = 0; // 12'hF11
   assign CSRArray[17] = 0; // 12'hF12
   assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
   assign CSRArray[19] = 0; // 12'hF15
   assign CSRArray[20] = 0; // 12'h34A
 	  // supervisor CSRs
-  assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
+  assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
-  assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
+  assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
-  assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
+  assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
-  assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
+  assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
-  assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
+  assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
-  assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
+  assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
-  assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
+  assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
-  assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
+  assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
-  assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
+  assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
-  assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
+  assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
-  assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
+  assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
-  assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
+  assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
 	  // user CSRs
-  assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
+  assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
-  assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
+  assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
-  assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
+  assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
 
   //
   assign XLENZeros = '0;