diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 3c39c0694..00e11bdb6 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -50,8 +50,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE output logic CacheAccess, // lsu control input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, - input logic TrapM, + input logic DCacheTrapM, + input logic ICacheTrapM, input logic Cacheable, // Bus fsm interface output logic CacheFetchLine, @@ -214,7 +214,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign CacheRW = Cacheable ? RW : 2'b00; assign CacheAtomic = Cacheable ? Atomic : 2'b00; cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, - .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM, + .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .DCacheTrapM, .ICacheTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index a1c785dc7..c70e92a8a 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -42,8 +42,8 @@ module cachefsm input logic CPUBusy, // interlock fsm input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, - input logic TrapM, + input logic DCacheTrapM, + input logic ICacheTrapM, // Bus inputs input logic CacheBusAck, // dcache internals @@ -98,12 +98,12 @@ module cachefsm (* mark_debug = "true" *) statetype CurrState, NextState; logic IgnoreRequest; - assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; + assign IgnoreRequest = IgnoreRequestTLB | (DCacheTrapM | ICacheTrapM); // if the command is used in the READY state then the cache needs to be able to supress - // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. + // using both IgnoreRequestTLB and DCacheTrapM. Otherwise we can just use IgnoreRequestTLB. - assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. + assign DoFlush = FlushCache & ~(DCacheTrapM | ICacheTrapM); // do NOT suppress flush on DTLBMissM. Does not depend on address translation. assign AMO = CacheAtomic[1] & (&CacheRW); assign DoAMO = AMO & ~IgnoreRequest; assign DoRead = CacheRW[1] & ~IgnoreRequest; @@ -194,8 +194,8 @@ module cachefsm assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? - assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. - // use the raw requests as we don't want IgnoreRequestTrapM in the critical path + assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~(DCacheTrapM | ICacheTrapM))) | // Ignore Request is needed on TLB miss. + // use the raw requests as we don't want DCacheTrapM in the critical path (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & (DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9c1b8e77f..b009bcb4b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -223,7 +223,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0), + icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .ICacheTrapM(TrapM), .DCacheTrapM('0), .LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 5326df669..7f0dd395d 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -46,8 +46,7 @@ module interlockfsm( output logic InterlockStall, output logic SelReplayMemE, output logic SelHPTW, - output logic IgnoreRequestTLB, - output logic IgnoreRequestTrapM); + output logic IgnoreRequestTLB); logic ToITLBMiss; logic ToITLBMissNoReplay; @@ -105,6 +104,4 @@ module interlockfsm( assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM)); - assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) | - ((InterlockCurrState == STATE_T1_REPLAY) & (TrapM)); endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f38ded69a..95e9c8021 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -107,7 +107,7 @@ module lsu ( logic CacheableM; logic BusStall; logic InterlockStall; - logic IgnoreRequestTLB, IgnoreRequestTrapM; + logic IgnoreRequestTLB; logic BusCommittedM, DCacheCommittedM; logic SelLSUBusWord; logic DataDAPageFaultM; @@ -136,10 +136,10 @@ module lsu ( .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, - .IgnoreRequestTLB, .IgnoreRequestTrapM); + .IgnoreRequestTLB); end else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; - assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM; + assign CPUBusy = StallW; assign PreLSURWM = MemRWM; assign LSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; @@ -197,7 +197,7 @@ module lsu ( logic [`LLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; logic SelUncachedAdr; - assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; + assign IgnoreRequest = IgnoreRequestTLB | TrapM; if (`DMEM == `MEM_TIM) begin : dtim // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. @@ -245,7 +245,7 @@ module lsu ( .ByteMask(FinalByteMaskM), .WordCount, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), - .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM), + .IgnoreRequestTLB, .DCacheTrapM(TrapM), .ICacheTrapM(1'b0), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 751c2c928..748aa3df0 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -65,8 +65,7 @@ module lsuvirtmem( output logic InterlockStall, output logic CPUBusy, output logic SelHPTW, - output logic IgnoreRequestTLB, - output logic IgnoreRequestTrapM); + output logic IgnoreRequestTLB); logic AnyCPUReqM; @@ -87,7 +86,7 @@ module lsuvirtmem( interlockfsm interlockfsm ( .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF, .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM, - .InterlockStall, .SelReplayMemE, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); + .InterlockStall, .SelReplayMemE, .SelHPTW, .IgnoreRequestTLB); hptw hptw( .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,