mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
more progress.
This commit is contained in:
Ross Thompson
parent
2d6a6c6e44
commit
96793d15c0
@ -50,11 +50,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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@ -169,48 +169,48 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/BusState
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add wave -noupdate -expand -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/BusState
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive
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add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURSTD
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURSTD
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
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add wave -noupdate -expand -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/HRDATA
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
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add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHREADY
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add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHREADY
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add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
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add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
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@ -404,8 +404,12 @@ add wave -noupdate -expand -group CLINT /testbench/dut/uncore/uncore/clint/clint
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA
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add wave -noupdate -expand -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY
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add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uncore/uart/uart/u/LSR
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add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uncore/uart/uart/u/LSR
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add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
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add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
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add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
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add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
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@ -544,8 +548,9 @@ add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HSIZ
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRANS
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRANS
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck
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add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
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add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
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add wave -noupdate /testbench/dut/core/lsu/ByteMaskM
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {34777 ns} 0} {{Cursor 3} {334914 ns} 1} {{Cursor 4} {335206 ns} 1}
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WaveRestoreCursors {{Cursor 2} {34315 ns} 0} {{Cursor 3} {34791 ns} 1} {{Cursor 4} {335206 ns} 1}
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quietly wave cursor active 1
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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configure wave -valuecolwidth 314
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@ -561,4 +566,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timeline 0
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configure wave -timelineunits ns
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configure wave -timelineunits ns
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update
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update
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WaveRestoreZoom {34617 ns} {34937 ns}
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WaveRestoreZoom {34151 ns} {34471 ns}
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12
pipelined/src/cache/AHBBuscachefsm.sv
vendored
12
pipelined/src/cache/AHBBuscachefsm.sv
vendored
@ -75,7 +75,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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logic WordCountFlag;
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logic WordCountFlag;
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logic [2:0] LocalBurstType;
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic CntReset;
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logic [1:0] RWDelay, CacheRWDelay;
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assign CntReset = BusNextState == STATE_READY;
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assign CntReset = BusNextState == STATE_READY;
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@ -99,7 +99,11 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
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assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
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(BusNextState == STATE_READY & |CacheRW & HREADY);
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(BusNextState == STATE_READY & |CacheRW & HREADY);
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// replace with fsm with two more states.
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flopenr #(2) RWReg(HCLK, ~HRESETn, 1'b1, RW, RWDelay);
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flopenr #(2) CacheRWReg(HCLK, ~HRESETn, 1'b1, CacheRW, CacheRWDelay);
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always_ff @(posedge HCLK)
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always_ff @(posedge HCLK)
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if (~HRESETn) BusCurrState <= #1 STATE_READY;
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if (~HRESETn) BusCurrState <= #1 STATE_READY;
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@ -135,7 +139,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0]
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assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0]
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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assign CaptureEn = BusCurrState == STATE_CAPTURE | (BusCurrState == STATE_CACHE_ACCESS & HREADY);
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assign CaptureEn = (BusCurrState == STATE_CAPTURE & RWDelay[1]) | (BusCurrState == STATE_CACHE_ACCESS & HREADY & CacheRWDelay[1]);
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assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access.
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assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access.
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always_comb begin
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always_comb begin
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@ -154,7 +158,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign CacheBusAck = (BusCurrState == STATE_CACHE_ACCESS & HREADY & WordCountFlag);
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assign CacheBusAck = (BusCurrState == STATE_CACHE_ACCESS & HREADY & WordCountFlag);
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assign SelBusWord = (BusCurrState == STATE_READY & RW[0]) |
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assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |
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(BusCurrState == STATE_CAPTURE & RW[0]) |
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(BusCurrState == STATE_CAPTURE & RW[0]) |
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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@ -276,7 +276,12 @@ module lsu (
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.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
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.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
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flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM[`XLEN/8-1:0], LSUHWSTRB);
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// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
|
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logic [`XLEN/8-1:0] BusByteMaskM;
|
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|
swbytemask #(`XLEN) busswbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM));
|
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|
|
||||||
|
flop #(`XLEN/8) HWSTRBReg(clk, BusByteMaskM[`XLEN/8-1:0], LSUHWSTRB);
|
||||||
|
|
||||||
|
|
||||||
end else begin : passthrough // just needs a register to hold the value from the bus
|
end else begin : passthrough // just needs a register to hold the value from the bus
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user