From 9679345cae0dc8e2eae879f791fada04e37eac21 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 19 Jan 2021 22:58:56 -0500 Subject: [PATCH] testgen-ADD-SUB initial untested --- wally-pipelined/testgen/testgen-ADD-SUB.py | 132 +++++++++++++++++---- wally-pipelined/testgen/testgen_footer.S | 18 +++ wally-pipelined/testgen/testgen_header.S | 7 +- 3 files changed, 131 insertions(+), 26 deletions(-) mode change 100644 => 100755 wally-pipelined/testgen/testgen-ADD-SUB.py create mode 100644 wally-pipelined/testgen/testgen_footer.S diff --git a/wally-pipelined/testgen/testgen-ADD-SUB.py b/wally-pipelined/testgen/testgen-ADD-SUB.py old mode 100644 new mode 100755 index ce7db7b83..96d56df77 --- a/wally-pipelined/testgen/testgen-ADD-SUB.py +++ b/wally-pipelined/testgen/testgen-ADD-SUB.py @@ -1,38 +1,124 @@ +#!/usr/bin/python3 +################################## # testgen-ADD-SUB.py # # David_Harris@hmc.edu 19 January 2021 # # Generate directed and random test vectors for RISC-V Design Validation. +################################## +################################## # libraries -#import bitstream as bs +################################## +from datetime import datetime +from random import randint +from random import seed +from random import getrandbits -#corners = [0, 1, 2, 0xFF, 0x624B3E97CC52DD14, 0x7FFFFFFFFFFFFFFE, 0x7FFFFFFFFFFFFFFF, -# 0x8000000000000000, 0x8000000000000001, 0xC365DDEB9173AB42, 0xFFFFFFFFFFFFFFFE, 0xFFFFFFFFFFFFFFFF] -corners = [0, 1, 2, 255] +################################## +# functions +################################## -testname = "ADD-SUB" -fname = "WALLY-" + testname -testnum = 0; +def computeExpected(a, b, test): + if (test == "ADD"): + return a + b + elif (test == "SUB"): + return a - b + else: + die("bad test name ", test) + # exit(1) +def randRegs(): + reg1 = randint(1,32) + reg2 = randint(1,32) + reg3 = randint(1,32) + if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): + return randRegs() + else: + return reg1, reg2, reg3 +def writeVector(a,b): + global testnum + expected = computeExpected(a, b, test) + expected = expected % 2**xlen # drop carry if necessary + if (expected < 0): # take twos complement + expected = 2**xlen + expected + reg1, reg2, reg3 = randRegs() + lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) + lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) + lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" + lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" + lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" + lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" + lines = lines + "sd x" + str(reg3) + ", " + str(8*testnum) + "(x6)\n" + lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" + f.write(lines) + line = formatstr.format(expected)+"\n" + r.write(line) + testnum = testnum+1 - - - # Testcase 0: rs1:x31(0x10fd3dedadea5195), rs2:x16(0xdf7f3844121bcc23), result rd:x1(0xf07c7631c0061db8) - # li x16, MASK_XLEN(0xdf7f3844121bcc23) - #li x31, MASK_XLEN(0x10fd3dedadea5195) - # add x1, x31, x16 - # sd x1, 0(x6) - #RVTEST_IO_ASSERT_GPR_EQ(x7, x1, 0xf07c7631c0061db8) +################################## +# main body +################################## +# change these to suite your tests +tests = ["ADD", "SUB"] +author = "David_Harris@hmc.edu & Katherine Parry" +xlens = [32, 64] +numrand = 100; -f = open(fname, "w") -for a in corners: - for b in corners: - tc = "# Testcase " + str(testnum - f.write(tc) - line = "li x1, MASK_XLEN(" + str(a) + ")" +# setup +seed(0) # make tests reproducible + +# generate files for each test +for xlen in xlens: + formatstrlen = str(int(xlen/4)) + formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + for test in tests: + corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, + 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] + imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" + basename = "WALLY-" + test + fname = imperaspath + "src/" + basename + ".S" + refname = imperaspath + "references/" + basename + ".reference_output" + testnum = 0 + + # print custom header part + f = open(fname, "w") + r = open(refname, "w") + line = "///////////////////////////////////////////\n" f.write(line) - testnum = testnum+1 -f.close() \ No newline at end of file + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) + + # insert generic header + h = open("testgen_header.S", "r") + for line in h: + f.write(line) + + # print directed and random test vectors + for a in corners: + for b in corners: + writeVector(a, b) + for i in range(0,numrand): + a = getrandbits(xlen) + b = getrandbits(xlen) + writeVector(a, b) + + + # print footer + h = open("testgen_footer.S", "r") + for line in h: + f.write(line) + + # Finish + line = ".fill " + str(testnum) + ", 8, -1\n" + f.write(line) + f.close() + r.close() + + + + diff --git a/wally-pipelined/testgen/testgen_footer.S b/wally-pipelined/testgen/testgen_footer.S new file mode 100644 index 000000000..f7cc0b18b --- /dev/null +++ b/wally-pipelined/testgen/testgen_footer.S @@ -0,0 +1,18 @@ + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN + +test_1_res: diff --git a/wally-pipelined/testgen/testgen_header.S b/wally-pipelined/testgen/testgen_header.S index b09cb1503..118042a5c 100644 --- a/wally-pipelined/testgen/testgen_header.S +++ b/wally-pipelined/testgen/testgen_header.S @@ -1,6 +1,6 @@ - // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// Adapted from Imperas RISCV-TEST_SUITE // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, @@ -30,8 +30,9 @@ RV_COMPLIANCE_CODE_BEGIN # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test group 1\n") + #RVTEST_IO_WRITE_STR(x31, "# Test group 1\n") # address for test results - la x6, test_1_res \ No newline at end of file + la x6, test_1_res + \ No newline at end of file