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improve hart status signalling

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Matthew 2024-06-09 11:26:58 -05:00
parent 7f63daa49c
commit 95df21ff1e
3 changed files with 63 additions and 30 deletions
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30
src/debug/dm.sv
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@ -85,10 +85,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
logic ResumeReq; logic ResumeReq;
logic HaltOnReset; logic HaltOnReset;
logic Halted; logic Halted;
logic AckHaveReset;
hartcontrol hartcontrol(.clk, .rst(rst | ~DmActive), .NdmReset, .HaltReq, hartcontrol hartcontrol(.clk, .rst(rst | ~DmActive), .NdmReset, .AckHaveReset, .HaltReq,
.ResumeReq, .HaltOnReset, .DebugStall, .Halted, .AllRunning, .ResumeReq, .HaltOnReset, .DebugStall, .Halted, .AllRunning, .AnyRunning,
.AnyRunning, .AllHalted, .AnyHalted, .AllResumeAck, .AnyResumeAck); .AllHalted, .AnyHalted, .AllResumeAck, .AnyResumeAck, .AllHaveReset, .AnyHaveReset);
enum logic [3:0] {INACTIVE, IDLE, ACK, R_DATA, W_DATA, DMSTATUS, W_DMCONTROL, R_DMCONTROL, enum logic [3:0] {INACTIVE, IDLE, ACK, R_DATA, W_DATA, DMSTATUS, W_DMCONTROL, R_DMCONTROL,
@ -137,9 +138,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
// DMStatus // DMStatus
logic StickyUnavail; logic StickyUnavail;
logic ImpEBreak; logic ImpEBreak;
logic AllHaveReset;
logic AnyHaveReset;
logic AllResumeAck; logic AllResumeAck;
logic AnyResumeAck; logic AnyResumeAck;
logic AllNonExistent; logic AllNonExistent; // TODO
logic AnyNonExistent; logic AnyNonExistent;
logic AllUnavail; // TODO logic AllUnavail; // TODO
logic AnyUnavail; logic AnyUnavail;
@ -164,7 +167,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
10'b0, 4'b0, NdmReset, DmActive}; 10'b0, 4'b0, NdmReset, DmActive};
assign DMStatus = {7'b0, 1'b0, StickyUnavail, ImpEBreak, 2'b0, assign DMStatus = {7'b0, 1'b0, StickyUnavail, ImpEBreak, 2'b0,
2'b0, AllResumeAck, AnyResumeAck, AllNonExistent, AllHaveReset, AnyHaveReset, AllResumeAck, AnyResumeAck, AllNonExistent,
AnyNonExistent, AllUnavail, AnyUnavail, AllRunning, AnyRunning, AllHalted, AnyNonExistent, AllUnavail, AnyUnavail, AllRunning, AnyRunning, AllHalted,
AnyHalted, Authenticated, AuthBusy, HasResetHaltReq, ConfStrPtrValid, Version}; AnyHalted, Authenticated, AuthBusy, HasResetHaltReq, ConfStrPtrValid, Version};
@ -183,8 +186,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
case (State) case (State)
INACTIVE : begin INACTIVE : begin
// Reset Values // Reset Values
// TODO: one-line these
RspData <= 0; RspData <= 0;
HaltReq <= 0; HaltReq <= 0;
ResumeReq <= 0;
AckHaveReset <= 0;
HaltOnReset <= 0; HaltOnReset <= 0;
NdmReset <= 0; NdmReset <= 0;
StickyUnavail <= 0; StickyUnavail <= 0;
@ -204,6 +210,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
ACK : begin ACK : begin
NewAcState <= AC_IDLE; NewAcState <= AC_IDLE;
ResumeReq <= 0; ResumeReq <= 0;
AckHaveReset <= 0;
if (~ReqValid) if (~ReqValid)
State <= ~DmActive ? INACTIVE : IDLE; State <= ~DmActive ? INACTIVE : IDLE;
end end
@ -256,7 +263,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
W_DMCONTROL : begin W_DMCONTROL : begin
// While an abstract command is executing (busy in abstractcs is high), a debugger must not change // While an abstract command is executing (busy in abstractcs is high), a debugger must not change
// hartsel, and must not write 1 to haltreq, resumereq, ackhavereset, setresethaltreq, or clrresethaltreq // hartsel, and must not write 1 to haltreq, resumereq, ackhavereset, setresethaltreq, or clrresethaltreq
if (Busy & (ReqData[`HALTREQ] | ReqData[`RESUMEREQ] | ReqData[`SETRESETHALTREQ] | ReqData[`CLRRESETHALTREQ])) if (Busy & (ReqData[`HALTREQ] | ReqData[`RESUMEREQ] | ReqData[`ACKHAVERESET] | ReqData[`SETRESETHALTREQ] | ReqData[`CLRRESETHALTREQ]))
CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr; CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
else begin else begin
HaltReq <= ReqData[`HALTREQ]; HaltReq <= ReqData[`HALTREQ];
@ -266,11 +273,12 @@ module dm import cvw::*; #(parameter cvw_t P) (
// On any given write, a debugger may only write 1 to at most one of the following bits: resumereq, // On any given write, a debugger may only write 1 to at most one of the following bits: resumereq,
// hartreset, ackhavereset, setresethaltreq, and clrresethaltreq. The others must be written 0 // hartreset, ackhavereset, setresethaltreq, and clrresethaltreq. The others must be written 0
case ({ReqData[`RESUMEREQ],ReqData[`SETRESETHALTREQ],ReqData[`CLRRESETHALTREQ]}) case ({ReqData[`RESUMEREQ],ReqData[`ACKHAVERESET],ReqData[`SETRESETHALTREQ],ReqData[`CLRRESETHALTREQ]})
3'b000 :; // None 4'b0000 :; // None
3'b100 : ResumeReq <= 1; 4'b1000 : ResumeReq <= 1;
3'b010 : HaltOnReset <= 1; 4'b0100 : AckHaveReset <= 1;
3'b001 : HaltOnReset <= 0; 4'b0010 : HaltOnReset <= 1;
4'b0001 : HaltOnReset <= 0;
default : begin // Invalid (not onehot), dont write any changes default : begin // Invalid (not onehot), dont write any changes
HaltReq <= HaltReq; HaltReq <= HaltReq;
AckUnavail <= AckUnavail; AckUnavail <= AckUnavail;

2
src/debug/dtm.sv
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@ -55,7 +55,7 @@ module dtm #(parameter ADDR_WIDTH, parameter JTAG_DEVICE_ID) (
// Clock Domain Crossing // Clock Domain Crossing
logic tcks; // Synchronized JTAG clock logic tcks; // Synchronized JTAG clock
logic resetn; logic resetn; // TODO: reset DM (but not hart)
logic UpdateDtmcs; logic UpdateDtmcs;
logic [31:0] DtmcsIn; logic [31:0] DtmcsIn;
logic [31:0] DtmcsOut; logic [31:0] DtmcsOut;

39
src/debug/hartcontrol.sv
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@ -30,6 +30,7 @@
module hartcontrol( module hartcontrol(
input logic clk, rst, input logic clk, rst,
input logic NdmReset, // Triggers HaltOnReset behavior input logic NdmReset, // Triggers HaltOnReset behavior
input logic AckHaveReset, // Clears *HaveReset status
input logic HaltReq, // Initiate core halt input logic HaltReq, // Initiate core halt
input logic ResumeReq, // Initiates core resume input logic ResumeReq, // Initiates core resume
@ -44,18 +45,31 @@ module hartcontrol(
output logic AllHalted, output logic AllHalted,
output logic AnyHalted, output logic AnyHalted,
output logic AllResumeAck, output logic AllResumeAck,
output logic AnyResumeAck output logic AnyResumeAck,
output logic AllHaveReset,
output logic AnyHaveReset
); );
enum logic {RUNNING, HALTED} State;
assign AnyHaveReset = AllHaveReset;
always_ff @(posedge clk) begin
if (NdmReset)
AllHaveReset <= 1;
else if (AckHaveReset)
AllHaveReset <= 0;
end
assign Halted = DebugStall; assign Halted = DebugStall;
assign AllRunning = ~DebugStall; assign AllRunning = ~DebugStall;
assign AnyRunning = ~DebugStall; assign AnyRunning = ~DebugStall;
assign AllHalted = DebugStall; assign AllHalted = DebugStall;
assign AnyHalted = DebugStall; assign AnyHalted = DebugStall;
assign AllResumeAck = ~DebugStall; // BOZO: when sdext is implemented (proper step support is added)
assign AnyResumeAck = ~DebugStall; // change ResumeReq to be ignored when HaltReq
// but ResumeReq should still always clear *ResumeAck
enum logic {RUNNING, HALTED} State; assign AnyResumeAck = AllResumeAck;
assign DebugStall = (State == HALTED); assign DebugStall = (State == HALTED);
@ -66,9 +80,20 @@ module hartcontrol(
State <= HaltOnReset ? HALTED : RUNNING; State <= HaltOnReset ? HALTED : RUNNING;
else begin else begin
case (State) case (State)
RUNNING : State <= HaltReq ? HALTED : RUNNING; RUNNING : begin
if (HaltReq) begin
State <= HALTED;
end else if (ResumeReq) begin
AllResumeAck <= 0;
end
end
HALTED : State <= ResumeReq ? RUNNING : HALTED; HALTED : begin
if (ResumeReq) begin
State <= RUNNING;
AllResumeAck <= 1;
end
end
endcase endcase
end end
end end