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This commit is contained in:
David Harris 2021-06-07 09:50:23 -04:00
commit 95cc70295b
74 changed files with 221290 additions and 124689 deletions
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30
testsBP/crt0/pcnt_driver.h Normal file
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#ifndef __PCNT_DRIVER_H
#define __PCNT_DRIVER_H
long int readPerfCnt(long int cntNum, int clear);
void enablePerfCnt(long int flags);
void disablePerfCnt(long int flags);
#define CYCLE_COUNT (0)
#define INSTR_COUNT (2)
#define LOAD_STAL_COUNT (3)
#define BP_WRONG_DIR_COUNT (4)
#define BR_DIR_COUNT (5)
#define BTB_WRONG_COUNT (6)
#define NON_BR_CFI_COUNT (7)
#define RAS_WRONG_COUNT (8)
#define RETURN_COUNT (9)
#define BTB_CLASS_WRONG_COUNT (10)
#define CYCLE_COUNT_EN (1)
#define INSTR_COUNT_EN (1 << 2)
#define LOAD_STAL_COUNT_EN (1 << 3)
#define BP_WRONG_DIR_COUNT_EN (1 << 4)
#define BR_DIR_COUNT_EN (1 << 5)
#define BTB_WRONG_COUNT_EN (1 << 6)
#define NON_BR_CFI_COUNT_EN (1 << 7)
#define RAS_WRONG_COUNT_EN (1 << 8)
#define RETURN_COUNT_EN (1 << 9)
#define BTB_CLASS_WRONG_COUNT_EN (1 << 10)
#endif

147
testsBP/crt0/pcnt_driver.s Normal file
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.section .text
.global enablePerfCnt
.type enablePerfCnt, @function
enablePerfCnt:
# a0 is the mask
csrrc x0, 0x320, a0 # clear bits to disable inhibit register
ret
.section .text
.global disablePerfCnt
.type disablePerfCnt, @function
disablePerfCnt:
# a0 is the mask
csrrs x0, 0x320, a0 # set bits to disable inhibit register
ret
.section .text
.global readPerfCnt
.type readPerfCnt, @function
readPerfCnt:
# a0 is the counter to read
# a1 is the flag to clear the register
# return the value of the counter in a0
li t0, 0xB
# if the counter number is greater than the number
# of counters return a -1
bge a0, t0, readPerfCntError
# pointers are 8 bytes so shift a0 by 8
slli a0, a0, 3
li t1, 1
beq a1, t1, readPerfCntClear
la t0, csrTable
j skip
readPerfCntClear:
la t0, csrTable_clear
skip:
add t0, t0, a0
ld t0, 0(t0)
jr t0
csrCycle:
csrrs a0, 0xB00, x0
ret
csrNull:
li a0, -1
ret
csrInstrCount:
csrrs a0, 0xB02, x0
ret
csrLoadStallCount:
csrrs a0, 0xB03, x0
ret
csrBPWrongCount:
csrrs a0, 0xB04, x0
ret
csrBPCount:
csrrs a0, 0xB05, x0
ret
csrBTBWrongCount:
csrrs a0, 0xB06, x0
ret
csrNonBRCFICount:
csrrs a0, 0xB07, x0
ret
csrRasWrongCount:
csrrs a0, 0xB08, x0
ret
csrReturnCount:
csrrs a0, 0xB09, x0
ret
csrBTBClassWrongCount:
csrrs a0, 0xB0A, x0
ret
csrCycle_clear:
csrrw a0, 0xB00, x0
ret
csrNull_clear:
li a0, -1
ret
csrInstrCount_clear:
csrrw a0, 0xB02, x0
ret
csrLoadStallCount_clear:
csrrw a0, 0xB03, x0
ret
csrBPWrongCount_clear:
csrrw a0, 0xB04, x0
ret
csrBPCount_clear:
csrrw a0, 0xB05, x0
ret
csrBTBWrongCount_clear:
csrrw a0, 0xB06, x0
ret
csrNonBRCFICount_clear:
csrrw a0, 0xB07, x0
ret
csrRasWrongCount_clear:
csrrw a0, 0xB08, x0
ret
csrReturnCount_clear:
csrrw a0, 0xB09, x0
ret
csrBTBClassWrongCount_clear:
csrrw a0, 0xB0A, x0
ret
readPerfCntError:
li a0, -1
ret
.section .data
.align 3
csrTable:
.8byte csrCycle #0
.8byte csrNull #1
.8byte csrInstrCount #2
.8byte csrLoadStallCount #3
.8byte csrBPWrongCount #4
.8byte csrBPCount #5
.8byte csrBTBWrongCount #6
.8byte csrNonBRCFICount #7
.8byte csrRasWrongCount #8
.8byte csrReturnCount #9
.8byte csrBTBClassWrongCount #A
csrTable_clear:
.8byte csrCycle_clear #0
.8byte csrNull_clear #1
.8byte csrInstrCount_clear #2
.8byte csrLoadStallCount_clear #3
.8byte csrBPWrongCount_clear #4
.8byte csrBPCount_clear #5
.8byte csrBTBWrongCount_clear #6
.8byte csrNonBRCFICount_clear #7
.8byte csrRasWrongCount_clear #8
.8byte csrReturnCount_clear #9
.8byte csrBTBClassWrongCount_clear #A

24
testsBP/crt0/pre_main.c Normal file
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#include <stdlib.h>
#include "pcnt_driver.h"
int pre_main(int argc, char *argv[]) {
long int bpmp0, brcnt0, bpmp1, brcnt1;
long int bpmp_diff, brcnt_diff;
bpmp0 = readPerfCnt(BP_WRONG_DIR_COUNT, 0);
brcnt0 = readPerfCnt(BR_DIR_COUNT, 0);
// enable counters
enablePerfCnt(BP_WRONG_DIR_COUNT_EN | BR_DIR_COUNT_EN);
int res = main(argc, argv);
disablePerfCnt(BP_WRONG_DIR_COUNT_EN | BR_DIR_COUNT_EN);
bpmp1 = readPerfCnt(BP_WRONG_DIR_COUNT, 0);
brcnt1 = readPerfCnt(BR_DIR_COUNT, 0);
bpmp_diff = bpmp1 - bpmp0;
brcnt_diff = brcnt1 - brcnt0;
return res;
}

18
testsBP/james_mm/Makefile Normal file
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TARGETDIR := mmm
TARGET := $(TARGETDIR)/$(TARGETDIR).elf
ROOT := ..
LIBRARY_DIRS := ${ROOT}/crt0
LIBRARY_FILES := crt0
MARCH :=-march=rv64imfdc
MABI :=-mabi=lp64d
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
CC=riscv64-unknown-elf-gcc
DA=riscv64-unknown-elf-objdump -d
include $(ROOT)/makefile.inc

235
testsBP/james_mm/james_mm.c Normal file
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#include <stdio.h>
typedef double Float;
Float C[100][100];
Float A[100][100] = { {1.02774012088775634765625, 1.61730301380157470703125, 1.8952558040618896484375, 1.404462337493896484375, 1.98954677581787109375, 1.167797565460205078125, 1.55445158481597900390625, 1.9668743610382080078125, 1.5313637256622314453125, 1.53427755832672119140625, 1.64590275287628173828125, 1.2509534358978271484375, 1.6938021183013916015625, 1.039519786834716796875, 1.213516712188720703125, 1.86304569244384765625, 1.7330493927001953125, 1.51679909229278564453125, 1.77849543094635009765625, 1.40046405792236328125, 1.83180654048919677734375, 1.95832598209381103515625, 1.42527329921722412109375, 1.4749257564544677734375, 1.56022608280181884765625, 1.9136836528778076171875, 1.637454986572265625, 1.48598992824554443359375, 1.08684885501861572265625, 1.63826620578765869140625, 1.88375222682952880859375, 1.14449465274810791015625, 1.1395418643951416015625, 1.9917156696319580078125, 1.95392167568206787109375, 1.74599516391754150390625, 1.7164361476898193359375, 1.08635962009429931640625, 1.0447027683258056640625, 1.19420087337493896484375, 1.546863555908203125, 1.68564879894256591796875, 1.59575450420379638671875, 1.77441298961639404296875, 1.30229461193084716796875, 1.3525941371917724609375, 1.87559330463409423828125, 1.6769621372222900390625, 1.55727636814117431640625, 1.34820497035980224609375, 1.3175308704376220703125, 1.2706453800201416015625, 1.50036919116973876953125, 1.2799260616302490234375, 1.60561096668243408203125, 1.12616443634033203125, 1.3950846195220947265625, 1.50007522106170654296875, 1.5105473995208740234375, 1.789562702178955078125, 1.7908232212066650390625, 1.2542808055877685546875, 1.47566127777099609375, 1.3056628704071044921875, 1.48381137847900390625, 1.579919338226318359375, 1.95281898975372314453125, 1.49150454998016357421875, 1.22803914546966552734375, 1.95455253124237060546875, 1.488368988037109375, 1.95978128910064697265625, 1.19619810581207275390625, 1.69436550140380859375, 1.559079647064208984375, 1.89227879047393798828125, 1.19061815738677978515625, 1.10260379314422607421875, 1.15807712078094482421875, 1.56331193447113037109375, 1.60420548915863037109375, 1.368010997772216796875, 1.13078212738037109375, 1.61316239833831787109375, 1.1313798427581787109375, 1.2132663726806640625, 1.2608478069305419921875, 1.07151615619659423828125, 1.22901248931884765625, 1.29342186450958251953125, 1.10609757900238037109375, 1.1309010982513427734375, 1.32736301422119140625, 1.34434032440185546875, 1.5844619274139404296875, 1.670124053955078125, 1.79101717472076416015625, 1.08113253116607666015625, 1.3099162578582763671875, 1.52770900726318359375},
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};
void main() {
int k;
int i;
int j;
int NCB;
int NRA;
int NCA;
NCA = 100;
NRA = 100;
NCB = 100;
for (k=0; k < NCB; k++)
for (i=0; i < NRA; i++) {
C[i][k] = 0.0;
for (j=0; j < NCA; j++) {
C[i][k] = C[i][k] + A[i][j] * B[j][k];
}
}
}

4
testsBP/simple/Makefile
View File

@ -4,8 +4,8 @@ ROOT := ..
LIBRARY_DIRS := ${ROOT}/crt0 LIBRARY_DIRS := ${ROOT}/crt0
LIBRARY_FILES := crt0 LIBRARY_FILES := crt0
MARCH :=-march=rv64ic MARCH :=-march=rv64imfdc
MABI :=-mabi=lp64 MABI :=-mabi=lp64d
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2

103
testsBP/simple/global_hist_test.s Normal file
View File

@ -0,0 +1,103 @@
.section .text
.globl global_hist_3_space_test
.type global_hist_3_space_test, @function
global_hist_3_space_test:
li t1, 1
li t2, 200
li t3, 0
li t4, 1
loop_3:
# instruction
addi t3, t3, 1
addi t3, t3, 1
addi t3, t3, 1
beqz t4, zero_3 # this branch toggles between taken and not taken.
li t4, 0
j one_3
zero_3:
li t4, 1
add t1, t1, t4
one_3:
addi t3, t3, 1
addi t2, t2, -1
bnez t2, loop_3
ret
.section .text
.globl global_hist_2_space_test
.type global_hist_2_space_test, @function
global_hist_2_space_test:
li t1, 1
li t2, 200
li t3, 0
li t4, 1
loop_2:
# instruction
addi t3, t3, 1
addi t3, t3, 1
beqz t4, zero_2 # this branch toggles between taken and not taken.
li t4, 0
j one_2
zero_2:
li t4, 1
add t1, t1, t4
one_2:
addi t2, t2, -1
bnez t2, loop_2
ret
.section .text
.globl global_hist_1_space_test
.type global_hist_1_space_test, @function
global_hist_1_space_test:
li t1, 1
li t2, 200
li t3, 0
li t4, 1
loop_1:
# instruction
addi t3, t3, 1
beqz t4, zero_1 # this branch toggles between taken and not taken.
li t4, 0
j one_1
zero_1:
li t4, 1
add t1, t1, t4
one_1:
addi t2, t2, -1
bnez t2, loop_1
ret
.section .text
.globl global_hist_0_space_test
.type global_hist_0_space_test, @function
global_hist_0_space_test:
li t1, 1
li t2, 200
li t3, 0
li t4, 1
loop_0:
# instruction
beqz t4, zero_0 # this branch toggles between taken and not taken.
li t4, 0
j one_0
zero_0:
li t4, 1
add t1, t1, t4
one_0:
addi t2, t2, -1
bnez t2, loop_0
ret

9
wally-pipelined/config/buildroot/wally-config.vh
View File

@ -38,6 +38,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -49,6 +55,9 @@
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000000001000 `define RESET_VECTOR 64'h0000000000001000

9
wally-pipelined/config/busybear/wally-config.vh
View File

@ -38,6 +38,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -49,6 +55,9 @@
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000000001000 `define RESET_VECTOR 64'h0000000000001000

6
wally-pipelined/config/coremark-64i/wally-config.vh
View File

@ -34,6 +34,12 @@
`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20) `define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20)
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1

4
wally-pipelined/config/coremark/wally-config.vh
View File

@ -50,6 +50,10 @@
`define MEM_DTIM 1 `define MEM_DTIM 1
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h00000000000100b0 `define RESET_VECTOR 64'h00000000000100b0

9
wally-pipelined/config/coremark_bare/wally-config.vh
View File

@ -38,6 +38,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -49,6 +55,9 @@
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000

9
wally-pipelined/config/rv32ic/wally-config.vh
View File

@ -37,6 +37,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -48,6 +54,9 @@
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 32'h80000000 `define RESET_VECTOR 32'h80000000

9
wally-pipelined/config/rv64BP/wally-config.vh
View File

@ -39,6 +39,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -50,6 +56,9 @@
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000000000000 `define RESET_VECTOR 64'h0000000000000000

9
wally-pipelined/config/rv64ic/wally-config.vh
View File

@ -38,6 +38,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -49,6 +55,9 @@
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000

3
wally-pipelined/config/rv64icfd/wally-config.vh
View File

@ -52,6 +52,9 @@
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000

10
wally-pipelined/config/rv64imc/wally-config.vh
View File

@ -38,6 +38,12 @@
`define ZCSR_SUPPORTED 1 `define ZCSR_SUPPORTED 1
`define COUNTERS 31 `define COUNTERS 31
`define ZCOUNTERS_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1
<<<<<<< HEAD
=======
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
`define N_SUPPORTED 0
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Microarchitectural Features // Microarchitectural Features
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
@ -47,6 +53,10 @@
`define MEM_DTIM 1 `define MEM_DTIM 1
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRY_BITS 5
`define DTLB_ENTRY_BITS 5
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000

11
wally-pipelined/config/shared/wally-constants.vh
View File

@ -28,10 +28,14 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
<<<<<<< HEAD
// Privileged modes // Privileged modes
`define M_MODE (2'b11) `define M_MODE (2'b11)
`define S_MODE (2'b01) `define S_MODE (2'b01)
`define U_MODE (2'b00) `define U_MODE (2'b00)
=======
`include "wally-config.vh"
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
// Virtual Memory Constants // Virtual Memory Constants
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) `define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
@ -47,3 +51,10 @@
`define SV32 1 `define SV32 1
`define SV39 8 `define SV39 8
`define SV48 9 `define SV48 9
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
`define M_MODE (2'b11)
`define S_MODE (2'b01)
`define U_MODE (2'b00)

4
wally-pipelined/lint-wally
View File

@ -7,7 +7,11 @@ verilator=`which verilator`
basepath=$(dirname $0) basepath=$(dirname $0)
for config in rv64ic rv32ic; do for config in rv64ic rv32ic; do
echo "$config linting..." echo "$config linting..."
<<<<<<< HEAD
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv); then if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv); then
=======
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then
>>>>>>> 64a687b80fbd04a02ac986dde4802d9324aa6ac1
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"
exit 1 exit 1
fi fi

1
wally-pipelined/regression/sim-wally-rv64icfd Executable file
View File

@ -0,0 +1 @@
vsim -do wally-pipelined-rv64icfd.do

50
wally-pipelined/regression/wally-pipelined-rv64icfd.do Normal file
View File

@ -0,0 +1,50 @@
# wally-pipelined.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Use this wally-pipelined.do file to run this example.
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
# do wally-pipelined.do
# or, to run from a shell, type the following at the shell prompt:
# vsim -do wally-pipelined.do -c
# (omit the "-c" to see the GUI while running from the shell)
onbreak {resume}
# create library
if [file exists work] {
vdel -all
}
vlib work
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt +acc work.testbench -o workopt
vsim workopt
view wave
-- display input and output signals as hexidecimal values
do ./wave-dos/default-waves.do
-- Run the Simulation
#run 5000
run -all
#quit
noview ../testbench/testbench-imperas.sv
view wave

197
wally-pipelined/regression/wave.do
View File

@ -7,59 +7,88 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
@ -88,18 +117,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
add wave -noupdate -expand -group alu -divider internals add wave -noupdate -group alu -divider internals
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
@ -130,13 +159,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group PCS /testbench/dut/hart/PCF
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD add wave -noupdate -group PCS /testbench/dut/hart/PCE
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE add wave -noupdate -group PCS /testbench/dut/hart/PCM
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM add wave -noupdate -group PCS /testbench/PCW
add wave -noupdate -expand -group PCS /testbench/PCW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
@ -169,13 +197,12 @@ add wave -noupdate -expand -group icache -expand -group {fsm out and control} /t
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN
add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF
@ -185,8 +212,6 @@ add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/ha
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag
add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable
add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine
@ -214,10 +239,12 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF add wave -noupdate -group csr -color Aquamarine -label {br executed} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]}
add wave -noupdate -group csr -color Aquamarine -label {br miss predicted} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]}
add wave -noupdate -group csr -childformat {{{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned}} /testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {252630976 ns} 1} {{Cursor 4} {72696935 ns} 0} {{Cursor 3} {252631405 ns} 0} WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {12105831 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 2
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 189 configure wave -valuecolwidth 189
configure wave -justifyvalue left configure wave -justifyvalue left
@ -232,4 +259,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {252630882 ns} {252631198 ns} WaveRestoreZoom {0 ns} {30754715 ns}

85
wally-pipelined/src/ifu/icache.sv → wally-pipelined/src/cache/ICacheCntrl.sv vendored
View File

@ -1,10 +1,10 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// icache.sv // icache.sv
// //
// Written: jaallen@g.hmc.edu 2021-03-02 // Written: ross1728@gmail.com June 04, 2021
// Modified: // Modified:
// //
// Purpose: Cache instructions for the ifu so it can access memory less often, saving cycles // Purpose: I Cache controller
// //
// A component of the Wally configurable RISC-V project. // A component of the Wally configurable RISC-V project.
// //
@ -25,62 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module icache( module ICacheCntrl #(parameter BLOCKLEN = 256) (
// Basic pipeline stuff
input logic clk, reset,
input logic StallF, StallD,
input logic FlushD,
input logic [`XLEN-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF,
// Data read in from the ebu unit
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
// Read requested from the ebu unit
output logic [`XLEN-1:0] InstrPAdrF,
output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed
output logic CompressedF,
// High if the icache is requesting a stall
output logic ICacheStallF,
// The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
output logic [31:0] InstrRawD
);
// Configuration parameters
// TODO Move these to a config file
localparam integer ICACHELINESIZE = 256;
localparam integer ICACHENUMLINES = 512;
// Input signals to cache memory
logic FlushMem;
logic ICacheMemWriteEnable;
logic [ICACHELINESIZE-1:0] ICacheMemWriteData;
logic EndFetchState;
logic [`XLEN-1:0] PCTagF, PCNextIndexF;
// Output signals from cache memory
logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid;
logic ICacheReadEn;
rodirectmappedmemre #(.LINESIZE(ICACHELINESIZE), .NUMLINES(ICACHENUMLINES), .WORDSIZE(`XLEN))
cachemem(
.*,
// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
.flush(FlushMem),
.WriteEnable(ICacheMemWriteEnable),
.WriteLine(ICacheMemWriteData),
.DataWord(ICacheMemReadData),
.DataValid(ICacheMemReadValid)
);
icachecontroller #(.LINESIZE(ICACHELINESIZE)) controller(.*);
// For now, assume no writes to executable memory
assign FlushMem = 1'b0;
endmodule
module icachecontroller #(parameter LINESIZE = 256) (
// Inputs from pipeline // Inputs from pipeline
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, input logic StallF, StallD,
@ -100,7 +45,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
output logic ICacheReadEn, output logic ICacheReadEn,
// Load data into the cache // Load data into the cache
output logic ICacheMemWriteEnable, output logic ICacheMemWriteEnable,
output logic [LINESIZE-1:0] ICacheMemWriteData, output logic [BLOCKLEN-1:0] ICacheMemWriteData,
// Outputs to rest of ifu // Outputs to rest of ifu
// High if the instruction in the fetch stage is compressed // High if the instruction in the fetch stage is compressed
@ -169,10 +114,10 @@ module icachecontroller #(parameter LINESIZE = 256) (
localparam AHBOFFETWIDTH = $clog2(AHBByteLength); localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
localparam BlockByteLength = LINESIZE / 8; localparam BlockByteLength = BLOCKLEN / 8;
localparam OFFSETWIDTH = $clog2(BlockByteLength); localparam OFFSETWIDTH = $clog2(BlockByteLength);
localparam WORDSPERLINE = LINESIZE/`XLEN; localparam WORDSPERLINE = BLOCKLEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGWPL = $clog2(WORDSPERLINE);
logic [4:0] CurrState, NextState; logic [4:0] CurrState, NextState;
@ -196,16 +141,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
logic [15:0] SpillDataBlock0; logic [15:0] SpillDataBlock0;
logic FlushDLastCyclen;
// Happy path signals
logic [31:0] AlignedInstrRawD;
//logic [31:0] AlignedInstrRawF, AlignedInstrRawD;
//logic FlushDLastCycleN;
//logic PCPMisalignedF;
localparam [31:0] NOP = 32'h13; localparam [31:0] NOP = 32'h13;
//logic [`XLEN-1:0] PCPF;
logic reset_q; logic reset_q;
logic [1:0] PCMux_q; logic [1:0] PCMux_q;
@ -514,13 +450,6 @@ module icachecontroller #(parameter LINESIZE = 256) (
.d(reset), .d(reset),
.q(reset_q)); .q(reset_q));
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FinalInstrRawF, NOP, AlignedInstrRawD); flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? NOP : FinalInstrRawF, NOP, InstrRawD);
// cannot have this mux as it creates a combo loop.
// This flop doesn't stall if StallF is high because we should output a nop
// when FlushD happens, even if the pipeline is also stalled.
flopr #(1) flushDLastCycleFlop(clk, reset, ~FlushD & (FlushDLastCyclen | ~StallF), FlushDLastCyclen);
mux2 #(32) InstrRawDMux(AlignedInstrRawD, NOP, ~FlushDLastCyclen, InstrRawD);
//assign InstrRawD = AlignedInstrRawD;
endmodule endmodule

59
wally-pipelined/src/cache/ICacheMem.sv vendored Normal file
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@ -0,0 +1,59 @@
`include "wally-config.vh"
module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256)
(
// Pipeline stuff
input logic clk,
input logic reset,
// If flush is high, invalidate the entire cache
input logic flush,
input logic [`XLEN-1:0] PCTagF, // physical address
input logic [`XLEN-1:0] PCNextIndexF, // virtual address
input logic WriteEnable,
input logic [BLOCKLEN-1:0] WriteLine,
output logic [BLOCKLEN-1:0] ReadLineF,
output logic HitF
);
// divide the address bus into sections; tag, index, and offset
localparam BLOCKBYTELEN = BLOCKLEN/8;
localparam OFFSETLEN = $clog2(BLOCKBYTELEN);
localparam INDEXLEN = $clog2(NUMLINES);
// *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48
localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN;
logic [TAGLEN-1:0] LookupTag;
logic [NUMLINES-1:0] ValidOut;
logic DataValidBit;
// Depth is number of bits in one "word" of the memory, width is number of such words
sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES))
cachemem (.*,
.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(ReadLineF),
.WriteData(WriteLine)
);
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
cachetags (.*,
.Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.ReadData(LookupTag),
.WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN])
);
// Correctly handle the valid bits
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
ValidOut <= {NUMLINES{1'b0}};
end else if (flush) begin
ValidOut <= {NUMLINES{1'b0}};
end else begin
if (WriteEnable) begin
ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1;
end
end
DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]];
end
assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]);
endmodule

110
wally-pipelined/src/cache/icache.sv vendored Normal file
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@ -0,0 +1,110 @@
///////////////////////////////////////////
// icache.sv
//
// Written: jaallen@g.hmc.edu 2021-03-02
// Modified:
//
// Purpose: Cache instructions for the ifu so it can access memory less often, saving cycles
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module icache
(
// Basic pipeline stuff
input logic clk, reset,
input logic StallF, StallD,
input logic FlushD,
input logic [`XLEN-1:0] PCNextF,
input logic [`XLEN-1:0] PCPF,
// Data read in from the ebu unit
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
// Read requested from the ebu unit
output logic [`XLEN-1:0] InstrPAdrF,
output logic InstrReadF,
// High if the instruction currently in the fetch stage is compressed
output logic CompressedF,
// High if the icache is requesting a stall
output logic ICacheStallF,
// The raw (not decompressed) instruction that was requested
// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
output logic [31:0] InstrRawD
);
// Configuration parameters
// TODO Move these to a config file
localparam integer BLOCKLEN = 256;
localparam integer NUMLINES = 512;
// Input signals to cache memory
logic FlushMem;
logic ICacheMemWriteEnable;
logic [BLOCKLEN-1:0] ICacheMemWriteData;
logic EndFetchState;
logic [`XLEN-1:0] PCTagF, PCNextIndexF;
// Output signals from cache memory
logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid;
logic ICacheReadEn;
logic [BLOCKLEN-1:0] ReadLineF;
ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES))
cachemem(
.*,
// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
.flush(FlushMem),
.WriteEnable(ICacheMemWriteEnable),
.WriteLine(ICacheMemWriteData),
.ReadLineF(ReadLineF),
.HitF(ICacheMemReadValid)
);
always_comb begin
case (PCTagF[4:1])
0: ICacheMemReadData = ReadLineF[31:0];
1: ICacheMemReadData = ReadLineF[47:16];
2: ICacheMemReadData = ReadLineF[63:32];
3: ICacheMemReadData = ReadLineF[79:48];
4: ICacheMemReadData = ReadLineF[95:64];
5: ICacheMemReadData = ReadLineF[111:80];
6: ICacheMemReadData = ReadLineF[127:96];
7: ICacheMemReadData = ReadLineF[143:112];
8: ICacheMemReadData = ReadLineF[159:128];
9: ICacheMemReadData = ReadLineF[175:144];
10: ICacheMemReadData = ReadLineF[191:160];
11: ICacheMemReadData = ReadLineF[207:176];
12: ICacheMemReadData = ReadLineF[223:192];
13: ICacheMemReadData = ReadLineF[239:208];
14: ICacheMemReadData = ReadLineF[255:224];
15: ICacheMemReadData = {16'b0, ReadLineF[255:240]};
endcase
end
ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*);
// For now, assume no writes to executable memory
assign FlushMem = 1'b0;
endmodule

32
wally-pipelined/src/dmem/dmem.sv
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@ -53,14 +53,30 @@ module dmem (
output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM,
output logic StoreMisalignedFaultM, StoreAccessFaultM, output logic StoreMisalignedFaultM, StoreAccessFaultM,
// TLB management
// mmu management
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] PageTableEntryM, input logic [`XLEN-1:0] PageTableEntryM,
input logic [1:0] PageTypeM, input logic [1:0] PageTypeM,
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM, input logic STATUS_MXR, STATUS_SUM,
input logic DTLBWriteM, DTLBFlushM, input logic DTLBWriteM, DTLBFlushM,
output logic DTLBMissM, DTLBHitM output logic DTLBMissM, DTLBHitM,
// PMA/PMP (inside mmu) signals
input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
input logic [2:0] HSIZE, HBURST,
input logic HWRITE,
input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
output logic DSquashBusAccessM,
output logic [5:0] DHSELRegionsM
); );
logic SquashSCM; logic SquashSCM;
@ -74,12 +90,18 @@ module dmem (
localparam STATE_FETCH_AMO = 2; localparam STATE_FETCH_AMO = 2;
localparam STATE_STALLED = 3; localparam STATE_STALLED = 3;
tlb #(.ENTRY_BITS(3), .ITLB(0)) dtlb(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
.PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM), .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM),
.TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),
.*);
.ExecuteAccessF(1'b0),
.SquashBusAccess(DSquashBusAccessM), .HSELRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
// Specify which type of page fault is occurring // Specify which type of page fault is occurring
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWM[1]; assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWM[1];
@ -164,7 +186,5 @@ module dmem (
endcase // case (CurrState) endcase // case (CurrState)
end end
endmodule endmodule

4
wally-pipelined/src/ebu/ahblite.sv
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@ -58,7 +58,7 @@ module ahblite (
output logic [`XLEN-1:0] MMUReadPTE, output logic [`XLEN-1:0] MMUReadPTE,
output logic MMUReady, output logic MMUReady,
// Signals from PMA checker // Signals from PMA checker
input logic SquashBusAccess, input logic DSquashBusAccessM, ISquashBusAccessF,
// Signals to PMA checker (metadata of proposed access) // Signals to PMA checker (metadata of proposed access)
output logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, output logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
// Return from bus // Return from bus
@ -147,7 +147,7 @@ module ahblite (
(ProposedNextBusState == MMUTRANSLATE); (ProposedNextBusState == MMUTRANSLATE);
// The PMA and PMP checkers can decide to squash the access // The PMA and PMP checkers can decide to squash the access
assign NextBusState = (SquashBusAccess) ? IDLE : ProposedNextBusState; assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState;
// stall signals // stall signals
// Note that we need to extend both stalls when MMUTRANSLATE goes to idle, // Note that we need to extend both stalls when MMUTRANSLATE goes to idle,

206
wally-pipelined/src/fpu/FMA/fma1.sv
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@ -1,103 +1,137 @@
//////////////////////////////////////////////////////////////////////////////// module fma1(
// Block Name: fmac.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This is the top level block of a floating-point multiply/accumulate
// unit(FMAC). It instantiates the following sub-blocks:
//
// array Booth encoding, partial product generation, product summation
// expgen Exponent summation, compare, and adjust
// align Alignment shifter
// add Carry-save adder for accumulate, carry propagate adder
// lza Leading zero anticipator to control normalization shifter
// normalize Normalization shifter
// round Rounding of result
// exception Handles exceptional cases
// bypass Handles bypass of result to ReadData1E or ReadData3E inputs
// sign One bit sign handling block
// special Catch special cases (inputs = 0 / infinity / etc.)
//
// The FMAC computes FmaResultM=ReadData1E*ReadData2E+ReadData3E, rounded with the mode specified by
// RN, RZ, RM, or RP. The result is optionally bypassed back to
// the ReadData1E or ReadData3E inputs for use on the next cycle. In addition, four signals
// are produced: trap, overflow, underflow, and inexact. Trap indicates
// an infinity, NaN, or denormalized number to be handled in software;
// the other three signals are IEEE flags.
//
/////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////// input logic [63:0] ReadData1E,
module fma1(ReadData1E, ReadData2E, ReadData3E, FrmE, input logic [63:0] ReadData2E,
rE, sE, tE, bsE, killprodE, sumshiftE, sumshiftzeroE, aligncntE, aeE input logic [63:0] ReadData3E,
, xzeroE, yzeroE, zzeroE, xnanE,ynanE, znanE, xdenormE, ydenormE, zdenormE, output logic [105:0] ProdManE,
xinfE, yinfE, zinfE, nanE, prodinfE); output logic [161:0] AlignedAddendE,
///////////////////////////////////////////////////////////////////////////// output logic [12:0] ProdExpE,
output logic AddendStickyE,
output logic KillProdE,
output logic XZeroE, YZeroE, ZZeroE,
output logic XInfE, YInfE, ZInfE,
output logic XNaNE, YNaNE, ZNaNE);
input logic [63:0] ReadData1E; // input 1 logic [51:0] XMan,YMan,ZMan;
input logic [63:0] ReadData2E; // input 2 logic [10:0] XExp,YExp,ZExp;
input logic [63:0] ReadData3E; // input 3 logic XSgn,YSgn,ZSgn;
input logic [2:0] FrmE; // Rounding mode logic [12:0] AlignCnt;
output logic [12:0] aligncntE; // status flags logic [211:0] Shift;
output logic [105:0] rE; // one result of partial product sum logic XDenormE, YDenormE, ZDenormE;
output logic [105:0] sE; // other result of partial products
output logic [163:0] tE; // output logic of alignment shifter
output logic [12:0] aeE; // multiplier expoent
output logic bsE; // sticky bit of addend
output logic killprodE; // ReadData3E >> product
output logic xzeroE;
output logic yzeroE;
output logic zzeroE;
output logic xdenormE;
output logic ydenormE;
output logic zdenormE;
output logic xinfE;
output logic yinfE;
output logic zinfE;
output logic xnanE;
output logic ynanE;
output logic znanE;
output logic nanE;
output logic prodinfE;
output logic [8:0] sumshiftE;
output logic sumshiftzeroE;
// Internal nodes
// output logic [12:0] aligncntE; // shift count for alignment
logic prodof; // ReadData1E*ReadData2E out of range // split inputs into the sign bit, mantissa, and exponent for readability
assign XSgn = ReadData1E[63];
assign YSgn = ReadData2E[63];
assign ZSgn = ReadData3E[63];
assign XExp = ReadData1E[62:52];
assign YExp = ReadData2E[62:52];
assign ZExp = ReadData3E[62:52];
assign XMan = ReadData1E[51:0];
assign YMan = ReadData2E[51:0];
assign ZMan = ReadData3E[51:0];
// determine if an input is a special value
assign XNaNE = &ReadData1E[62:52] && |ReadData1E[51:0];
assign YNaNE = &ReadData2E[62:52] && |ReadData2E[51:0];
assign ZNaNE = &ReadData3E[62:52] && |ReadData3E[51:0];
assign XDenormE = ~(|ReadData1E[62:52]) && |ReadData1E[51:0];
assign YDenormE = ~(|ReadData2E[62:52]) && |ReadData2E[51:0];
assign ZDenormE = ~(|ReadData3E[62:52]) && |ReadData3E[51:0];
assign XInfE = &ReadData1E[62:52] && ~(|ReadData1E[51:0]);
assign YInfE = &ReadData2E[62:52] && ~(|ReadData2E[51:0]);
assign ZInfE = &ReadData3E[62:52] && ~(|ReadData3E[51:0]);
assign XZeroE = ~(|ReadData1E[62:0]);
assign YZeroE = ~(|ReadData2E[62:0]);
assign ZZeroE = ~(|ReadData3E[62:0]);
// Calculate the product's exponent
// - When multipliying two fp numbers, add the exponents
// - Subtract 3ff to remove one of the biases (XExp + YExp has two biases, one from each exponent)
// - Denormal numbers have an an exponent value of 1, however they are
// represented with an exponent of 0. add one if there is a denormal number
assign ProdExpE = (XZeroE|YZeroE) ? 13'b0 :
{2'b0, XExp} + {2'b0, YExp} - 13'h3ff + XDenormE + YDenormE;
// Calculate the product's mantissa
// - Add the assumed one. If the number is denormalized or zero, it does not have an assumed one.
assign ProdManE = {53'b0,~(XDenormE|XZeroE),XMan} * {53'b0,~(YDenormE|YZeroE),YMan};
// determine the shift count for alignment
// - negitive means Z is larger, so shift Z left
// - positive means the product is larger, so shift Z right
// - Denormal numbers have an an exponent value of 1, however they are
// represented with an exponent of 0. add one to the exponent if it is a denormal number
assign AlignCnt = ProdExpE - ZExp - ZDenormE;
// Alignment shifter
// Defualt Addition without shifting
// | 55'b0 | 106'b(product) | 2'b0 |
// |1'b0| addnend |
// the 1'b0 before the added is because the product's mantissa has two bits before the decimal point (xx.xxxxxxxxxx...)
always_comb
begin
// Set default values
AddendStickyE = 0;
KillProdE = 0;
// If the product is too small to effect the sum, kill the product
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
if ($signed(AlignCnt) <= $signed(-56)) begin
KillProdE = 1;
AlignedAddendE = {55'b0, ~(ZZeroE|ZDenormE),ZMan,2'b0};
AddendStickyE = ~(XZeroE|YZeroE);
// If the Addend is shifted left (negitive AlignCnt)
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else if($signed(AlignCnt) <= $signed(0)) begin
Shift = {55'b0, ~(ZZeroE|ZDenormE),ZMan, 104'b0} << -AlignCnt;
AlignedAddendE = Shift[211:50];
AddendStickyE = |(Shift[49:0]);
// If the Addend is shifted right (positive AlignCnt)
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else if ($signed(AlignCnt)<=$signed(105)) begin
Shift = {55'b0, ~(ZZeroE|ZDenormE),ZMan, 104'b0} >> AlignCnt;
AlignedAddendE = Shift[211:50];
AddendStickyE = |(Shift[49:0]);
// If the addend is too small to effect the addition
// - The addend has to shift two past the end of the addend to be considered too small
// - The 2 extra bits are needed for rounding
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else begin
AlignedAddendE = 162'b0;
AddendStickyE = ~ZZeroE;
end
end
// Instantiate fraction datapath
multiply multiply(.xman(ReadData1E[51:0]), .yman(ReadData2E[51:0]), .*);
align align(.zman(ReadData3E[51:0]),.*);
// Instantiate exponent datapath
expgen1 expgen1(.xexp(ReadData1E[62:52]),.yexp(ReadData2E[62:52]),.zexp(ReadData3E[62:52]),.*);
// Instantiate special case detection across datapath & exponent path
special special(.*);
// Instantiate control output logic
flag1 flag1(.*);
endmodule endmodule

357
wally-pipelined/src/fpu/FMA/fma2.sv
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@ -1,104 +1,107 @@
//////////////////////////////////////////////////////////////////////////////// module fma2(
// Block Name: fmac.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This is the top level block of a floating-point multiply/accumulate
// unit(FMAC). It instantiates the following sub-blocks:
//
// array Booth encoding, partial product generation, product summation
// expgen Mxponent summation, compare, and adjust
// align Alignment shifter
// add Carry-save adder for accumulate, carry propagate adder
// lza Leading zero anticipator to control normalization shifter
// normalize Normalization shifter
// round Rounding of result
// exception Handles exceptional cases
// bypass Handles bypass of result to ReadData1M or ReadData3M input logics
// sign One bit sign handling block
// special Catch special cases (input logics = 0 / infinity / etc.)
//
// The FMAC computes FmaResultM=ReadData1M*ReadData2M+ReadData3M, rounded with the mode specified by
// RN, RZ, RM, or RP. The result is optionally bypassed back to
// the ReadData1M or ReadData3M input logics for use on the next cycle. In addition, four signals
// are produced: trap, overflow, underflow, and inexact. Trap indicates
// an infinity, NaN, or denormalized number to be handled in software;
// the other three signals are IMMM flags.
//
/////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////// input logic [63:0] ReadData1M,
module fma2(ReadData1M, ReadData2M, ReadData3M, FrmM, input logic [63:0] ReadData2M,
FmaResultM, FmaFlagsM, aligncntM, rM, sM, input logic [63:0] ReadData3M,
tM, normcntM, aeM, bsM,killprodM, input logic [2:0] FrmM,
xzeroM, yzeroM,zzeroM,xdenormM,ydenormM, input logic [105:0] ProdManM,
zdenormM,xinfM,yinfM,zinfM,xnanM,ynanM,znanM, input logic [161:0] AlignedAddendM,
nanM,sumshiftM,sumshiftzeroM,prodinfM input logic [12:0] ProdExpM,
input logic AddendStickyM,
); input logic KillProdM,
///////////////////////////////////////////////////////////////////////////// input logic [3:0] FOpCtrlM,
input logic XZeroM, YZeroM, ZZeroM,
input logic [63:0] ReadData1M; // input logic 1 input logic XInfM, YInfM, ZInfM,
input logic [63:0] ReadData2M; // input logic 2 input logic XNaNM, YNaNM, ZNaNM,
input logic [63:0] ReadData3M; // input logic 3 output logic [63:0] FmaResultM,
input logic [2:0] FrmM; // Rounding mode output logic [4:0] FmaFlagsM);
input logic [12:0] aligncntM; // status flags
input logic [105:0] rM; // one result of partial product sum
input logic [105:0] sM; // other result of partial products
input logic [163:0] tM; // output of alignment shifter
input logic [8:0] normcntM; // shift count for normalizer
input logic [12:0] aeM; // multiplier expoent
input logic bsM; // sticky bit of addend
input logic killprodM; // ReadData3M >> product
input logic prodinfM;
input logic xzeroM;
input logic yzeroM;
input logic zzeroM;
input logic xdenormM;
input logic ydenormM;
input logic zdenormM;
input logic xinfM;
input logic yinfM;
input logic zinfM;
input logic xnanM;
input logic ynanM;
input logic znanM;
input logic nanM;
input logic [8:0] sumshiftM;
input logic sumshiftzeroM;
output logic [63:0] FmaResultM; // output FmaResultM=ReadData1M*ReadData2M+ReadData3M
output logic [4:0] FmaFlagsM; // status flags logic [51:0] XMan, YMan, ZMan, WMan;
logic [10:0] XExp, YExp, ZExp, WExp;
logic XSgn, YSgn, ZSgn, WSgn, PSgn;
logic IsSub;
logic [105:0] ProdMan2;
logic [162:0] AlignedAddend2;
logic [161:0] Sum;
logic [162:0] SumTmp;
logic [12:0] SumExp;
logic [12:0] SumExpMinus1;
logic [12:0] SumExpTmp, WExpTmp;
logic [53:0] NormSum;
logic [161:0] NormSumTmp;
logic [8:0] NormCnt;
logic NormSumSticky;
logic SumZero;
logic NegSum;
logic InvZ;
logic ResultDenorm;
logic Sticky;
logic Plus1, Minus1, Plus1Tmp, Minus1Tmp;
logic Invalid,Underflow,Overflow,Inexact;
logic [8:0] DenormShift;
logic ProdInf, ProdOf, ProdUf;
logic [63:0] FmaResultTmp;
logic SubBySmallNum;
// Internal nodes // split inputs into the sign bit, mantissa, and exponent for readability
logic [163:0] sum; // output of carry prop adder assign XSgn = ReadData1M[63];
logic [53:0] v; // normalized sum, R, S bits assign YSgn = ReadData2M[63];
// logic [12:0] aligncnt; // shift count for alignment assign ZSgn = ReadData3M[63];
logic [8:0] normcnt; // shift count for normalizer
logic negsum; // negate sum
logic invz; // invert addend
logic selsum1; // select +1 mode of sum
logic negsum0; // sum +0 < 0
logic negsum1; // sum +1 < 0
logic sumzero; // sum = 0
logic infinity; // generate infinity on overflow
logic sumof; // result out of range
logic zexpsel;
logic denorm0;
logic resultdenorm;
logic inf;
logic specialsel;
logic expplus1;
logic sumuf;
logic psign;
logic sticky;
logic [12:0] de0;
logic isAdd;
assign isAdd = 1; assign XExp = ReadData1M[62:52];
assign YExp = ReadData2M[62:52];
assign ZExp = ReadData3M[62:52];
assign XMan = ReadData1M[51:0];
assign YMan = ReadData2M[51:0];
assign ZMan = ReadData3M[51:0];
// is it an FMSUB or FNMSUB instruction
assign IsSub = FOpCtrlM[0];
// Addition
// Negate Z when doing one of the following opperations:
// -prod + Z
// prod - Z
assign InvZ = IsSub ? ~(ZSgn ^ PSgn) : (ZSgn ^ PSgn);
// Choose an inverted or non-inverted addend - the one is added later
assign AlignedAddend2 = InvZ ? ~{2'b0,AlignedAddendM} : {2'b0,AlignedAddendM};
// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
assign ProdMan2 = KillProdM ? 106'b0 : ProdManM;
// Do the addition
// - add one to negate if the added was inverted
// - the 2 extra bits at the begining and end are needed for rounding
assign SumTmp = AlignedAddend2 + {55'b0, ProdMan2,2'b0} + InvZ;
// Is the sum negitive
assign NegSum = SumTmp[162];
// If the sum is negitive, negate the sum.
assign Sum = NegSum ? -SumTmp[161:0] : SumTmp[161:0];
// Leading one detector
logic [8:0] i;
always_comb begin
i = 0;
while (~Sum[161-i] && $unsigned(i) <= $unsigned(9'd161)) i = i+1; // search for leading one
NormCnt = i+1; // compute shift count
end
@ -110,25 +113,163 @@ module fma2(ReadData1M, ReadData2M, ReadData3M, FrmM,
// Normalization
// Determine if the sum is zero
assign SumZero = ~(|Sum);
// Determine if the result is denormal
assign ResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp+13'd52)>=0);
// Determine the shift needed for denormal results
assign DenormShift = ResultDenorm ? SumExpTmp-1 : 6'b0;
// Normalize the sum
assign NormSumTmp = SumZero ? 162'b0 : Sum << NormCnt+DenormShift;
assign NormSum = NormSumTmp[161:108];
// Calculate the sticky bit
assign NormSumSticky = (|NormSumTmp[107:0]);
assign Sticky = AddendStickyM | NormSumSticky;
// Determine sum's exponent
assign SumExpTmp = KillProdM ? ZExp : ProdExpM + -({5'b0, NormCnt} - 13'd56);
assign SumExp = SumZero ? 12'b0 :
ResultDenorm ? 12'b0 :
SumExpTmp;
// Instantiate fraction datapath
add add(.*);
lza lza(.*);
normalize normalize(.zexp(ReadData3M[62:52]),.*);
round round(.xman(ReadData1M[51:0]), .yman(ReadData2M[51:0]),.zman(ReadData3M[51:0]), .wman(FmaResultM[51:0]),.wsign(FmaResultM[63]),.*);
// Instantiate exponent datapath
expgen2 expgen2(.xexp(ReadData1M[62:52]),.yexp(ReadData2M[62:52]),.zexp(ReadData3M[62:52]),.wexp(FmaResultM[62:52]),.*);
// Instantiate control logic
sign sign(.xsign(ReadData1M[63]),.ysign(ReadData2M[63]),.zsign(ReadData3M[63]),.wsign(FmaResultM[63]),.*);
flag2 flag2(.xsign(ReadData1M[63]),.ysign(ReadData2M[63]),.zsign(ReadData3M[63]),.vbits(v[1:0]),.*);
// Rounding
// round to nearest even
// {NormSum[1], NormSum[0], Sticky}
// 0xx - do nothing
// 100 - tie - Plus1 if NormSum[2] = 1
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// 101/110/111 - Plus1
// round to zero - do nothing
// - subtract 1 if a small number was supposed to be subtracted from the positive result
// round to -infinity - Plus1 if negitive
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// - subtract 1 if a small number was supposed to be subtracted from the positive result
// round to infinity - Plus1 if positive
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// - subtract 1 if a small number was supposed to be subtracted from the negitive result
// round to nearest max magnitude
// {NormSum[1], NormSum[0], Sticky}
// 0xx - do nothing
// 100 - tie - Plus1
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// 101/110/111 - Plus1
// Deterimine if the result was supposed to be subtrated by a small number
assign SubBySmallNum = AddendStickyM&InvZ&~NormSumSticky;
always_comb begin
// Determine if you add 1
case (FrmM)
3'b000: Plus1Tmp = NormSum[1] & (NormSum[0] | (Sticky&~(~NormSum[0]&SubBySmallNum)) | (~NormSum[0]&~Sticky&NormSum[2]));//round to nearest even
3'b001: Plus1Tmp = 0;//round to zero
3'b010: Plus1Tmp = WSgn & ~(SubBySmallNum);//round down
3'b011: Plus1Tmp = ~WSgn & ~(SubBySmallNum);//round up
3'b100: Plus1Tmp = (NormSum[1] & (NormSum[0] | (Sticky&~(~NormSum[0]&SubBySmallNum)) | (~NormSum[0]&~Sticky)));//round to nearest max magnitude
default: Plus1Tmp = 1'bx;
endcase
// Determine if you subtract 1
case (FrmM)
3'b000: Minus1Tmp = 0;//round to nearest even
3'b001: Minus1Tmp = SubBySmallNum;//round to zero
3'b010: Minus1Tmp = ~WSgn & SubBySmallNum;//round down
3'b011: Minus1Tmp = WSgn & SubBySmallNum;//round up
3'b100: Minus1Tmp = 0;//round to nearest max magnitude
default: Minus1Tmp = 1'bx;
endcase
end
// If an answer is exact don't round
assign Plus1 = Sticky | (|NormSum[1:0]) ? Plus1Tmp : 0;
assign Minus1 = Sticky | (|NormSum[1:0]) ? Minus1Tmp : 0;
// Compute rounded result
assign {WExpTmp, WMan} = {SumExp, NormSum[53:2]} + Plus1 - Minus1;
assign WExp = WExpTmp[10:0];
// Sign calculation
// Calculate the product's sign
assign PSgn = XSgn ^ YSgn;
// Determine the sign if the sum is zero
// if product underflows then use psign
// otherwise
// if cancelation then 0 unless round to -inf
// otherwise psign
assign zerosign = Underflow ? PSgn :
(IsSub ? (PSgn^ZSgn ? PSgn : FrmM == 3'b010) :
(PSgn^ZSgn ? FrmM == 3'b010 : PSgn));
// is the result negitive
// if p - z is the Sum negitive
// if -p + z is the Sum positive
// if -p - z then the Sum is negitive
assign resultsgn = InvZ&ZSgn&NegSum | InvZ&PSgn&~NegSum | (ZSgn&PSgn);
assign WSgn = SumZero ? zerosign : resultsgn;
// Select the result
assign FmaResultTmp = XNaNM ? {XSgn, XExp, 1'b1,XMan[50:0]} :
YNaNM ? {YSgn, YExp, 1'b1,YMan[50:0]} :
ZNaNM ? {ZSgn, ZExp, 1'b1,ZMan[50:0]} :
Invalid ? {WSgn, 11'h7ff, 1'b1, 51'b0} : // has to be before inf
XInfM ? {PSgn, XExp, XMan} :
YInfM ? {PSgn, YExp, YMan} :
ZInfM ? {ZSgn^IsSub, ZExp, ZMan} :
Overflow ? {WSgn, 11'h7ff, 52'b0} :
Underflow ? {WSgn, 63'b0} :
KillProdM ? ReadData3M - (Minus1&AddendStickyM) + (Plus1&AddendStickyM): // has to be after Underflow
{WSgn,WExp,WMan};
// Negate the result if FNMADD or FNSUB instruction
assign FmaResultM[63] = FOpCtrlM[1] ? ~FmaResultTmp[63] : FmaResultTmp[63];
assign FmaResultM[62:0] = FmaResultTmp[62:0];
// Set Invalid flag for following cases:
// 1) Inf - Inf
// 2) 0 * Inf
// 3) any input is a signaling NaN
assign ProdOf = (ProdExpM >= 2047 && ~ProdExpM[12]);
assign ProdInf = ProdOf && ~XNaNM && ~YNaNM;
assign Invalid = (XNaNM&~XMan[51]) | (YNaNM&~YMan[51]) | (ZNaNM&~ZMan[51]) | ((XInfM || YInfM || ProdInf) & ZInfM & (XSgn ^ YSgn ^ ZSgn)) | (XZeroM & YInfM) | (YZeroM & XInfM);
// Set Overflow flag if the number is too big to be represented
assign Overflow = WExpTmp >= 2047 & ~WExpTmp[12];
// Set Underflow flag if the number is too small to be represented and isn't denormalized
assign ProdUf = KillProdM & ZZeroM;
assign Underflow = (WExpTmp[12] & ~ResultDenorm) | ProdUf;
// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
assign Inexact = Sticky|Overflow|Underflow | (|NormSum[1:0]);
// Combine flags - FMA can't set the Divide by zero flag
assign FmaFlagsM = {Invalid, 1'b0, Overflow, Underflow, Inexact};
endmodule endmodule

171
wally-pipelined/src/fpu/FMA/tbgen/results.dat
View File

@ -1 +1,170 @@
c3f000200003fffe 0000000000000001 001ffffffffffffe 80cffc400007fffd 80cffc400007fffc Wrong FmaResultM= -64 ydenorm 1119653 cce008007fffffff 7fe6e0fac3dc6e26 401ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 28027
c03fffffffffc800 7fdfffffffffe000 37f07ffffffffffc fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 44043
c7f000ffffffffef 7fefffffffffde00 4e1ffffffffffe7f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 107106
c7f00000dffffffe 7fe0000000000000 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 238237
ffdf0000001fffff 7feffffffffffffe 7fe0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 310309
c79ff80003fffffe 7feffc0000003ffe 2bd0020000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 426425
ffeffffeffc00000 3fffffffffffffff 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 436435
d16ff800007fffff 7fe0000000000000 c000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 517516
d10ffffffff3fffe 7feffffffffffffe b9d07f0000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 519518
442ff9fffffffffe ffefffffffffffff 3ff0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 553552
c34f24b48d2af3e7 7fef7fe000000000 800ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 577576
7fdfffffff8000ff c3f0100000000002 39300dfffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 593592
ffe00007fffffdfe 4340000000000001 ffd34131592163f6 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 654653
4b98eba3e512fb7b ffe84639040d967a 42c00000010001fe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 683682
ffed83a6b2e656b1 7fe0000000000001 0010000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 796795
7fd5220b51609cf6 c030000000001020 7fdfbfffffffffdf fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 903902
c3d6eb6dede43198 7feffffffffffffe 3a6008000000000f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1078076
c1f02000001fffff 7fe0000000000001 e8f000000040000f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1285283
c1cdfffbffffffff 7fe0000000000001 bca0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1355353
43447336acaf7bd8 ffeffffffffffffe 0010000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1391389
4010000000fff7ff ffe0000000000000 7fdfffc000003ffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1528526
ffe0000002000003 47fffc00000007ff 93b0040000002000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1597595
4060000200000400 ffe0000000000000 7fe0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1598596
fe7007fffdffffff 7fdffffffffff03e 001ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1631629
4000000000000000 ffe0000000000001 3fdffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1738736
4000000000000000 ffeffffffffffffe 4263dd4adb450db9 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1740738
40200001ffc00000 ffe0000000000000 3fdfcfffffffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1807805
400ffffffffffffe ffd00013fffffffe 40200000100001ff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1941939
400ffffffffffffe ffe0000000000001 c00fffe003ffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 1947945
7fe00000080000fe bfffffffffffffff 3fd002000000003f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2006003
4010000000000000 ffe0000000000001 7feffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2018015
4010000000000000 ffeffffffffffffe bf7ffffffff80001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2020017
43ffffd000000000 ffe0000000000000 613ffffffffffe1e fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2087084
c1fb6efe117a3ae3 7fefffffffffffff 43c0000001effffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2123120
ffdfffffc0000000 7fe0000002002000 3fffffffffbfff80 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2147144
401ffffffffffffe ffe0000000000001 7c300040000000ff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2227224
4340000000000000 ffe0000000000001 bfeffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2297294
c0f0000000203fff 7fefffffffffffff c921fffffffffefe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2402399
7fedffffffdfffff c7f0400000000008 401ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2406403
434fffffffffffff ffd0000008fffffe c03fffffffffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2419416
41dfffffffe00003 ffe0000000000001 3ff0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2436433
c1f0000000037fff 7fdffffffff7ffc0 3fdffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2451448
ffebfffffffffbff 4010000000000001 bf20001fffffffe0 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2465462
ffe000020001ffff 7fdfdffff7ffffff 41d000083fffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2471468
434ffffffffffffe ffe0000000000001 bf1fffffc00003ff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2506503
7fe0000000000000 c1c0000001ffffbf 0000000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 2538535
7fe0000000000000 c1d264933e9e988c 3ca0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2565562
7fe0000000000000 c00fffffffffffff bcaffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2567564
7fe0000000000000 c010000000000001 403400003fffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2569566
7fe0000000000001 c3d0bfffffffffff a9817e19c25e6ffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2590587
7fe0000000000001 c1c01feffffffffe 3fe0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2592589
7fe0000000000001 f860000ffbfffffe 4000000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2619616
7fe0000000000001 c1e29f751d0db106 41dff88000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2626623
7fe0000000000001 c010000000000001 800ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 2639636
7fe0000000000001 c340000000000000 41e9bfbd1705ab74 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2641638
7fe0000000000001 c1ffffc0007fffff c0e00000003f8000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2644641
7fefffffffffffff c3cfff000003ffff c01fffffefbfffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2653650
c00000ffc0000000 7fefffffffff81ff 00199d0888644678 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2660657
7fefffffffffffff c01fffe00000003e 3cdedfffffffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2671668
7fefffffffffffff c7e00800ffffffff c010000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2682679
7fefffffffffffff c3f50270323fdbca 3fe0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2691688
7fefffffffffffff c06f000000000006 8010000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2700697
7fefffffffffffff bff0000000000001 001ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2702699
7fefffffffffffff bffffffffffffffe 47edd848c981ea6a fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2704701
7fefffffffffffff d6f0007fbfffffff 380ff8000000001f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2707704
7fefffffffffffff c167c6ca402625fe ffe0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2709706
7fefffffffffffff c340000000000000 7feffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2711708
7fefffffffffffff c34fffffffffffff c1a3cdb48240da83 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2713710
7feffffffffffffe c01580f1a3e9c31d 3d258f8ba280bed4 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2725722
7feffffffffffffe ffd800001fffffff bfd0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2727724
7feffffffffffffe c27a98a4d75fad64 0000000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 2736733
c01ffffffe03ffff 7fd00000000c0000 c00ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2739736
7feffffffffffffe c3f01ffffff00000 4340000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2745742
7feffffffffffffe c0550d69ccececd4 403ffffff83fffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2761758
7feffffffffffffe c00fffffffffffff b81080ffffffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2776773
7feffffffffffffe c0020ec4bd7f8123 403894684b0415af fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2779776
7feffffffffffffe c34ffffffffffffe 401ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2783780
7feffffffffffffe ffe0000000000001 43c0000000000bfe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2785782
7feffffffffffffe c1f000000003ff7f 40017ffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2788785
bf9ffffffd800000 7fefffffffffffff ffefffffffbfffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2960957
e8d01e2c59865900 7fe05fffffffffff c34ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 2964961
ffd917679344f70e 401fffffffffffff c000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3094090
4470000023ffffff ffe0000000000001 b802000001ffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3204200
43627f4abb7a5c8e ffefffffffffffff 0010000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3274270
c1c0000820000000 7feffffffff8001f 402000100000007f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3332328
c1cd41643238b450 7feffffffffffffe 3f4012189596a55a fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3519515
c80ea7921c438451 7fe008000000007e 424153696dc450d3 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3552548
4f000fffffffffff ffefffffffffffff 4010000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3553549
7fe1868cfb076bc1 c34000000000037f b7effffc003ffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3719715
c3fff9fffffffffe 7fe0000000000000 3d6000008000000e fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3726722
43f007ffbfffffff ffefffffffffffff 43dffffeffffffbf fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3762758
7fdfffdfffffffbe c01fffffffffffff 3fd0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 3895891
ffeefffffffffff7 43e0003ffffeffff b7f000001fdfffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4125120
4800002000000007 ffe0000000000000 3ff0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4319314
43f856a5096bfc0d ffeffffffffffffe 3fd0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4391386
c009c2b9147e606c 7fe0000002007fff bfa004001ffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4440435
4030008000003fff ffe0000000000000 b810eaddea941d3f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4528523
67affffff8000006 f3016e70e2a6bd2f c1edddf29e459b21 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4548543
ffe07ffbffffffff 5026589203bb88d1 401ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4586581
43dffffc00000003 ffe0000000000000 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4598593
ffdfffffff800003 4010000000000001 c290000080000002 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4627622
ffd001fffffffbff 4010000000000001 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4697692
bffffffffffffffe 7fefffffffffffff 3d30040000200000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4704699
c000000000000000 7fefffffffffffff bfeffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4774769
c000000000000000 7fe9d625d7f2ee96 380ffeffffffc000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4797792
41efffffbfffdfff ffe0000000000000 bbf0000003f80000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4807802
fcf00000000003e0 7fdfffffffc02000 bfeffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4892887
c00ffffffffffffe 7fe0000000000000 001ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4981976
c00ffffffffffffe 7fefffffffffffff 4020e8f734a930e7 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 4983978
ffeffffc01fffffe 43d0000000000000 3806864c983757ae fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5030024
41b0000000010007 ffe0000000000001 0010000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5157151
c3e413dc0ee29162 7fefffffffffffff 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5193187
c01ffffffffffffe 7fe0000000000000 401ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5261255
c01ffffffffffffe 7fefffffffffffff c1c177d35a8a07ad fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5263257
c340000000000000 7feffffffffffffe 3ffffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5333327
c34ff0000003fffe 7fefffffffffffff c0101442690e84e3 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5402396
c340000000000001 7fe41774eee28bfa 37efffff000000ff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5437431
c34fffffffffffff 7fe0000000000000 4010008001fffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5470464
c34ffffffffffffe 7fe0000000000000 bcaffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5540534
c34ffffffffffffe 7feffffffffffffe c7e6b68e99fe64db fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5542536
ffe0000000000000 41effffff7fffffe 2a7000207fffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5590584
ffe0000000000000 40b00000000008ff 4013ac1788ee2681 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5599593
ffe0000000000000 4010000000000000 3fdffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5603597
ffe0000000000000 401fffffffffffff 0012000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5605599
ffe0000000000000 45e00007fff7ffff 9c80852a49e348a6 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5608602
ffe0000000000000 41e6d2bd893fa49f 0000000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5610604
ffe0000000000000 7feffffffffffffe 800ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5612606
ffe0000000000000 4804ecddd4dee74f 9700000101fffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5617611
ffe0000000000000 47e0400000000100 4340000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5619613
ffe0000000000000 41d0000000001fff 800007ffffffdfff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5626620
ffe0000000000001 4c7ffffffff87fff 3fbfdffffffffff7 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5662656
ffe0000000000001 401ffffffffffffe 001ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5675669
ffe0000000000001 4340000000000001 48700003fffefffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5677671
ffe0000000000001 4000f2f5230ef1a6 382efffffeffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5689683
ffe0000000000001 407b2a20706ca02f bcc8eea3de85c218 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5707701
41efdffffffbfffe ffe0000000000001 bca0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5715709
ffe0000000000001 43e000000000ffff 4340000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5718712
ffedffffffff7fff 7f500000001fffff 469cefa7e05db8e7 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5728722
ffefffffffffffff 3fffffffffffffff bcaffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5738732
ffefffffffffffff 4000000000000001 800ffffffdffe000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5740734
ffefffffffffffff 7fe0000000000000 3fdffffffffffe1f fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5749743
ffd44208deea7d5b 7fdffffcffffffff caf0000000007fff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5764758
ffefffffffffffff 43cffff6ffffffff 47ffba85ed27c05e fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5779773
ffeffffffffffffe 40b0000fffffffc0 bfd0000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5799793
ffeffffffffffffe 43ea49f9e3cf97b4 0000000000000001 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5808802
ffeffffffffffffe 4000000000000001 800ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z zdenorm ovrflw FmaResultM=-inf 5810804
ffeffffffffffffe 4010000000000000 bc800001ffffffe0 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5812806
ffeffffffffffffe 7fe0000000000000 c34ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5819813
ffeffffffffffffe 7feffffffffffffe c1efff801fffffff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5821815
ffdfffffc0007ffe 4340000000000001 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5886880
c4a000001ffeffff 7fe0000000000000 b80fc03ffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5888882
ffdfffff00000040 48f00001bfffffff c00ffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5910904
c37ffffffffffbf0 7fd1800000000000 bfa7e7cad560a3d0 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 5912906
c1700000000007f7 7feffffffffffffe 3f6ff7ffffffefff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6240233
c3fffffffdfe0000 7fe0000000000000 c34fff6000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6447440
400ffffdfffff7fe ffefffffffffffff 41de000000007ffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6483476
4030000000004020 ffe88b9c477c3a97 ffe007ffff000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6575568
7fe00807ffffffff c1e0000000007fe0 bfeffffffffffffe fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6676669
ffdfc00000000800 7fe0000000000000 bcffffffffffefef fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6726719
7feffffeffffbfff c34ffffffffffffe c000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6760753
42bff00000000010 ffefffffffffffff c3003a94038a1ec3 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6762755
c3c00ffffffffeff 7feddda224891f86 43d0aa9335103e61 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6782775
c08ff80000000400 7fe0000000000001 3ff0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6796789
c07fffdfffffffbe 7feffffffffffffe 474ffffffdffff80 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6798791
c01fffffeffff7ff 7fd0080080000000 bff26df7cf61cdd5 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6827820
c7effff000000004 7fe0000008000fff 4770000007ffbfff fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 6863856
7fe85e6f4033d7dd c000000000000000 bfe0000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 7031023
c1f732bc454b0563 7fe0000000000001 8000000000000000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 7076068
ffe000000fffffbe 401ffffffffffffe b80d2116944eef72 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 7141133
ffd0002000001fff 40e00003ffffefff c03fffffffe80000 fff0000000000000 ffefffffffffffff Wrong FmaResultM= z ovrflw FmaResultM=-inf 7242234

BIN
wally-pipelined/src/fpu/FMA/tbgen/tb
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Binary file not shown.

6
wally-pipelined/src/fpu/FMA/tbgen/tb.c
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@ -26,13 +26,13 @@ void main() {
char ans[81]; char ans[81];
char flags[3]; char flags[3];
int FrmE; int FrmE;
long stop = 1119653; long stop = 5587581;
int debug = 1; int debug = 0;
//my_string = (char *) malloc (nbytes + 1); //my_string = (char *) malloc (nbytes + 1);
//bytes_read = getline (&my_string, &nbytes, stdin); //bytes_read = getline (&my_string, &nbytes, stdin);
for(n=0; n < 305; n++) {//613 for 10000 for(n=0; n < 1000; n++) {//613 for 10000
if(getline(&ln,&nbytes,fp) < 0 || feof(fp)) break; if(getline(&ln,&nbytes,fp) < 0 || feof(fp)) break;
if(k == stop && debug == 1) break; if(k == stop && debug == 1) break;
k++; k++;

341671
wally-pipelined/src/fpu/FMA/tbgen/tb.v
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File diff suppressed because it is too large Load Diff

43
wally-pipelined/src/fpu/FMA/tbgen/tbhead.v
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@ -11,26 +11,25 @@ module tb;
wire [4:0] FmaFlagsM; wire [4:0] FmaFlagsM;
wire [12:0] aligncntE; // status flags wire [12:0] aligncntE; // status flags
wire [105:0] rE; // one result of partial product sum wire [105:0] ProdManE; // other result of partial products
wire [105:0] sE; // other result of partial products wire [161:0] AlignedAddendE; // wire of alignment shifter
wire [163:0] tE; // wire of alignment shifter
wire [8:0] normcntE; // shift count for normalizer wire [8:0] normcntE; // shift count for normalizer
wire [12:0] aeE; // multiplier expoent wire [12:0] ProdExpE; // multiplier expoent
wire bsE; // sticky bit of addend wire AddendStickyE; // sticky bit of addend
wire killprodE; // ReadData3E >> product wire KillProdE; // ReadData3E >> product
wire prodofE; // ReadData1E*ReadData2E out of range wire prodofE; // ReadData1E*ReadData2E out of range
wire xzeroE; wire XZeroE;
wire yzeroE; wire yzeroE;
wire zzeroE; wire zzeroE;
wire xdenormE; wire XDenormE;
wire ydenormE; wire YDenormE;
wire zdenormE; wire ZDenormE;
wire xinfE; wire XInfE;
wire yinfE; wire YInfE;
wire zinfE; wire ZInfE;
wire xnanE; wire XNaNE;
wire ynanE; wire YNaNE;
wire znanE; wire ZNaNE;
wire nanE; wire nanE;
wire [8:0] sumshiftE; wire [8:0] sumshiftE;
wire sumshiftzeroE; wire sumshiftzeroE;
@ -45,16 +44,16 @@ reg ansnan;
reg [105:0] s; // partial product 2 reg [105:0] s; // partial product 2
reg [51:0] xnorm; reg [51:0] xnorm;
reg [51:0] ynorm; reg [51:0] ynorm;
wire [3:0] FOpCtrlM;
assign FOpCtrlM = 4'b0;
localparam period = 20; localparam period = 20;
fma1 UUT1(.*); fma1 UUT1(.*);
fma2 UUT2(.ReadData1M(ReadData1E), .ReadData2M(ReadData2E), .ReadData3M(ReadData3E), .FrmM(FrmE), fma2 UUT2(.ReadData1M(ReadData1E), .ReadData2M(ReadData2E), .ReadData3M(ReadData3E), .FrmM(FrmE), .ProdManM(ProdManE),
.aligncntM(aligncntE), .rM(rE), .sM(sE), .AlignedAddendM(AlignedAddendE), .ProdExpM(ProdExpE), .AddendStickyM(AddendStickyE),.KillProdM(KillProdE),
.tM(tE), .normcntM(normcntE), .aeM(aeE), .bsM(bsE),.killprodM(killprodE), .XZeroM(XZeroE),.YZeroM(YZeroE),.ZZeroM(ZZeroE),.XInfM(XInfE),.YInfM(YInfE),.ZInfM(ZInfE),.XNaNM(XNaNE),.YNaNM(YNaNE),.ZNaNM(ZNaNE), .*);
.xzeroM(xzeroE), .yzeroM(yzeroE),.zzeroM(zzeroE),.xdenormM(xdenormE),.ydenormM(ydenormE),
.zdenormM(zdenormE),.xinfM(xinfE),.yinfM(yinfE),.zinfM(zinfE),.xnanM(xnanE),.ynanM(ynanE),.znanM(znanE),
.nanM(nanE),.sumshiftM(sumshiftE),.sumshiftzeroM(sumshiftzeroE), .prodinfM(prodinfE), .*);
initial initial

65
wally-pipelined/src/fpu/add.sv
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@ -1,65 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
//
// Block Name: add.v
// Author: David Harris
// Date: 11/12/1995
//
// Block Description:
// This block performs the addition of the product and addend. It also
// contains logic necessary to adjust the signs for effective subtracts
// and negative results.
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module add(rM, sM, tM, sum,
negsum, invz, selsum1, negsum0, negsum1, killprodM);
////////////////////////////////////////////////////////////////////////////////
input logic [105:0] rM; // partial product 1
input logic [105:0] sM; // partial product 2
input logic [163:0] tM; // aligned addend
input logic invz; // invert addend
input logic selsum1; // select +1 mode of compound adder
input logic killprodM; // z >> product
input logic negsum; // Negate sum
output logic [163:0] sum; // sum
output logic negsum0; // sum was negative in +0 mode
output logic negsum1; // sum was negative in +1 mode
// Internal nodes
wire [105:0] r2; // partial product possibly zeroed out
wire [105:0] s2; // partial product possibly zeroed out
wire [164:0] t2; // addend after inversion if necessary
wire [164:0] sum0; // sum of compound adder +0 mode
wire [164:0] sum1; // sum of compound adder +1 mode
wire [163:0] prodshifted; // sum of compound adder +1 mode
wire [164:0] tmp; // sum of compound adder +1 mode
// Invert addend if z'sM sign is diffrent from the product'sM sign
assign t2 = invz ? ~{1'b0,tM} : {1'b0,tM};
// Zero out product if Z >> product or product really should be
assign r2 = killprodM ? 106'b0 : rM;
assign s2 = killprodM ? 106'b0 : sM;
//***replace this with a more structural cpa that synthisises better
// Compound adder
// Consists of 3:2 CSA followed by long compound CPA
//assign prodshifted = killprodM ? 0 : {56'b0, r2+s2, 2'b0};
//assign tmp = ({{57{r2[105]}},r2, 2'b0} + {{57{s2[105]}},s2, 2'b0});
assign sum0 = t2 + 164'b0 + {57'b0, r2+s2, 2'b0};
assign sum1 = t2 + 164'b1 + {57'b0, r2+s2, 2'b0}; // +1 from invert of z above
// Check sign bits in +0/1 modes
assign negsum0 = sum0[164];
assign negsum1 = sum1[164];
// Mux proper result (+Oil mode and inversion) using 4:1 mux
//assign sumzero = |sum;
assign sum = selsum1 ? (negsum ? -sum1[163:0] : sum1[163:0]) : (negsum ? -sum0[163:0] : sum0[163:0]);
endmodule

88
wally-pipelined/src/fpu/align.sv
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@ -1,88 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: align.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block implements the alignment shifter. It is responsible for
// adjusting the fraction portion of the addend relative to the fraction
// produced in the multiplier array.
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module align(zman, aligncntE, xzeroE, yzeroE, zzeroE, zdenormE, tE, bsE,
killprodE, sumshiftE, sumshiftzeroE);
/////////////////////////////////////////////////////////////////////////////
input logic [51:0] zman; // Fraction of addend z;
input logic [12:0] aligncntE; // amount to shift
input logic xzeroE; // Input X = 0
input logic yzeroE; // Input Y = 0
input logic zzeroE; // Input Z = 0
input logic zdenormE; // Input Z is denormalized
output logic [163:0] tE; // aligned addend (54 bits left of bpt)
output logic bsE; // sticky bit of addend
output logic killprodE; // Z >> product
output logic [8:0] sumshiftE;
output logic sumshiftzeroE;
// Internal nodes
reg [215:0] shift; // aligned addend from shifter
logic [12:0] tmp;
always_comb
begin
// Default to clearing sticky bits
bsE = 0;
// And to using product as primary operand in adder I exponent gen
killprodE = xzeroE | yzeroE;
// d = aligncntE
// p = 53
//***try reducing this hardware to use one shifter
if ($signed(aligncntE) <= $signed(-(13'd105))) begin //d<=-2p+1
//product ancored case with saturated shift
sumshiftE = 163; // 3p+4
sumshiftzeroE = 0;
shift = {1'b1,zman,163'b0} >> sumshiftE;
tE = zzeroE ? 0 : {shift[215:52]};
bsE = |(shift[51:0]);
end else if($signed(aligncntE) <= $signed(13'd2)) begin // -2p+1<d<=2
// product ancored or cancellation
tmp = 13'd57-aligncntE;
sumshiftE = tmp[8:0]; // p + 2 - d
sumshiftzeroE = 0;
shift = {~zdenormE,zman,163'b0} >> sumshiftE;
tE = zzeroE ? 0 : {shift[215:52]};
bsE = |(shift[51:0]);
end else if ($signed(aligncntE)<=$signed(13'd55)) begin // 2 < d <= p+2
// addend ancored case
// used to be 56 \/ somthing doesn't seem right too many typos
tmp = 13'd57-aligncntE;
sumshiftE = tmp[8:0];
sumshiftzeroE = 0;
shift = {~zdenormE,zman, 163'b0} >> sumshiftE;
tE = zzeroE ? 0 : {shift[215:52]};
bsE = |(shift[51:0]);
end else begin // d >= p+3
// addend anchored case with saturated shift
sumshiftE = 0;
sumshiftzeroE = 1;
shift = {~zdenormE,zman, 163'b0} >> sumshiftE;
tE = zzeroE ? 0 : {shift[215:52]};
bsE = |(shift[51:0]);
killprodE = 1;
end
end
endmodule

53
wally-pipelined/src/fpu/booth.sv
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@ -1,53 +0,0 @@
module booth(xExt, choose, add1, e, pp);
/////////////////////////////////////////////////////////////////////////////
input logic [53:0] xExt; // multiplicand xExt
input logic [2:0] choose; // bits needed to choose which encoding
output logic [1:0] add1; // do you add 1
output logic e;
output logic [54:0] pp; // the resultant encoding
logic [54:0] temp;
logic [53:0] negx;
//logic temp;
assign negx = ~xExt;
always_comb
case (choose)
3'b000 : pp = 55'b0; // 0
3'b001 : pp = {1'b0, xExt}; // 1
3'b010 : pp = {1'b0, xExt}; // 1
3'b011 : pp = {xExt, 1'b0}; // 2
3'b100 : pp = {negx, 1'b0}; // -2
3'b101 : pp = {1'b1, negx}; // -1
3'b110 : pp = {1'b1, negx}; // -1
3'b111 : pp = '1; // -0
endcase
always_comb
case (choose)
3'b000 : e = 0; // 0
3'b001 : e = 0; // 1
3'b010 : e = 0; // 1
3'b011 : e = 0; // 2
3'b100 : e = 1; // -2
3'b101 : e = 1; // -1
3'b110 : e = 1; // -1
3'b111 : e = 1; // -0
endcase
// assign add1 = (choose[2] == 1'b1) ? ((choose[1:0] == 2'b11) ? 1'b0 : 1'b1) : 1'b0;
// assign add1 = choose[2];
always_comb
case (choose)
3'b000 : add1 = 2'b0; // 0
3'b001 : add1 = 2'b0; // 1
3'b010 : add1 = 2'b0; // 1
3'b011 : add1 = 2'b0; // 2
3'b100 : add1 = 2'b10; // -2
3'b101 : add1 = 2'b1; // -1
3'b110 : add1 = 2'b1; // -1
3'b111 : add1 = 2'b1; // -0
endcase
endmodule

93
wally-pipelined/src/fpu/compressors.sv
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@ -1,93 +0,0 @@
// //***breaks lint with warnings like: %Warning-UNOPTFLAT: Example path: src/fpu/compressors.sv:37: ASSIGNW
// //%Warning-UNOPTFLAT: Example path: src/fpu/compressors.sv:32: wallypipelinedsoc.hart.fpu.fma1.multiply.genblk5[0].add4.cout
// module add3comp2(a, b, c, carry, sum);
// /////////////////////////////////////////////////////////////////////////////
// //look into diffrent implementations of the compressors?
// parameter BITS = 4;
// input logic [BITS-1:0] a;
// input logic [BITS-1:0] b;
// input logic [BITS-1:0] c;
// output logic [BITS-1:0] carry;
// output logic [BITS-1:0] sum;
// genvar i;
// generate
// for(i= 0; i<BITS; i=i+1) begin
// sng3comp2 add0(a[i], b[i], c[i], carry[i], sum[i]);
// end
// endgenerate
// endmodule
// module add4comp2(a, b, c, d, carry, sum);
// /////////////////////////////////////////////////////////////////////////////
// parameter BITS = 4;
// input logic [BITS-1:0] a;
// input logic [BITS-1:0] b;
// input logic [BITS-1:0] c;
// input logic [BITS-1:0] d;
// output logic [BITS:0] carry;
// output logic [BITS-1:0] sum;
// logic [BITS-1:0] cout;
// logic carryTmp;
// genvar i;
// sng4comp2 add0(a[0], b[0], c[0], d[0], 1'b0, cout[0], carry[0], sum[0]);
// generate
// for(i= 1; i<BITS-1; i=i+1) begin
// sng4comp2 add1(a[i], b[i], c[i], d[i], cout[i-1], cout[i], carry[i], sum[i]);
// end
// endgenerate
// sng4comp2 add2(a[BITS-1], b[BITS-1], c[BITS-1], d[BITS-1], cout[BITS-2], cout[BITS-1], carryTmp, sum[BITS-1]);
// assign carry[BITS-1] = carryTmp & cout[BITS-1];
// assign carry[BITS] = carryTmp ^ cout[BITS-1];
// endmodule
// module sng3comp2(a, b, c, carry, sum);
// /////////////////////////////////////////////////////////////////////////////
// //look into diffrent implementations of the compressors?
// input logic a;
// input logic b;
// input logic c;
// output logic carry;
// output logic sum;
// logic axorb;
// assign axorb = a ^ b;
// assign sum = axorb ^ c;
// assign carry = axorb ? c : a;
// endmodule
// module sng4comp2(a, b, c, d, cin, cout, carry, sum);
// /////////////////////////////////////////////////////////////////////////////
// //look into pass gate 4:2 counters?
// input logic a;
// input logic b;
// input logic c;
// input logic d;
// input logic cin;
// output logic cout;
// output logic carry;
// output logic sum;
// logic TmpSum;
// sng3comp2 add1(.carry(cout), .sum(TmpSum),.*);
// sng3comp2 add2(.a(TmpSum), .b(d), .c(cin), .*);
// endmodule

90
wally-pipelined/src/fpu/expgen1.sv
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@ -1,90 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: expgen.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block implements the exponent path of the FMAC. It performs the
// following operations:
//
// 1) Compute exponent of multiply.
// 2) Compare multiply and add exponents to generate alignment shift count
// 3) Adjust exponent based on normalization
// 4) Increment exponent based on postrounding renormalization
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module expgen1(xexp, yexp, zexp, xzeroE, yzeroE,
xdenormE, ydenormE, zdenormE,
aligncntE, prodof, aeE);
/////////////////////////////////////////////////////////////////////////////
input logic [62:52] xexp; // Exponent of multiplicand x
input logic [62:52] yexp; // Exponent of multiplicand y
input logic [62:52] zexp; // Exponent of addend z
input logic xdenormE; // Z is denorm
input logic ydenormE; // Z is denorm
input logic zdenormE; // Z is denorm
input logic xzeroE; // Z is denorm
input logic yzeroE; // Z is denorm
output logic [12:0] aligncntE; // shift count for alignment shifter
output logic prodof; // X*Y exponent out of bounds
output logic [12:0] aeE; //exponent of multiply
// Internal nodes
wire [12:0] aligncnt0; // Shift count for alignment
wire [12:0] aligncnt1; // Shift count for alignment
wire [12:0] be; // Exponent of multiply
wire [12:0] de1; // Normalized exponent
wire [12:0] de; // Normalized exponent
wire [10:0] infinityres; // Infinity or max number
wire [10:0] nanres; // Nan propagated or generated
wire [10:0] specialres; // Exceptional case result
// Compute exponent of multiply
// Note that the exponent does not have to be incremented on a postrounding
// normalization of X because the mantissa was already increased. Report
// if exponent is out of bounds
assign aeE = xzeroE|yzeroE ? 0 : {2'b0,xexp} + {2'b0,yexp} - 13'd1023;
assign prodof = (aeE > 2046 && ~aeE[12]);
// Compute alignment shift count
// Adjust for postrounding normalization of Z.
// This should not increas the critical path because the time to
// check if a round overflows is shorter than the actual round and
// is masked by the bypass mux and two 10 bit adder delays.
// assign aligncnt0 = - 1 + ~xdenormE + ~ydenormE - ~zdenormE;
// assign aligncnt1 = - 1 + {12'b0,~xdenormE} + {12'b0,~ydenormE} - {12'b0,~zdenormE};
assign aligncntE = {2'b0,zexp} -aeE - 1 + {12'b0,~xdenormE} + {12'b0,~ydenormE} - {12'b0,~zdenormE};
//assign aligncntE = zexp -aeE - 1 + ~xdenormE + ~ydenormE - ~zdenormE;
//assign aligncntE = zexp - aeE;// KEP use all of aeE
// Select exponent (usually from product except in case of huge addend)
//assign be = zexpsel ? zexp : aeE;
// Adjust exponent based on normalization
// A compound adder takes care of the case of post-rounding normalization
// requiring an extra increment
//assign de0 = sumzero ? 13'b0 : be + normcnt + 2;
// assign de1 = sumzero ? 13'b0 : be + normcnt + 2;
// bypass occurs before rounding or taking early results
//assign wbypass = de0[10:0];
// In a non-critical special mux, we combine the early result from other
// FPU blocks with the results of exceptional conditions. Overflow
// produces either infinity or the largest finite number, depending on the
// rounding mode. NaNs are propagated or generated.
endmodule

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@ -1,108 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: expgen.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block implements the exponent path of the FMAC. It performs the
// following operations:
//
// 1) Compute exponent of multiply.
// 2) Compare multiply and add exponents to generate alignment shift count
// 3) Adjust exponent based on normalization
// 4) Increment exponent based on postrounding renormalization
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module expgen2(xexp, yexp, zexp,
sumzero, resultdenorm, infinity,
FmaFlagsM, inf, expplus1,
nanM, de0, xnanM, ynanM, znanM, specialsel,
wexp,
sumof, sumuf);
/////////////////////////////////////////////////////////////////////////////
input logic [62:52] xexp; // Exponent of multiplicand x
input logic [62:52] yexp; // Exponent of multiplicand y
input logic [62:52] zexp; // Exponent of addend z
input logic sumzero; // sum exactly equals zero
input logic resultdenorm; // postnormalize rounded result
input logic infinity; // generate infinity on overflow
input logic [4:0] FmaFlagsM; // Result invalid
input logic inf; // Some input is infinity
input logic nanM; // Some input is NaN
input logic [12:0] de0; // X is NaN NaN
input logic xnanM; // X is NaN
input logic ynanM; // Y is NaN
input logic znanM; // Z is NaN
input logic expplus1;
input logic specialsel; // Select special result
output logic [62:52] wexp; // Exponent of result
output logic sumof; // X*Y+Z exponent out of bounds
output logic sumuf; // X*Y+Z exponent underflows
// Internal nodes
wire [12:0] aligncnt0; // Shift count for alignment
wire [12:0] aligncnt1; // Shift count for alignment
wire [12:0] be; // Exponent of multiply
wire [12:0] de1; // Normalized exponent
wire [12:0] de; // Normalized exponent
wire [10:0] infinityres; // Infinity or max number
wire [10:0] nanres; // Nan propagated or generated
wire [10:0] specialres; // Exceptional case result
// Compute exponent of multiply
// Note that the exponent does not have to be incremented on a postrounding
// normalization of X because the mantissa was already increased. Report
// if exponent is out of bounds
// Select exponent (usually from product except in case of huge addend)
//assign be = zexpsel ? zexp : ae;
// Adjust exponent based on normalization
// A compound adder takes care of the case of post-rounding normalization
// requiring an extra increment
//assign de0 = sumzero ? 13'b0 : be + normcnt + 2;
// assign de1 = sumzero ? 13'b0 : be + normcnt + 2;
// check for exponent out of bounds after add
assign de = resultdenorm | sumzero ? 0 : de0;
assign sumof = ~de[12] && de > 2046;
assign sumuf = de == 0 && ~sumzero && ~resultdenorm;
// bypass occurs before rounding or taking early results
//assign wbypass = de0[10:0];
// In a non-critical special mux, we combine the early result from other
// FPU blocks with the results of exceptional conditions. Overflow
// produces either infinity or the largest finite number, depending on the
// rounding mode. NaNs are propagated or generated.
assign specialres = FmaFlagsM[4] | nanM ? nanres : // invalid
FmaFlagsM[2] ? infinityres : //overflow
inf ? 11'b11111111111 :
FmaFlagsM[1] ? 11'b0 : 11'bx; //underflow
assign infinityres = infinity ? 11'b11111111111 : 11'b11111111110;
// IEEE 754-2008 section 6.2.3 states:
// "If two or more inputs are NaN, then the payload of the resulting NaN should be
// identical to the payload of one of the input NaNs if representable in the destination
// format. This standard does not specify which of the input NaNs will provide the payload."
assign nanres = xnanM ? xexp : (ynanM ? yexp : (znanM? zexp : 11'b11111111111));
// A mux selects the early result from other FPU blocks or the
// normalized FMAC result. Special cases are also detected.
assign wexp = specialsel ? specialres[10:0] : de[10:0] + {10'b0,expplus1};
endmodule

9
wally-pipelined/src/fpu/fctrl.sv
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@ -57,12 +57,13 @@ module fctrl (
always_comb begin always_comb begin
//checks all but FMA/store/load //checks all but FMA/store/load
IllegalFPUInstr2D = 0; IllegalFPUInstr2D = 0;
FDivStartD = 1'b0;
if(OpD == 7'b1010011) begin if(OpD == 7'b1010011) begin
casez(Funct7D) casez(Funct7D)
//compare //compare
7'b10100?? : FResultSelD = 3'b001; 7'b10100?? : FResultSelD = 3'b001;
//div/sqrt //div/sqrt
7'b0?011?? : FResultSelD = 3'b000; 7'b0?011?? : begin FResultSelD = 3'b000; FDivStartD = 1'b1; end
//add/sub //add/sub
7'b0000??? : FResultSelD = 3'b100; 7'b0000??? : FResultSelD = 3'b100;
//mult //mult
@ -129,8 +130,6 @@ module fctrl (
//this value is used enough to be shorthand //this value is used enough to be shorthand
//if op is div/sqrt - start div/sqrt
assign FDivStartD = ~|FResultSelD; // is FResultSelD == 000
//operation control for each fp operation //operation control for each fp operation
//has to be expanded over standard to account for //has to be expanded over standard to account for
@ -168,8 +167,8 @@ module fctrl (
//fma/mult //fma/mult
// fmadd = ?000 // fmadd = ?000
// fmsub = ?001 // fmsub = ?001
// fnmadd = ?010 // fnmsub = ?010 -(a*b)+c
// fnmsub = ?011 // fnmadd = ?011 -(a*b)-c
// fmul = ?100 // fmul = ?100
// {?, is mul, is negitive, is sub} // {?, is mul, is negitive, is sub}
3'b010 : begin FOpCtrlD = {1'b0, OpD[4:2]}; FInput2UsedD = 1'b1; FInput3UsedD = ~OpD[4]; end 3'b010 : begin FOpCtrlD = {1'b0, OpD[4:2]}; FInput2UsedD = 1'b1; FInput3UsedD = ~OpD[4]; end

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@ -1,34 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: flag.v
// Author: David Harris
// Date: 12/6/1995
//
// Block Description:
// This block generates the flags: invalid, overflow, underflow, inexact.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module flag1(xnanE, ynanE, znanE, prodof, prodinfE, nanE);
/////////////////////////////////////////////////////////////////////////////
input logic xnanE; // X is NaN
input logic ynanE; // Y is NaN
input logic znanE; // Z is NaN
input logic prodof; // X*Y overflows exponent
output logic nanE; // Some source is NaN
// Internal nodes
output logic prodinfE; // X*Y larger than max possible
// If any input logic is NaN, propagate the NaN
assign nanE = xnanE || ynanE || znanE;
// Generate infinity checks
assign prodinfE = prodof && ~xnanE && ~ynanE;
endmodule

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@ -1,80 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: flag.v
// Author: David Harris
// Date: 12/6/1995
//
// Block Description:
// This block generates the flags: invalid, overflow, underflow, inexact.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module flag2(xsign,ysign,zsign, xnanM, ynanM, znanM, xinfM, yinfM, zinfM, sumof, sumuf,
xzeroM, yzeroM, zzeroM, vbits, killprodM,
inf, nanM, FmaFlagsM,sticky,prodinfM);
/////////////////////////////////////////////////////////////////////////////
input logic xnanM; // X is NaN
input logic ynanM; // Y is NaN
input logic znanM; // Z is NaN
input logic xsign; // Sign of z
input logic ysign; // Sign of z
input logic zsign; // Sign of z
input logic sticky; // X is Inf
input logic prodinfM;
input logic xinfM; // X is Inf
input logic yinfM; // Y is Inf
input logic zinfM; // Z is Inf
input logic sumof; // X*Y + z underflows exponent
input logic sumuf; // X*Y + z underflows exponent
input logic xzeroM; // x = 0
input logic yzeroM; // y = 0
input logic zzeroM; // y = 0
input logic killprodM;
input logic [1:0] vbits; // R and S bits of result
output logic inf; // Some source is Inf
input logic nanM; // Some source is NaN
output logic [4:0] FmaFlagsM;
// Internal nodes
logic suminf;
// Same with infinity (inf - inf and O * inf don't propagate inf
// but it's ok becaue illegal op takes higher precidence)
assign inf= xinfM || yinfM || zinfM || suminf;//KEP added suminf
//assign inf= xinfM || yinfM || zinfM;//original
assign suminf = sumof && ~xnanM && ~ynanM && ~znanM;
// Set the overflow flag for the following cases:
// 1) Rounded multiply result would be out of bounds
// 2) Rounded add result would be out of bounds
assign FmaFlagsM[2] = suminf && ~inf;
// Set the underflow flag for the following cases:
// 1) Any input logic is denormalized
// 2) output logic would be denormalized or smaller
assign FmaFlagsM[1] = (sumuf && ~inf && ~prodinfM && ~nanM) || (killprodM & zzeroM & ~(yzeroM | xzeroM));
// Set the inexact flag for the following cases:
// 1) Multiplication inexact
// 2) Addition inexact
// One of these cases occurred if the R or S bit is set
assign FmaFlagsM[0] = (vbits[0] || vbits[1] ||sticky || suminf) && ~(inf || nanM);
// Set invalid flag for following cases:
// 1) Inf - Inf
// 2) 0 * Inf
// 3) output logic = NaN (this is not part of the IEEE spec, only 486 proj)
assign FmaFlagsM[4] = (xinfM || yinfM || prodinfM) && zinfM && (xsign ^ ysign ^ zsign) ||
xzeroM && yinfM || yzeroM && xinfM;// KEP remove case 3) above
assign FmaFlagsM[3] = 0; // divide by zero flag
endmodule

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@ -1,103 +1,141 @@
//////////////////////////////////////////////////////////////////////////////// module fma1(
// Block Name: fmac.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This is the top level block of a floating-point multiply/accumulate
// unit(FMAC). It instantiates the following sub-blocks:
//
// array Booth encoding, partial product generation, product summation
// expgen Exponent summation, compare, and adjust
// align Alignment shifter
// add Carry-save adder for accumulate, carry propagate adder
// lza Leading zero anticipator to control normalization shifter
// normalize Normalization shifter
// round Rounding of result
// exception Handles exceptional cases
// bypass Handles bypass of result to FInput1E or FInput3E inputs
// sign One bit sign handling block
// special Catch special cases (inputs = 0 / infinity / etc.)
//
// The FMAC computes FmaResultM=FInput1E*FInput2E+FInput3E, rounded with the mode specified by
// RN, RZ, RM, or RP. The result is optionally bypassed back to
// the FInput1E or FInput3E inputs for use on the next cycle. In addition, four signals
// are produced: trap, overflow, underflow, and inexact. Trap indicates
// an infinity, NaN, or denormalized number to be handled in software;
// the other three signals are IEEE flags.
//
/////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////// input logic [63:0] FInput1E,
module fma1(FInput1E, FInput2E, FInput3E, FrmE, input logic [63:0] FInput2E,
rE, sE, tE, bsE, killprodE, sumshiftE, sumshiftzeroE, aligncntE, aeE input logic [63:0] FInput3E,
, xzeroE, yzeroE, zzeroE, xnanE,ynanE, znanE, xdenormE, ydenormE, zdenormE, input logic [3:0] FOpCtrlE,
xinfE, yinfE, zinfE, nanE, prodinfE); output logic [105:0] ProdManE,
///////////////////////////////////////////////////////////////////////////// output logic [161:0] AlignedAddendE,
output logic [12:0] ProdExpE,
output logic AddendStickyE,
output logic KillProdE,
output logic XZeroE, YZeroE, ZZeroE,
output logic XInfE, YInfE, ZInfE,
output logic XNaNE, YNaNE, ZNaNE);
input logic [63:0] FInput1E; // input 1 logic [51:0] XMan,YMan,ZMan;
input logic [63:0] FInput2E; // input 2 logic [10:0] XExp,YExp,ZExp;
input logic [63:0] FInput3E; // input 3 logic XSgn,YSgn,ZSgn;
input logic [2:0] FrmE; // Rounding mode logic [12:0] AlignCnt;
output logic [12:0] aligncntE; // status flags logic [211:0] Shift;
output logic [105:0] rE; // one result of partial product sum logic XDenormE, YDenormE, ZDenormE;
output logic [105:0] sE; // other result of partial products logic [63:0] FInput3E2;
output logic [163:0] tE; // output logic of alignment shifter
output logic [12:0] aeE; // multiplier expoent
output logic bsE; // sticky bit of addend
output logic killprodE; // FInput3E >> product
output logic xzeroE;
output logic yzeroE;
output logic zzeroE;
output logic xdenormE;
output logic ydenormE;
output logic zdenormE;
output logic xinfE;
output logic yinfE;
output logic zinfE;
output logic xnanE;
output logic ynanE;
output logic znanE;
output logic nanE;
output logic prodinfE;
output logic [8:0] sumshiftE;
output logic sumshiftzeroE;
// Internal nodes // Set addend to zero if FMUL instruction
assign FInput3E2 = FOpCtrlE[2] ? 64'b0 : FInput3E;
// output logic [12:0] aligncntE; // shift count for alignment // split inputs into the sign bit, mantissa, and exponent for readability
assign XSgn = FInput1E[63];
assign YSgn = FInput2E[63];
assign ZSgn = FInput3E2[63];
assign XExp = FInput1E[62:52];
assign YExp = FInput2E[62:52];
assign ZExp = FInput3E2[62:52];
assign XMan = FInput1E[51:0];
assign YMan = FInput2E[51:0];
assign ZMan = FInput3E2[51:0];
logic prodof; // FInput1E*FInput2E out of range
// determine if an input is a special value
assign XNaNE = &FInput1E[62:52] && |FInput1E[51:0];
assign YNaNE = &FInput2E[62:52] && |FInput2E[51:0];
assign ZNaNE = &FInput3E2[62:52] && |FInput3E2[51:0];
assign XDenormE = ~(|FInput1E[62:52]) && |FInput1E[51:0];
assign YDenormE = ~(|FInput2E[62:52]) && |FInput2E[51:0];
assign ZDenormE = ~(|FInput3E2[62:52]) && |FInput3E2[51:0];
assign XInfE = &FInput1E[62:52] && ~(|FInput1E[51:0]);
assign YInfE = &FInput2E[62:52] && ~(|FInput2E[51:0]);
assign ZInfE = &FInput3E2[62:52] && ~(|FInput3E2[51:0]);
assign XZeroE = ~(|FInput1E[62:0]);
assign YZeroE = ~(|FInput2E[62:0]);
assign ZZeroE = ~(|FInput3E2[62:0]);
// Calculate the product's exponent
// - When multipliying two fp numbers, add the exponents
// - Subtract 3ff to remove one of the biases (XExp + YExp has two biases, one from each exponent)
// - Denormal numbers have an an exponent value of 1, however they are
// represented with an exponent of 0. add one if there is a denormal number
assign ProdExpE = (XZeroE|YZeroE) ? 13'b0 :
{2'b0, XExp} + {2'b0, YExp} - 13'h3ff + {12'b0, XDenormE} + {12'b0, YDenormE};
// Calculate the product's mantissa
// - Add the assumed one. If the number is denormalized or zero, it does not have an assumed one.
assign ProdManE = {53'b0,~(XDenormE|XZeroE),XMan} * {53'b0,~(YDenormE|YZeroE),YMan};
// determine the shift count for alignment
// - negitive means Z is larger, so shift Z left
// - positive means the product is larger, so shift Z right
// - Denormal numbers have an an exponent value of 1, however they are
// represented with an exponent of 0. add one to the exponent if it is a denormal number
assign AlignCnt = ProdExpE - {2'b0, ZExp} - {12'b0, ZDenormE};
// Alignment shifter
// Defualt Addition without shifting
// | 55'b0 | 106'b(product) | 2'b0 |
// |1'b0| addnend |
// the 1'b0 before the added is because the product's mantissa has two bits before the decimal point (xx.xxxxxxxxxx...)
always_comb
begin
// Set default values
AddendStickyE = 0;
KillProdE = 0;
// If the product is too small to effect the sum, kill the product
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
if ($signed(AlignCnt) <= $signed(-13'd56)) begin
KillProdE = 1;
AlignedAddendE = {107'b0, ~(ZZeroE|ZDenormE),ZMan,2'b0};
AddendStickyE = ~(XZeroE|YZeroE);
// If the Addend is shifted left (negitive AlignCnt)
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else if($signed(AlignCnt) <= $signed(13'd0)) begin
Shift = {55'b0, ~(ZZeroE|ZDenormE),ZMan, 104'b0} << -AlignCnt;
AlignedAddendE = Shift[211:50];
AddendStickyE = |(Shift[49:0]);
// If the Addend is shifted right (positive AlignCnt)
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else if ($signed(AlignCnt)<=$signed(13'd105)) begin
Shift = {55'b0, ~(ZZeroE|ZDenormE),ZMan, 104'b0} >> AlignCnt;
AlignedAddendE = Shift[211:50];
AddendStickyE = |(Shift[49:0]);
// If the addend is too small to effect the addition
// - The addend has to shift two past the end of the addend to be considered too small
// - The 2 extra bits are needed for rounding
// | 55'b0 | 106'b(product) | 2'b0 |
// | addnend |
end else begin
AlignedAddendE = 162'b0;
AddendStickyE = ~ZZeroE;
end
end
// Instantiate fraction datapath
multiply multiply(.xman(FInput1E[51:0]), .yman(FInput2E[51:0]), .*);
align align(.zman(FInput3E[51:0]),.*);
// Instantiate exponent datapath
expgen1 expgen1(.xexp(FInput1E[62:52]),.yexp(FInput2E[62:52]),.zexp(FInput3E[62:52]),.*);
// Instantiate special case detection across datapath & exponent path
special special(.*);
// Instantiate control output logic
flag1 flag1(.*);
endmodule endmodule

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@ -1,107 +1,110 @@
//////////////////////////////////////////////////////////////////////////////// module fma2(
// Block Name: fmac.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This is the top level block of a floating-point multiply/accumulate
// unit(FMAC). It instantiates the following sub-blocks:
//
// array Booth encoding, partial product generation, product summation
// expgen Mxponent summation, compare, and adjust
// align Alignment shifter
// add Carry-save adder for accumulate, carry propagate adder
// lza Leading zero anticipator to control normalization shifter
// normalize Normalization shifter
// round Rounding of result
// exception Handles exceptional cases
// bypass Handles bypass of result to FInput1M or FInput3M input logics
// sign One bit sign handling block
// special Catch special cases (input logics = 0 / infinity / etc.)
//
// The FMAC computes FmaResultM=FInput1M*FInput2M+FInput3M, rounded with the mode specified by
// RN, RZ, RM, or RP. The result is optionally bypassed back to
// the FInput1M or FInput3M input logics for use on the next cycle. In addition, four signals
// are produced: trap, overflow, underflow, and inexact. Trap indicates
// an infinity, NaN, or denormalized number to be handled in software;
// the other three signals are IMMM flags.
//
/////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////// input logic [63:0] FInput1M,
module fma2(FInput1M, FInput2M, FInput3M, FrmM, input logic [63:0] FInput2M,
FmaResultM, FmaFlagsM, aligncntM, rM, sM, input logic [63:0] FInput3M,
tM, normcntM, aeM, bsM,killprodM, input logic [2:0] FrmM,
xzeroM, yzeroM,zzeroM,xdenormM,ydenormM, input logic [105:0] ProdManM,
zdenormM,xinfM,yinfM,zinfM,xnanM,ynanM,znanM, input logic [161:0] AlignedAddendM,
nanM,sumshiftM,sumshiftzeroM,prodinfM input logic [12:0] ProdExpM,
input logic AddendStickyM,
); input logic KillProdM,
///////////////////////////////////////////////////////////////////////////// input logic [3:0] FOpCtrlM,
input logic XZeroM, YZeroM, ZZeroM,
input logic [63:0] FInput1M; // input logic 1 input logic XInfM, YInfM, ZInfM,
input logic [63:0] FInput2M; // input logic 2 input logic XNaNM, YNaNM, ZNaNM,
input logic [63:0] FInput3M; // input logic 3 output logic [63:0] FmaResultM,
input logic [2:0] FrmM; // Rounding mode output logic [4:0] FmaFlagsM);
input logic [12:0] aligncntM; // status flags
input logic [105:0] rM; // one result of partial product sum
input logic [105:0] sM; // other result of partial products
input logic [163:0] tM; // output of alignment shifter
input logic [8:0] normcntM; // shift count for normalizer
input logic [12:0] aeM; // multiplier expoent
input logic bsM; // sticky bit of addend
input logic killprodM; // FInput3M >> product
input logic prodinfM;
input logic xzeroM;
input logic yzeroM;
input logic zzeroM;
input logic xdenormM;
input logic ydenormM;
input logic zdenormM;
input logic xinfM;
input logic yinfM;
input logic zinfM;
input logic xnanM;
input logic ynanM;
input logic znanM;
input logic nanM;
input logic [8:0] sumshiftM;
input logic sumshiftzeroM;
output logic [63:0] FmaResultM; // output FmaResultM=FInput1M*FInput2M+FInput3M
output logic [4:0] FmaFlagsM; // status flags logic [51:0] XMan, YMan, ZMan, WMan;
logic [10:0] XExp, YExp, ZExp, WExp;
logic XSgn, YSgn, ZSgn, WSgn, PSgn;
logic [105:0] ProdMan2;
logic [162:0] AlignedAddend2;
logic [161:0] Sum;
logic [162:0] SumTmp;
logic [12:0] SumExp;
logic [12:0] SumExpMinus1;
logic [12:0] SumExpTmp, SumExpTmpMinus1, WExpTmp;
logic [53:0] NormSum;
logic [161:0] NormSumTmp;
logic [8:0] NormCnt;
logic NormSumSticky;
logic SumZero;
logic NegSum;
logic InvZ;
logic ResultDenorm;
logic Sticky;
logic Plus1, Minus1, Plus1Tmp, Minus1Tmp;
logic Invalid,Underflow,Overflow,Inexact;
logic [8:0] DenormShift;
logic ProdInf, ProdOf, ProdUf;
logic [63:0] FmaResultTmp;
logic SubBySmallNum;
logic [63:0] FInput3M2;
logic ZeroSgn, ResultSgn;
// Set addend to zero if FMUL instruction
assign FInput3M2 = FOpCtrlM[2] ? 64'b0 : FInput3M;
// split inputs into the sign bit, mantissa, and exponent for readability
assign XSgn = FInput1M[63];
assign YSgn = FInput2M[63];
assign ZSgn = FInput3M2[63]^FOpCtrlM[0]; //Negate Z if subtraction
assign XExp = FInput1M[62:52];
assign YExp = FInput2M[62:52];
assign ZExp = FInput3M2[62:52];
assign XMan = FInput1M[51:0];
assign YMan = FInput2M[51:0];
assign ZMan = FInput3M2[51:0];
// Internal nodes
logic [163:0] sum; // output of carry prop adder
logic [53:0] v; // normalized sum, R, S bits
// logic [12:0] aligncnt; // shift count for alignment
logic [8:0] normcnt; // shift count for normalizer
logic negsum; // negate sum
logic invz; // invert addend
logic selsum1; // select +1 mode of sum
logic negsum0; // sum +0 < 0
logic negsum1; // sum +1 < 0
logic sumzero; // sum = 0
logic infinity; // generate infinity on overflow
logic sumof; // result out of range
logic zexpsel;
logic denorm0;
logic resultdenorm;
logic inf;
logic specialsel;
logic expplus1;
logic sumuf;
logic psign;
logic sticky;
logic [12:0] de0;
logic isAdd;
logic wsign;
logic [51:0] wman;
logic [10:0] wexp;
assign isAdd = 1; // Calculate the product's sign
// Negate product's sign if FNMADD or FNMSUB
assign PSgn = XSgn ^ YSgn ^ FOpCtrlM[1];
// Addition
// Negate Z when doing one of the following opperations:
// -prod + Z
// prod - Z
assign InvZ = ZSgn ^ PSgn;
// Choose an inverted or non-inverted addend - the one is added later
assign AlignedAddend2 = InvZ ? ~{1'b0,AlignedAddendM} : {1'b0,AlignedAddendM};
// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
assign ProdMan2 = KillProdM ? 106'b0 : ProdManM;
// Do the addition
// - add one to negate if the added was inverted
// - the 2 extra bits at the begining and end are needed for rounding
assign SumTmp = AlignedAddend2 + {55'b0, ProdMan2,2'b0} + {162'b0, InvZ};
// Is the sum negitive
assign NegSum = SumTmp[162];
// If the sum is negitive, negate the sum.
assign Sum = NegSum ? -SumTmp[161:0] : SumTmp[161:0];
// Leading one detector
logic [8:0] i;
always_comb begin
i = 0;
while (~Sum[161-i] && $unsigned(i) <= $unsigned(9'd161)) i = i+1; // search for leading one
NormCnt = i+1; // compute shift count
end
@ -113,27 +116,160 @@ module fma2(FInput1M, FInput2M, FInput3M, FrmM,
// Normalization
// Determine if the sum is zero
assign SumZero = ~(|Sum);
// Determine if the result is denormal
assign ResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp+13'd52)>=0);
// Determine the shift needed for denormal results
assign SumExpTmpMinus1 = SumExpTmp-1;
assign DenormShift = ResultDenorm ? SumExpTmpMinus1[8:0] : 9'b0;
// Normalize the sum
assign NormSumTmp = SumZero ? 162'b0 : Sum << NormCnt+DenormShift;
assign NormSum = NormSumTmp[161:108];
// Calculate the sticky bit
assign NormSumSticky = (|NormSumTmp[107:0]);
assign Sticky = AddendStickyM | NormSumSticky;
// Determine sum's exponent
assign SumExpTmp = KillProdM ? {2'b0, ZExp} : ProdExpM + -({4'b0, NormCnt} - 13'd56);
assign SumExp = SumZero ? 13'b0 :
ResultDenorm ? 13'b0 :
SumExpTmp;
// Instantiate fraction datapath
add add(.*);
lza lza(.*);
normalize normalize(.zexp(FInput3M[62:52]),.*);
round round(.xman(FInput1M[51:0]), .yman(FInput2M[51:0]),.zman(FInput3M[51:0]),.*);
// Instantiate exponent datapath
expgen2 expgen2(.xexp(FInput1M[62:52]),.yexp(FInput2M[62:52]),.zexp(FInput3M[62:52]),.*);
// Instantiate control logic
sign sign(.xsign(FInput1M[63]),.ysign(FInput2M[63]),.zsign(FInput3M[63]),.*);
flag2 flag2(.xsign(FInput1M[63]),.ysign(FInput2M[63]),.zsign(FInput3M[63]),.vbits(v[1:0]),.*);
assign FmaResultM = {wsign,wexp,wman};
// Rounding
// round to nearest even
// {NormSum[1], NormSum[0], Sticky}
// 0xx - do nothing
// 100 - tie - Plus1 if NormSum[2] = 1
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// 101/110/111 - Plus1
// round to zero - do nothing
// - subtract 1 if a small number was supposed to be subtracted from the positive result
// round to -infinity - Plus1 if negitive
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// - subtract 1 if a small number was supposed to be subtracted from the positive result
// round to infinity - Plus1 if positive
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// - subtract 1 if a small number was supposed to be subtracted from the negitive result
// round to nearest max magnitude
// {NormSum[1], NormSum[0], Sticky}
// 0xx - do nothing
// 100 - tie - Plus1
// - don't add 1 if there was supposed to be a subtraction by a small number that didn't happen
// 101/110/111 - Plus1
// Deterimine if the result was supposed to be subtrated by a small number
assign SubBySmallNum = AddendStickyM&InvZ&~NormSumSticky;
always_comb begin
// Determine if you add 1
case (FrmM)
3'b000: Plus1Tmp = NormSum[1] & (NormSum[0] | (Sticky&~(~NormSum[0]&SubBySmallNum)) | (~NormSum[0]&~Sticky&NormSum[2]));//round to nearest even
3'b001: Plus1Tmp = 0;//round to zero
3'b010: Plus1Tmp = WSgn & ~(SubBySmallNum);//round down
3'b011: Plus1Tmp = ~WSgn & ~(SubBySmallNum);//round up
3'b100: Plus1Tmp = (NormSum[1] & (NormSum[0] | (Sticky&~(~NormSum[0]&SubBySmallNum)) | (~NormSum[0]&~Sticky)));//round to nearest max magnitude
default: Plus1Tmp = 1'bx;
endcase
// Determine if you subtract 1
case (FrmM)
3'b000: Minus1Tmp = 0;//round to nearest even
3'b001: Minus1Tmp = SubBySmallNum;//round to zero
3'b010: Minus1Tmp = ~WSgn & SubBySmallNum;//round down
3'b011: Minus1Tmp = WSgn & SubBySmallNum;//round up
3'b100: Minus1Tmp = 0;//round to nearest max magnitude
default: Minus1Tmp = 1'bx;
endcase
end
// If an answer is exact don't round
assign Plus1 = Sticky | (|NormSum[1:0]) ? Plus1Tmp : 1'b0;
assign Minus1 = Sticky | (|NormSum[1:0]) ? Minus1Tmp : 1'b0;
// Compute rounded result
assign {WExpTmp, WMan} = {SumExp, NormSum[53:2]} - {64'b0, Minus1} + {64'b0, Plus1};
assign WExp = WExpTmp[10:0];
// Sign calculation
// Determine the sign if the sum is zero
// if product underflows then use psign
// otherwise
// if cancelation then 0 unless round to -inf
// otherwise psign
assign ZeroSgn = Underflow & ~ResultDenorm ? PSgn :
(PSgn^ZSgn ? FrmM == 3'b010 : PSgn);
// is the result negitive
// if p - z is the Sum negitive
// if -p + z is the Sum positive
// if -p - z then the Sum is negitive
assign ResultSgn = InvZ&(ZSgn)&NegSum | InvZ&PSgn&~NegSum | ((ZSgn)&PSgn);
assign WSgn = SumZero ? ZeroSgn : ResultSgn;
// Select the result
assign FmaResultM = XNaNM ? {XSgn, XExp, 1'b1,XMan[50:0]} :
YNaNM ? {YSgn, YExp, 1'b1,YMan[50:0]} :
ZNaNM ? {ZSgn, ZExp, 1'b1,ZMan[50:0]} :
Invalid ? {WSgn, 11'h7ff, 1'b1, 51'b0} : // has to be before inf
XInfM ? {PSgn, XExp, XMan} :
YInfM ? {PSgn, YExp, YMan} :
ZInfM ? {ZSgn, ZExp, ZMan} :
Overflow ? {WSgn, 11'h7ff, 52'b0} :
Underflow & ~ResultDenorm ? {WSgn, 63'b0} - {63'b0, (Minus1&AddendStickyM)} + {63'b0, (Plus1&AddendStickyM)} :
KillProdM ? {ZSgn, ZExp, ZMan} - {63'b0, (Minus1&AddendStickyM)} + {63'b0, (Plus1&AddendStickyM)}: // has to be after Underflow
{WSgn,WExp,WMan};
// Set Invalid flag for following cases:
// 1) Inf - Inf
// 2) 0 * Inf
// 3) any input is a signaling NaN
assign ProdOf = (ProdExpM >= 2047 && ~ProdExpM[12]);
assign ProdInf = ProdOf && ~XNaNM && ~YNaNM;
assign Invalid = (XNaNM&~XMan[51]) | (YNaNM&~YMan[51]) | (ZNaNM&~ZMan[51]) | ((XInfM || YInfM || ProdInf) & ZInfM & (XSgn ^ YSgn ^ ZSgn)) | (XZeroM & YInfM) | (YZeroM & XInfM);
// Set Overflow flag if the number is too big to be represented
assign Overflow = WExpTmp >= 2047 & ~WExpTmp[12];
// Set Underflow flag if the number is too small to be represented in normal numbers
assign ProdUf = KillProdM & ZZeroM;
assign Underflow = SumExp[12] | ProdUf;
// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
assign Inexact = Sticky|Overflow| (|NormSum[1:0]);
// Combine flags
// - FMA can't set the Divide by zero flag
// - Don't set the underflow flag if the result is exact
assign FmaFlagsM = {Invalid, 1'b0, Overflow, Underflow & Inexact, Inexact};
endmodule endmodule

26
wally-pipelined/src/fpu/fpdiv.sv
View File

@ -23,8 +23,8 @@
// //
// `timescale 1ps/1ps // `timescale 1ps/1ps
module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn,
FDivStartE, reset, clk, DivBusyM); FDivStartE, reset, clk, FDivBusyE);
input [63:0] FInput1E; // 1st input operand (A) input [63:0] FInput1E; // 1st input operand (A)
input [63:0] FInput2E; // 2nd input operand (B) input [63:0] FInput2E; // 2nd input operand (B)
@ -38,11 +38,11 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
input reset; input reset;
input clk; input clk;
output [63:0] FDivResultM; // Result of operation output [63:0] FDivResultE; // Result of operation
output [4:0] FDivFlagsM; // IEEE exception flags output [4:0] FDivFlagsE; // IEEE exception flags
output DivDenormM; // DivDenormM on input or output output DivDenormE; // DivDenormE on input or output
output FDivSqrtDoneM; output FDivSqrtDoneE;
output DivBusyM; output FDivBusyE;
supply1 vdd; supply1 vdd;
supply0 vss; supply0 vss;
@ -101,7 +101,7 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE); convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE);
// Test for exceptions and return the "Invalid Operation" and // Test for exceptions and return the "Invalid Operation" and
// "Denormalized" Input FDivFlagsM. The "sel_inv" is used in // "Denormalized" Input FDivFlagsE. The "sel_inv" is used in
// the third pipeline stage to select the result. Also, op1_Norm // the third pipeline stage to select the result. Also, op1_Norm
// and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized. // and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized.
// sub is one if the effective operation is subtaction. // sub is one if the effective operation is subtaction.
@ -138,9 +138,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
load_regr, load_regs, FmtE, DivOpType, exp_odd); load_regr, load_regs, FmtE, DivOpType, exp_odd);
// FSM : control divider // FSM : control divider
fsm control (FDivSqrtDoneM, load_rega, load_regb, load_regc, load_regd, fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr,
clk, reset, FDivStartE, DivOpType, DivBusyM); clk, reset, FDivStartE, DivOpType, FDivBusyE);
// Round the mantissa to a 52-bit value, with the leading one // Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and // removed. The rounding units also handles special cases and
@ -152,9 +152,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
q1, qm1, qp1, q0, qm0, qp0, regr_out); q1, qm1, qp1, q0, qm0, qp0, regr_out);
// Store the final result and the exception flags in registers. // Store the final result and the exception flags in registers.
flopenr #(64) rega (clk, reset, FDivSqrtDoneM, Result, FDivResultM); flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultE);
flopenr #(1) regb (clk, reset, FDivSqrtDoneM, DenormIO, DivDenormM); flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormE);
flopenr #(5) regc (clk, reset, FDivSqrtDoneM, FlagsIn, FDivFlagsM); flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivFlagsE);
endmodule // fpadd endmodule // fpadd

91
wally-pipelined/src/fpu/fpu.sv
View File

@ -42,7 +42,7 @@ module fpu (
output logic FStallD, output logic FStallD,
output logic FWriteIntE, FWriteIntM, FWriteIntW, output logic FWriteIntE, FWriteIntM, FWriteIntW,
output logic [`XLEN-1:0] FWriteDataM, output logic [`XLEN-1:0] FWriteDataM,
output logic FDivSqrtDoneM, output logic FDivBusyE,
output logic IllegalFPUInstrD, output logic IllegalFPUInstrD,
output logic [`XLEN-1:0] FPUResultW); output logic [`XLEN-1:0] FPUResultW);
@ -73,38 +73,21 @@ module fpu (
logic [`XLEN-1:0] FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions logic [`XLEN-1:0] FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions
// div/sqrt signals // div/sqrt signals
logic DivDenormM, DivDenormW; logic DivDenormE, DivDenormM, DivDenormW;
logic DivOvEn, DivUnEn; logic DivOvEn, DivUnEn;
logic DivBusyM; logic [63:0] FDivResultE, FDivResultM, FDivResultW;
logic [63:0] FDivResultM, FDivResultW; logic [4:0] FDivFlagsE, FDivFlagsM, FDivFlagsW;
logic [4:0] FDivFlagsM, FDivFlagsW; logic FDivSqrtDoneE, FDivSqrtDoneM;
// FMA signals // FMA signals
logic [12:0] aligncntE, aligncntM; logic [105:0] ProdManE, ProdManM;
logic [105:0] rE, rM; logic [161:0] AlignedAddendE, AlignedAddendM;
logic [105:0] sE, sM; logic [12:0] ProdExpE, ProdExpM;
logic [163:0] tE, tM; logic AddendStickyE, AddendStickyM;
logic [8:0] normcntE, normcntM; logic KillProdE, KillProdM;
logic [12:0] aeE, aeM; logic XZeroE, YZeroE, ZZeroE, XZeroM, YZeroM, ZZeroM;
logic bsE, bsM; logic XInfE, YInfE, ZInfE, XInfM, YInfM, ZInfM;
logic killprodE, killprodM; logic XNaNE, YNaNE, ZNaNE, XNaNM, YNaNM, ZNaNM;
logic prodofE, prodofM;
logic xzeroE, xzeroM;
logic yzeroE, yzeroM;
logic zzeroE, zzeroM;
logic xdenormE, xdenormM;
logic ydenormE, ydenormM;
logic zdenormE, zdenormM;
logic xinfE, xinfM;
logic yinfE, yinfM;
logic zinfE, zinfM;
logic xnanE, xnanM;
logic ynanE, ynanM;
logic znanE, znanM;
logic nanE, nanM;
logic [8:0] sumshiftE, sumshiftM;
logic sumshiftzeroE, sumshiftzeroM;
logic prodinfE, prodinfM;
logic [63:0] FmaResultM, FmaResultW; logic [63:0] FmaResultM, FmaResultW;
logic [4:0] FmaFlagsM, FmaFlagsW; logic [4:0] FmaFlagsM, FmaFlagsW;
@ -241,7 +224,7 @@ module fpu (
.CLK(clk), .CLK(clk),
.ECLK(fpdivClk)); .ECLK(fpdivClk));
fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk)); fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .*);
// first of two-stage instance of floating-point add/cvt unit // first of two-stage instance of floating-point add/cvt unit
fpuaddcvt1 fpadd1 (.*); fpuaddcvt1 fpadd1 (.*);
@ -265,31 +248,27 @@ module fpu (
//***************** //*****************
// fma E/M pipe registers // fma E/M pipe registers
//***************** //*****************
flopenrc #(13) EMRegFma1(clk, reset, PipeClearEM, PipeEnableEM, aligncntE, aligncntM); flopenrc #(106) EMRegFma3(clk, reset, PipeClearEM, PipeEnableEM, ProdManE, ProdManM);
flopenrc #(106) EMRegFma2(clk, reset, PipeClearEM, PipeEnableEM, rE, rM); flopenrc #(162) EMRegFma4(clk, reset, PipeClearEM, PipeEnableEM, AlignedAddendE, AlignedAddendM);
flopenrc #(106) EMRegFma3(clk, reset, PipeClearEM, PipeEnableEM, sE, sM); flopenrc #(13) EMRegFma6(clk, reset, PipeClearEM, PipeEnableEM, ProdExpE, ProdExpM);
flopenrc #(164) EMRegFma4(clk, reset, PipeClearEM, PipeEnableEM, tE, tM); flopenrc #(1) EMRegFma7(clk, reset, PipeClearEM, PipeEnableEM, AddendStickyE, AddendStickyM);
flopenrc #(9) EMRegFma5(clk, reset, PipeClearEM, PipeEnableEM, normcntE, normcntM); flopenrc #(1) EMRegFma8(clk, reset, PipeClearEM, PipeEnableEM, KillProdE, KillProdM);
flopenrc #(13) EMRegFma6(clk, reset, PipeClearEM, PipeEnableEM, aeE, aeM); flopenrc #(1) EMRegFma10(clk, reset, PipeClearEM, PipeEnableEM, XZeroE, XZeroM);
flopenrc #(1) EMRegFma7(clk, reset, PipeClearEM, PipeEnableEM, bsE, bsM); flopenrc #(1) EMRegFma11(clk, reset, PipeClearEM, PipeEnableEM, YZeroE, YZeroM);
flopenrc #(1) EMRegFma8(clk, reset, PipeClearEM, PipeEnableEM, killprodE, killprodM); flopenrc #(1) EMRegFma12(clk, reset, PipeClearEM, PipeEnableEM, ZZeroE, ZZeroM);
flopenrc #(1) EMRegFma9(clk, reset, PipeClearEM, PipeEnableEM, prodofE, prodofM); flopenrc #(1) EMRegFma16(clk, reset, PipeClearEM, PipeEnableEM, XInfE, XInfM);
flopenrc #(1) EMRegFma10(clk, reset, PipeClearEM, PipeEnableEM, xzeroE, xzeroM); flopenrc #(1) EMRegFma17(clk, reset, PipeClearEM, PipeEnableEM, YInfE, YInfM);
flopenrc #(1) EMRegFma11(clk, reset, PipeClearEM, PipeEnableEM, yzeroE, yzeroM); flopenrc #(1) EMRegFma18(clk, reset, PipeClearEM, PipeEnableEM, ZInfE, ZInfM);
flopenrc #(1) EMRegFma12(clk, reset, PipeClearEM, PipeEnableEM, zzeroE, zzeroM); flopenrc #(1) EMRegFma19(clk, reset, PipeClearEM, PipeEnableEM, XNaNE, XNaNM);
flopenrc #(1) EMRegFma13(clk, reset, PipeClearEM, PipeEnableEM, xdenormE, xdenormM); flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM);
flopenrc #(1) EMRegFma14(clk, reset, PipeClearEM, PipeEnableEM, ydenormE, ydenormM); flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM);
flopenrc #(1) EMRegFma15(clk, reset, PipeClearEM, PipeEnableEM, zdenormE, zdenormM);
flopenrc #(1) EMRegFma16(clk, reset, PipeClearEM, PipeEnableEM, xinfE, xinfM); //*****************
flopenrc #(1) EMRegFma17(clk, reset, PipeClearEM, PipeEnableEM, yinfE, yinfM); // fpdiv E/M pipe registers
flopenrc #(1) EMRegFma18(clk, reset, PipeClearEM, PipeEnableEM, zinfE, zinfM); //*****************
flopenrc #(1) EMRegFma19(clk, reset, PipeClearEM, PipeEnableEM, xnanE, xnanM); flopenrc #(64) EMRegDiv1(clk, reset, PipeClearEM, PipeEnableEM, FDivResultE, FDivResultM);
flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, ynanE, ynanM); flopenrc #(5) EMRegDiv2(clk, reset, PipeClearEM, PipeEnableEM, FDivFlagsE, FDivFlagsM);
flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, znanE, znanM); flopenrc #(1) EMRegDiv3(clk, reset, PipeClearEM, PipeEnableEM, DivDenormE, DivDenormM);
flopenrc #(1) EMRegFma22(clk, reset, PipeClearEM, PipeEnableEM, nanE, nanM);
flopenrc #(9) EMRegFma23(clk, reset, PipeClearEM, PipeEnableEM, sumshiftE, sumshiftM);
flopenrc #(1) EMRegFma24(clk, reset, PipeClearEM, PipeEnableEM, sumshiftzeroE, sumshiftzeroM);
flopenrc #(1) EMRegFma25(clk, reset, PipeClearEM, PipeEnableEM, prodinfE, prodinfM);
//***************** //*****************
// fpadd E/M pipe registers // fpadd E/M pipe registers

4
wally-pipelined/src/fpu/fpuhazard.sv
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@ -29,7 +29,7 @@ module fpuhazard(
input logic [4:0] Adr1, Adr2, Adr3, input logic [4:0] Adr1, Adr2, Adr3,
input logic FWriteEnE, FWriteEnM, FWriteEnW, input logic FWriteEnE, FWriteEnM, FWriteEnW,
input logic [4:0] RdE, RdM, RdW, input logic [4:0] RdE, RdM, RdW,
input logic DivBusyM, input logic FDivBusyE,
input logic RegWriteD, input logic RegWriteD,
input logic [2:0] FResultSelD, FResultSelE, input logic [2:0] FResultSelD, FResultSelE,
input logic IllegalFPUInstrD, input logic IllegalFPUInstrD,
@ -46,7 +46,7 @@ module fpuhazard(
FForwardInput1D = 2'b00; FForwardInput1D = 2'b00;
FForwardInput2D = 2'b00; FForwardInput2D = 2'b00;
FForwardInput3D = 1'b0; FForwardInput3D = 1'b0;
FStallD = DivBusyM; FStallD = FDivBusyE;
if (~IllegalFPUInstrD) begin if (~IllegalFPUInstrD) begin
// if taking a value from int register // if taking a value from int register
if ((Adr1 == RdE) & (FWriteEnE | ((FResultSelE == 3'b110) & RegWriteD))) if ((Adr1 == RdE) & (FWriteEnE | ((FResultSelE == 3'b110) & RegWriteD)))

4
wally-pipelined/src/fpu/fsm.sv
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@ -48,7 +48,7 @@ module fsm (done, load_rega, load_regb, load_regc,
S25=5'd25, S26=5'd26, S27=5'd27, S25=5'd25, S26=5'd26, S27=5'd27,
S28=5'd28, S29=5'd29, S30=5'd30; S28=5'd28, S29=5'd29, S30=5'd30;
always @(posedge clk) always @(negedge clk)
begin begin
if(reset==1'b1) if(reset==1'b1)
CURRENT_STATE=S0; CURRENT_STATE=S0;
@ -245,7 +245,7 @@ module fsm (done, load_rega, load_regb, load_regc,
S10: // done S10: // done
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b1; divBusy = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;

40
wally-pipelined/src/fpu/lza.sv
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@ -1,40 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: lop.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block implements a Leading One Predictor used to determine
// the normalization shift count.
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module lza(sum, normcnt, sumzero);
/////////////////////////////////////////////////////////////////////////////
input logic [163:0] sum; // sum
output logic [8:0] normcnt; // normalization shift count
output logic sumzero; // sum = 0
// Internal nodes
reg [8:0] i; // loop index
// A real LOP uses a fast carry chain to find only the first 0.
// It is an example of a parallel prefix algorithm. For the sake
// of simplicity, this model is behavioral instead.
// A real LOP would also operate on the sources of the adder, not
// the result!
always_comb
begin
i = 0;
while (~sum[163-i] && i <= 163) i = i+1; // search for leading one
normcnt = i; // compute shift count
end
// Also check if sum is zero
assign sumzero = ~(|sum);
endmodule

138
wally-pipelined/src/fpu/multiply.sv
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@ -1,138 +0,0 @@
module multiply(xman, yman, xdenormE, ydenormE, xzeroE, yzeroE, rE, sE);
/////////////////////////////////////////////////////////////////////////////
input logic [51:0] xman; // Fraction of multiplicand x
input logic [51:0] yman; // Fraction of multiplicand y
input logic xdenormE; // is x denormalized
input logic ydenormE; // is y denormalized
input logic xzeroE; // Z is denorm
input logic yzeroE; // Z is denorm
output logic [105:0] rE; // partial product 1
output logic [105:0] sE; // partial product 2
wire [54:0] yExt; //y with appended 0 and assumed 1
wire [53:0] xExt; //y with assumed 1
wire [26:0][1:0] add1;
wire [26:0][54:0] pp;
wire [26:0] e;
logic [106:0] tmpsE;
logic [17:0][106:0] lv1add;
logic [11:0][106:0] lv2add;
logic [7:0][106:0] lv3add;
logic [3:0][106:0] lv4add;
logic [21:0][107:0] carryTmp;
wire [26:0][106:0] acc;
// wire [105:0] acc
genvar i;
// assign xExt = {1'b0,~(xdenormE|xzeroE),xman};
// assign yExt = {1'b0,~(ydenormE|yzeroE),yman, 1'b0};
// generate
// for(i=0; i<27; i=i+1) begin
// booth booth(.xExt(xExt), .choose(yExt[(i*2)+2:i*2]), .add1(add1[i]), .e(e[i]), .pp(pp[i]));
// end
// endgenerate
// assign acc[0] = {49'b0,~e[0],e[0],e[0],pp[0]};
// assign acc[1] = {49'b01,~e[1],pp[1],add1[0]};
// assign acc[2] = {47'b01,~e[2],pp[2],add1[1], 2'b0};
// assign acc[3] = {45'b01,~e[3],pp[3],add1[2], 4'b0};
// assign acc[4] = {43'b01,~e[4],pp[4],add1[3], 6'b0};
// assign acc[5] = {41'b01,~e[5],pp[5],add1[4], 8'b0};
// assign acc[6] = {39'b01,~e[6],pp[6],add1[5], 10'b0};
// assign acc[7] = {37'b01,~e[7],pp[7],add1[6], 12'b0};
// assign acc[8] = {35'b01,~e[8],pp[8],add1[7], 14'b0};
// assign acc[9] = {33'b01,~e[9],pp[9],add1[8], 16'b0};
// assign acc[10] = {31'b01,~e[10],pp[10],add1[9], 18'b0};
// assign acc[11] = {29'b01,~e[11],pp[11],add1[10], 20'b0};
// assign acc[12] = {27'b01,~e[12],pp[12],add1[11], 22'b0};
// assign acc[13] = {25'b01,~e[13],pp[13],add1[12], 24'b0};
// assign acc[14] = {23'b01,~e[14],pp[14],add1[13], 26'b0};
// assign acc[15] = {21'b01,~e[15],pp[15],add1[14], 28'b0};
// assign acc[16] = {19'b01,~e[16],pp[16],add1[15], 30'b0};
// assign acc[17] = {17'b01,~e[17],pp[17],add1[16], 32'b0};
// assign acc[18] = {15'b01,~e[18],pp[18],add1[17], 34'b0};
// assign acc[19] = {13'b01,~e[19],pp[19],add1[18], 36'b0};
// assign acc[20] = {11'b01,~e[20],pp[20],add1[19], 38'b0};
// assign acc[21] = {9'b01,~e[21],pp[21],add1[20], 40'b0};
// assign acc[22] = {7'b01,~e[22],pp[22],add1[21], 42'b0};
// assign acc[23] = {5'b01,~e[23],pp[23],add1[22], 44'b0};
// assign acc[24] = {3'b01,~e[24],pp[24],add1[23], 46'b0};
// assign acc[25] = {1'b0, ~e[25],pp[25],add1[24], 48'b0};
// assign acc[26] = {pp[26],add1[25], 50'b0};
//***breaks lint with warnings like: %Warning-UNOPTFLAT: Example path: src/fpu/multiply.sv:86: ASSIGNW
// %Warning-UNOPTFLAT: Example path: src/fpu/multiply.sv:22: wallypipelinedsoc.hart.fpu.fma1.multiply.lv3add
//*** resize adders
// generate
// for(i=0; i<9; i=i+1) begin
// add3comp2 #(.BITS(107)) add1(.a(acc[i*3]), .b(acc[i*3+1]), .c(acc[i*3+2]),
// .carry(carryTmp[i][106:0]), .sum(lv1add[i*2+1]));
// assign lv1add[i*2] = {carryTmp[i][105:0], 1'b0};
// end
// endgenerate
// generate
// for(i=0; i<6; i=i+1) begin
// add3comp2 #(.BITS(107)) add2(.a(lv1add[i*3]), .b(lv1add[i*3+1]), .c(lv1add[i*3+2]),
// .carry(carryTmp[i+9][106:0]), .sum(lv2add[i*2+1]));
// assign lv2add[i*2] = {carryTmp[i+9][105:0], 1'b0};
// end
// endgenerate
// generate
// for(i=0; i<4; i=i+1) begin
// add3comp2 #(.BITS(107)) add3(.a(lv2add[i*3]), .b(lv2add[i*3+1]), .c(lv2add[i*3+2]),
// .carry(carryTmp[i+15][106:0]), .sum(lv3add[i*2+1]));
// assign lv3add[i*2] = {carryTmp[i+15][105:0], 1'b0};
// end
// endgenerate
// generate
// for(i=0; i<2; i=i+1) begin
// add4comp2 #(.BITS(107)) add4(.a(lv3add[i*4]), .b(lv3add[i*4+1]), .c(lv3add[i*4+2]), .d(lv3add[i*4+3]),
// .carry(carryTmp[i+19]), .sum(lv4add[i*2+1]));
// assign lv4add[i*2] = {carryTmp[i+19][105:0], 1'b0};
// end
// endgenerate
// add4comp2 #(.BITS(107)) add5(.a(lv4add[0]), .b(lv4add[1]), .c(lv4add[2]), .d(lv4add[3]) ,
// .carry(carryTmp[21]), .sum(tmpsE));
// assign sE = tmpsE[105:0];
// assign rE = {carryTmp[21][104:0], 1'b0};
// assign rE = 0;
// assign sE = acc[0] +
// acc[1] +
// acc[2] +
// acc[3] +
// acc[4] +
// acc[5] +
// acc[6] +
// acc[7] +
// acc[8] +
// acc[9] +
// acc[10] +
// acc[11] +
// acc[12] +
// acc[13] +
// acc[14] +
// acc[15] +
// acc[16] +
// acc[17] +
// acc[18] +
// acc[19] +
// acc[20] +
// acc[21] +
// acc[22] +
// acc[23] +
// acc[24] +
// acc[25] +
// acc[26];
assign sE = {53'b0,~(xdenormE|xzeroE),xman} * {53'b0,~(ydenormE|yzeroE),yman};
assign rE = 0;
endmodule

147
wally-pipelined/src/fpu/normalize.sv
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@ -1,147 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: normalize.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block performs the normalization shift. It also
// generates the Rands bits for rounding. Finally, it
// handles the special case of a zero sum.
//
// v[53:2] is the fraction component of the prerounded result.
// It can be bypassed back to the X or Z inputs of the FMAC
// for back-to-back operations.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module normalize(sum, zexp, normcnt, aeM, aligncntM, sumshiftM, sumshiftzeroM, sumzero,
xzeroM, zzeroM, yzeroM, bsM, xdenormM, ydenormM, zdenormM, sticky, de0, resultdenorm, v);
/////////////////////////////////////////////////////////////////////////////
input logic [163:0] sum; // sum
input logic [62:52] zexp; // sum
input logic [8:0] normcnt; // normalization shift count
input logic [12:0] aeM; // normalization shift count
input logic [12:0] aligncntM; // normalization shift count
input logic [8:0] sumshiftM; // normalization shift count
input logic sumshiftzeroM;
input logic sumzero; // sum is zero
input logic bsM; // sticky bit for addend
input logic xdenormM; // Input Z is denormalized
input logic ydenormM; // Input Z is denormalized
input logic zdenormM; // Input Z is denormalized
input logic xzeroM;
input logic yzeroM;
input logic zzeroM;
output logic sticky; //sticky bit
output logic [12:0] de0;
output logic resultdenorm; // Input Z is denormalized
output logic [53:0] v; // normalized sum, R, S bits
// Internal nodes
logic [163:0] sumshifted; // shifted sum
logic [9:0] sumshifttmp;
logic [163:0] sumshiftedtmp; // shifted sum
logic isShiftLeft1;
logic tmp,tmp1,tmp2,tmp3,tmp4, tmp5;
// When the sum is zero, normalization does not apply and only the
// sticky bit must be computed. Otherwise, the sum is right-shifted
// and the Rand S bits (v[1] and v[O], respectively) are assigned.
// The R bit is also set on denormalized numbers where the exponent
// was computed to be exactly -1023 and the L bit was set. This
// is required for correct rounding up of multiplication results.
// The sticky bit calculation is actually built into the shifter and
// does not require a true subtraction shown in the model.
assign isShiftLeft1 = (aligncntM == 13'b1 ||aligncntM == 13'b0 || $signed(aligncntM) == $signed(-(13'b1)))&& zexp == 11'h2;
// assign tmp = ($signed(aeM-normcnt+2) >= $signed(-1022));
always_comb
begin
// d = aligncntM
// l = normcnt
// p = 53
// ea + eb = aeM
// set d<=2 to d<=0
if ($signed(aligncntM)<=$signed(13'd2)) begin //d<=2
// product anchored or cancellation
if ($signed(aeM-{{4{normcnt[8]}},normcnt}+13'd2) >= $signed(-(13'd1022))) begin //ea+eb-l+2 >= emin
//normal result
de0 = xzeroM|yzeroM ? {2'b0,zexp} : aeM-{{4{normcnt[8]}},normcnt}+{12'b0,xdenormM}+{12'b0,ydenormM}+13'd57;
resultdenorm = |sum & ~|de0 | de0[12];
// if z is zero then there was a 56 bit shift of the product
sumshifted = resultdenorm ? sum << sumshiftM-{8'b0,zzeroM}+{8'b0,isShiftLeft1} : sum << normcnt; // p+2+l
v = sumshifted[162:109];
sticky = (|sumshifted[108:0]) | bsM;
//de0 = aeM-normcnt+2-1023;
end else begin
sumshifted = sum << (13'd1080+aeM);
v = sumshifted[162:109];
sticky = (|sumshifted[108:0]) | bsM;
resultdenorm = 1;
de0 = 0;
end
end else begin // extract normalized bits
sumshifttmp = {1'b0,sumshiftM} - 2;
sumshifted = sumshifttmp[9] ? sum : sum << sumshifttmp;
tmp1 = (sumshifted[163] & ~sumshifttmp[9]);
tmp2 = ((sumshifttmp[9] & sumshiftM[0]) || sumshifted[162]);
tmp3 = (sumshifted[161] || (sumshifttmp[9] & sumshiftM[1]));
tmp4 = sumshifted[160];
tmp5 = sumshifted[159];
// for some reason use exp = zexp + {0,1,2}
// the book says exp = zexp + {-1,0,1}
if(sumshiftzeroM) begin
v = sum[162:109];
sticky = (|sum[108:0]) | bsM;
de0 = {2'b0,zexp};
end else if(sumshifted[163] & ~sumshifttmp[9])begin
v = sumshifted[162:109];
sticky = (|sumshifted[108:0]) | bsM;
de0 = {2'b0,zexp} +13'd2;
end else if ((sumshifttmp[9] & sumshiftM[0]) || sumshifted[162]) begin
v = sumshifted[161:108];
sticky = (|sumshifted[107:0]) | bsM;
de0 = {2'b0,zexp}+13'd1;
end else if (sumshifted[161] || (sumshifttmp[9] & sumshiftM[1])) begin
v = sumshifted[160:107];
sticky = (|sumshifted[106:0]) | bsM;
//de0 = zexp-1;
de0 = {2'b0,zexp}+{12'b0,zdenormM};
end else if(sumshifted[160]& ~zdenormM) begin
de0 = {2'b0,zexp}-13'b1;
v = ~|de0&~sumzero ? sumshifted[160:107] : sumshifted[159:106];
sticky = (|sumshifted[105:0]) | bsM;
//de0 = zexp-1;
end else if(sumshifted[159]& ~zdenormM) begin
//v = sumshifted[158:105];
de0 = {2'b0,zexp}-13'd2;
v = (~|de0 | de0[12])&~sumzero ? sumshifted[161:108] : sumshifted[158:105];
sticky = (|sumshifted[104:0]) | bsM;
//de0 = zexp-1;
end else if(zdenormM) begin
v = sumshifted[160:107];
sticky = (|sumshifted[106:0]) | bsM;
//de0 = zexp-1;
de0 = {{2{zexp[62]}},zexp};
end else begin
de0 = 0;
sumshifted = sum << sumshiftM-1; // p+2+l
v = sumshifted[162:109];
sticky = (|sumshifted[108:0]) | bsM;
end
resultdenorm = (~|de0 | de0[12]);
end
end
// shift sum left by normcnt, filling the right with zeros
//assign sumshifted = sum << normcnt;
endmodule

122
wally-pipelined/src/fpu/round.sv
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@ -1,122 +0,0 @@
/////////////////////////////////////////////////////////////////////////////
// Block Name: round.v
// Author: David Harris
// Date: 11/2/1995
//
// Block Description:
// This block is responsible for rounding the normalized result of // the FMAC. Because prenormalized results may be bypassed back to // the FMAC X and z input logics, rounding does not appear in the critical // path of most floating point code. This is good because rounding // requires an entire 52 bit carry-propagate half-adder delay.
//
// The results from other FPU blocks (e.g. FCVT, FDIV, etc) are also
// muxed in to form the actual result for register file writeback. This
// saves a mux from the writeback path.
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module round(v, sticky, FrmM, wsign,
FmaFlagsM, inf, nanM, xnanM, ynanM, znanM,
xman, yman, zman,
wman, infinity, specialsel,expplus1);
/////////////////////////////////////////////////////////////////////////////
input logic [53:0] v; // normalized sum, R, S bits
input logic sticky; //sticky bit
input logic [2:0] FrmM;
input logic wsign; // Sign of result
input logic [4:0] FmaFlagsM;
input logic inf; // Some input logic is infinity
input logic nanM; // Some input logic is NaN
input logic xnanM; // X is NaN
input logic ynanM; // Y is NaN
input logic znanM; // Z is NaN
input logic [51:0] xman; // input logic X
input logic [51:0] yman; // input logic Y
input logic [51:0] zman; // input logic Z
output logic [51:0] wman; // rounded result of FMAC
output logic infinity; // Generate infinity on overflow
output logic specialsel; // Select special result
output logic expplus1;
// Internal nodes
logic plus1; // Round by adding one
wire [52:0] v1; // Result + 1 (for rounding)
wire [51:0] specialres; // Result of exceptional case
wire [51:0] infinityres; // Infinity or largest real number
wire [51:0] nanres; // Propagated or generated NaN
// Compute if round should occur. This equation is derived from
// the rounding tables.
// round to infinity - plus1 if positive
// round to -infinity - plus1 if negitive
// round to zero - do nothing
// round to nearest even
// {v[1], v[0], sticky}
// 0xx - do nothing
// 100 - tie - plus1 if v[2] = 1
// 101/110/111 - plus1
//***causes lint warning: %Warning-UNOPTFLAT: Example path: src/fpu/round.sv:59: ALWAYS
// %Warning-UNOPTFLAT: Example path: src/fpu/round.sv:42: wallypipelinedsoc.hart.fpu.fma2.round.plus1
always_comb begin
case (FrmM)
3'b000: plus1 = (v[1] & (v[0] | sticky | (~v[0]&~sticky&v[2])));//round to nearest even
3'b001: plus1 = 0;//round to zero
3'b010: plus1 = wsign;//round down
3'b011: plus1 = ~wsign;//round up
3'b100: plus1 = (v[1] & (v[0] | sticky | (~v[0]&~sticky&~wsign)));//round to nearest max magnitude
default: plus1 = 1'bx;
endcase
end
// Compute rounded result
assign v1 = v[53:2] + 1;
// Determine if postnormalization is necessary
// Predicted by all bits =1 before round +1
//assign postnormalize = &(v[53:2]) && plus1;
// Determine special result in event of of selection of a result from
// another FPU functional unit, infinity, NAN, or underflow
// The special result mux is a 4:1 mux that should not appear in the
// critical path of the machine. It is not priority encoded, despite
// the code below suggesting otherwise. Also, several of the identical data
// input logics to the wide muxes can be combined at the expense of more
// complicated non-critical control in the circuit implementation.
assign specialsel = FmaFlagsM[2] || FmaFlagsM[1] || FmaFlagsM[4] || //overflow underflow invalid
nanM || inf;
assign specialres = FmaFlagsM[4] | nanM ? nanres : //invalid
FmaFlagsM[2] ? infinityres : //overflow
inf ? 52'b0 :
FmaFlagsM[1] ? 52'b0 : 52'bx; // underflow
// Overflow is handled differently for different rounding modes
// Round is to either infinity or to maximum finite number
assign infinity = |FrmM;//rn || (rp && ~wsign) || (rm && wsign);//***look into this
assign infinityres = infinity ? 52'b0 : {52{1'b1}};
// Invalid operations produce a quiet NaN. The result should
// propagate an input logic if the input logic is NaN. Since we assume all
// NaN input logics are already quiet, we don't have to force them quiet.
// assign nanres = xnanM ? x: (ynanM ? y : (znanM ? z : {1'b1, 51'b0})); // original
// IEEE 754-2008 section 6.2.3 states:
// "If two or more input logics are NaN, then the payload of the resulting NaN should be
// identical to the payload of one of the input logic NaNs if representable in the destination
// format. This standard does not specify which of the input logic NaNs will provide the payload."
assign nanres = xnanM ? {1'b1, xman[50:0]}: (ynanM ? {1'b1, yman[50:0]} : (znanM ? {1'b1, zman[50:0]} : {1'b1, 51'b0}));// KEP 210112 add the 1 to make NaNs quiet
// Select result with 4:1 mux
// If the sum is zero and we round up, there is a special case in
// which we produce a massive loss of significance and trap to software.
// It is handled in the exception unit.
assign expplus1 = v1[52] & ~specialsel & plus1;
assign wman = specialsel ? specialres : (plus1 ? v1[51:0] : v[53:2]);
endmodule

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wally-pipelined/src/fpu/sign.sv
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@ -1,112 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: sign.v
// Author: David Harris
// Date: 12/1/1995
//
// Block Description:
// This block manages the signs of the numbers.
// 1 = negative
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module sign(xsign, ysign, zsign, negsum0, negsum1, bsM, FrmM, FmaFlagsM,
sumzero, zinfM, inf, wsign, invz, negsum, selsum1, isAdd);
////////////////////////////////////////////////////////////////////////////I
input logic xsign; // Sign of X
input logic ysign; // Sign of Y
input logic zsign; // Sign of Z
input logic isAdd;
input logic negsum0; // Sum in +O mode is negative
input logic negsum1; // Sum in +1 mode is negative
input logic bsM; // sticky bit from addend
input logic [2:0] FrmM; // Round toward minus infinity
input logic [4:0] FmaFlagsM; // Round toward minus infinity
input logic sumzero; // Sum = O
input logic zinfM; // Y = Inf
input logic inf; // Some input logic = Inf
output logic wsign; // Sign of W
output logic invz; // Invert addend into adder
output logic negsum; // Negate result of adder
output logic selsum1; // Select +1 mode from compound adder
// Internal nodes
wire zerosign; // sign if result= 0
wire sumneg; // sign if result= 0
wire infsign; // sign if result= Inf
logic tmp;
logic psign;
// Compute sign of product
assign psign = xsign ^ ysign;
// Invert addend if sign of Z is different from sign of product assign invz = zsign ^ psign;
//do you invert z
assign invz = (zsign ^ psign);
assign selsum1 = invz;
//negate sum if its negitive
assign negsum = (selsum1&negsum1) | (~selsum1&negsum0);
// is the sum negitive
// if p - z is the sum negitive
// if -p + z is the sum positive
// if -p - z then the sum is negitive
assign sumneg = invz&zsign&negsum1 | invz&psign&~negsum1 | (zsign&psign);
//always @(invz or negsum0 or negsum1 or bsM or ps)
// begin
// if (~invz) begin // both input logics have same sign
// negsum = 0;
// selsum1 = 0;
// end else if (bsM) begin // sticky bit set on addend
// selsum1 = 0;
// negsum = negsum0;
// end else if (ps) begin // sticky bit set on product
// selsum1 = 1;
// negsum = negsum1;
// end else begin // both sticky bits clear
// //selsum1 = negsum1; // KEP 210113-10:44 Selsum1 was adding 1 to values that were multiplied by 0
// selsum1 = ~negsum1; //original
// negsum = negsum1;
// end
//end
// Compute sign of result
// This involves a special case when the sum is zero:
// x+x retains the same sign as x even when x = +/- 0.
// otherwise, x-x = +O unless in the RM mode when x-x = -0
// There is also a special case for NaNs and invalid results;
// the sign of the NaN produced is forced to be 0.
// Sign calculation is not in the critical path so the cases
// can be tolerated.
// IEEE 754-2008 section 6.3 states
// "When ether an input logic or result is NaN, this standard does not interpret the sign of a NaN."
// also pertaining to negZero it states:
// "When the sum/difference of two operands with opposite signs is exactly zero, the sign of that sum/difference
// shall be +0 in all rounding attributes EXCEPT roundTowardNegative. Under that attribute, the sign of an exact zero
// sum/difference shall be -0. However, x+x = x-(-X) retains the same sign as x even when x is zero."
//assign zerosign = (~invz && killprodM) ? zsign : rm;//***look into
// assign zerosign = (~invz && killprodM) ? zsign : 0;
// zero sign
// if product underflows then use psign
// otherwise
// addition
// if cancelation then 0 unless round to -inf
// otherwise psign
// subtraction
// if cancelation then 0 unless round to -inf
// otherwise psign
assign zerosign = FmaFlagsM[1] ? psign :
(isAdd ? (psign^zsign ? FrmM == 3'b010 : psign) :
(psign^zsign ? psign : FrmM == 3'b010));
assign infsign = zinfM ? zsign : psign; //KEP 210112 keep the correct sign when result is infinity
//assign infsign = xinfM ? (yinfM ? psign : xsign) : yinfM ? ysign : zsign;//original
assign tmp = FmaFlagsM[4] ? 0 : (inf ? infsign :(sumzero ? zerosign : psign ^ negsum));
assign wsign = FmaFlagsM[4] ? 0 : (inf ? infsign :(sumzero ? zerosign : sumneg));
endmodule

67
wally-pipelined/src/fpu/special.sv
View File

@ -1,67 +0,0 @@
///////////////////////////////////////////////////////////////////////////////
// Block Name: special.v
// Author: David Harris
// Date: 12/2/1995
//
// Block Description:
// This block implements special case handling for unusual operands (e.g.
// 0, NaN, denormalize, infinity). The block consists of zero/one detectors.
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
module special(FInput1E, FInput2E, FInput3E, xzeroE, yzeroE, zzeroE,
xnanE, ynanE, znanE, xdenormE, ydenormE, zdenormE, xinfE, yinfE, zinfE);
/////////////////////////////////////////////////////////////////////////////
input logic [63:0] FInput1E; // Input FInput1E
input logic [63:0] FInput2E; // Input FInput2E
input logic [63:0] FInput3E; // Input FInput3E
output logic xzeroE; // Input FInput1E = 0
output logic yzeroE; // Input FInput2E = 0
output logic zzeroE; // Input FInput3E = 0
output logic xnanE; // FInput1E is NaN
output logic ynanE; // FInput2E is NaN
output logic znanE; // FInput3E is NaN
output logic xdenormE; // FInput1E is denormalized
output logic ydenormE; // FInput2E is denormalized
output logic zdenormE; // FInput3E is denormalized
output logic xinfE; // FInput1E is infinity
output logic yinfE; // FInput2E is infinity
output logic zinfE; // FInput3E is infinity
// In the actual circuit design, the gates looking at bits
// 51:0 and at bits 62:52 should be shared among the various detectors.
// Check if input is NaN
assign xnanE = &FInput1E[62:52] && |FInput1E[51:0];
assign ynanE = &FInput2E[62:52] && |FInput2E[51:0];
assign znanE = &FInput3E[62:52] && |FInput3E[51:0];
// Check if input is denormalized
assign xdenormE = ~(|FInput1E[62:52]) && |FInput1E[51:0];
assign ydenormE = ~(|FInput2E[62:52]) && |FInput2E[51:0];
assign zdenormE = ~(|FInput3E[62:52]) && |FInput3E[51:0];
// Check if input is infinity
assign xinfE = &FInput1E[62:52] && ~(|FInput1E[51:0]);
assign yinfE = &FInput2E[62:52] && ~(|FInput2E[51:0]);
assign zinfE = &FInput3E[62:52] && ~(|FInput3E[51:0]);
// Check if inputs are all zero
// Also forces denormalized inputs to zero.
// In the circuit implementation, this can be optimized
// to just check if the exponent is zero.
// KATHERINE - commented following (21/01/11)
// assign xzeroE = ~(|FInput1E[62:0]) || xdenormE;
// assign yzeroE = ~(|FInput2E[62:0]) || ydenormE;
// assign zzeroE = ~(|FInput3E[62:0]) || zdenormE;
// KATHERINE - removed denorm to prevent output logicing zero when computing with a denormalized number
assign xzeroE = ~(|FInput1E[62:0]);
assign yzeroE = ~(|FInput2E[62:0]);
assign zzeroE = ~(|FInput3E[62:0]);
endmodule

26
wally-pipelined/src/generic/lzd.sv
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@ -44,7 +44,7 @@ module lzd2 (P, V, B);
assign V = B[0] | B[1]; assign V = B[0] | B[1];
assign P = B[0] & ~B[1]; assign P = B[0] & ~B[1];
endmodule // lz2 endmodule // lzd2
module lzd_hier #(parameter WIDTH=8) module lzd_hier #(parameter WIDTH=8)
(input logic [WIDTH-1:0] B, (input logic [WIDTH-1:0] B,
@ -78,8 +78,8 @@ module lzd4 (ZP, ZV, B);
output logic [1:0] ZP; output logic [1:0] ZP;
output logic ZV; output logic ZV;
lz2 l1(ZPa, ZVa, B[1:0]); lzd2 l1(ZPa, ZVa, B[1:0]);
lz2 l2(ZPb, ZVb, B[3:2]); lzd2 l2(ZPb, ZVb, B[3:2]);
assign ZP[0:0] = ZVb ? ZPb : ZPa; assign ZP[0:0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb; assign ZP[1] = ~ZVb;
@ -99,8 +99,8 @@ module lzd8 (ZP, ZV, B);
output logic [2:0] ZP; output logic [2:0] ZP;
output logic ZV; output logic ZV;
lz4 l1(ZPa, ZVa, B[3:0]); lzd4 l1(ZPa, ZVa, B[3:0]);
lz4 l2(ZPb, ZVb, B[7:4]); lzd4 l2(ZPb, ZVb, B[7:4]);
assign ZP[1:0] = ZVb ? ZPb : ZPa; assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb; assign ZP[2] = ~ZVb;
@ -120,8 +120,8 @@ module lzd16 (ZP, ZV, B);
output logic [3:0] ZP; output logic [3:0] ZP;
output logic ZV; output logic ZV;
lz8 l1(ZPa, ZVa, B[7:0]); lzd8 l1(ZPa, ZVa, B[7:0]);
lz8 l2(ZPb, ZVb, B[15:8]); lzd8 l2(ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa; assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb; assign ZP[3] = ~ZVb;
@ -141,8 +141,8 @@ module lzd32 (ZP, ZV, B);
output logic [4:0] ZP; output logic [4:0] ZP;
output logic ZV; output logic ZV;
lz16 l1(ZPa, ZVa, B[15:0]); lzd16 l1(ZPa, ZVa, B[15:0]);
lz16 l2(ZPb, ZVb, B[31:16]); lzd16 l2(ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa; assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb; assign ZP[4] = ~ZVb;
@ -162,8 +162,8 @@ module lzd64 (ZP, ZV, B);
output logic [5:0] ZP; output logic [5:0] ZP;
output logic ZV; output logic ZV;
lz32 l1(ZPa, ZVa, B[31:0]); lzd32 l1(ZPa, ZVa, B[31:0]);
lz32 l2(ZPb, ZVb, B[63:32]); lzd32 l2(ZPb, ZVb, B[63:32]);
assign ZP[4:0] = ZVb ? ZPb : ZPa; assign ZP[4:0] = ZVb ? ZPb : ZPa;
assign ZP[5] = ~ZVb; assign ZP[5] = ~ZVb;
@ -183,8 +183,8 @@ module lzd128 (ZP, ZV, B);
output logic [6:0] ZP; output logic [6:0] ZP;
output logic ZV; output logic ZV;
lz64 l1(ZPa, ZVa, B[64:0]); lzd64 l1(ZPa, ZVa, B[64:0]);
lz64 l2(ZPb, ZVb, B[127:63]); lzd64 l2(ZPb, ZVb, B[127:63]);
assign ZP[5:0] = ZVb ? ZPb : ZPa; assign ZP[5:0] = ZVb ? ZPb : ZPa;
assign ZP[6] = ~ZVb; assign ZP[6] = ~ZVb;

4
wally-pipelined/src/hazard/hazard.sv
View File

@ -33,7 +33,7 @@ module hazard(
input logic LoadStallD, MulDivStallD, CSRRdStallD, input logic LoadStallD, MulDivStallD, CSRRdStallD,
input logic DataStall, ICacheStallF, input logic DataStall, ICacheStallF,
input logic FPUStallD, input logic FPUStallD,
input logic DivBusyE, input logic DivBusyE,FDivBusyE,
// Stall & flush outputs // Stall & flush outputs
output logic StallF, StallD, StallE, StallM, StallW, output logic StallF, StallD, StallE, StallM, StallW,
output logic FlushF, FlushD, FlushE, FlushM, FlushW output logic FlushF, FlushD, FlushE, FlushM, FlushW
@ -57,7 +57,7 @@ module hazard(
assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE); assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE);
assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE; assign StallECause = DivBusyE | FDivBusyE;
assign StallMCause = 0; assign StallMCause = 0;
assign StallWCause = DataStall || ICacheStallF; assign StallWCause = DataStall || ICacheStallF;

104
wally-pipelined/src/ifu/icacheMem.sv
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@ -1,104 +0,0 @@
`include "wally-config.vh"
module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, parameter WORDSIZE = `XLEN) (
// Pipeline stuff
input logic clk,
input logic reset,
// If flush is high, invalidate the entire cache
input logic flush,
// Select which address to read (broken for efficiency's sake)
input logic [`XLEN-1:0] PCTagF, // physical tag address
input logic [`XLEN-1:0] PCNextIndexF,
// Write new data to the cache
input logic WriteEnable,
input logic [LINESIZE-1:0] WriteLine,
// Output the word, as well as if it is valid
output logic [31:0] DataWord, // *** was WORDSIZE-1
output logic DataValid
);
// Various compile-time constants
localparam integer WORDWIDTH = $clog2(WORDSIZE/8);
localparam integer OFFSETWIDTH = $clog2(LINESIZE/WORDSIZE);
localparam integer SETWIDTH = $clog2(NUMLINES);
localparam integer TAGWIDTH = `XLEN - OFFSETWIDTH - SETWIDTH - WORDWIDTH;
localparam integer OFFSETBEGIN = WORDWIDTH;
localparam integer OFFSETEND = OFFSETBEGIN+OFFSETWIDTH-1;
localparam integer SETBEGIN = OFFSETEND+1;
localparam integer SETEND = SETBEGIN + SETWIDTH - 1;
localparam integer TAGBEGIN = SETEND + 1;
localparam integer TAGEND = TAGBEGIN + TAGWIDTH - 1;
// Machinery to read from and write to the correct addresses in memory
logic [LINESIZE-1:0] ReadLine;
logic [LINESIZE/WORDSIZE-1:0][WORDSIZE-1:0] ReadLineTransformed;
// Machinery to check if a given read is valid and is the desired value
logic [TAGWIDTH-1:0] DataTag;
logic [NUMLINES-1:0] ValidOut;
logic DataValidBit;
// Depth is number of bits in one "word" of the memory, width is number of such words
sram1rw #(.DEPTH(LINESIZE), .WIDTH(NUMLINES)) cachemem (
.*,
.Addr(PCNextIndexF[SETEND:SETBEGIN]),
.ReadData(ReadLine),
.WriteData(WriteLine)
);
sram1rw #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags (
.*,
.Addr(PCNextIndexF[SETEND:SETBEGIN]),
.ReadData(DataTag),
.WriteData(PCTagF[TAGEND:TAGBEGIN])
);
// Pick the right bits coming out the read line
//assign DataWord = ReadLineTransformed[ReadOffset];
//logic [31:0] tempRD;
always_comb begin
case (PCTagF[4:1])
0: DataWord = ReadLine[31:0];
1: DataWord = ReadLine[47:16];
2: DataWord = ReadLine[63:32];
3: DataWord = ReadLine[79:48];
4: DataWord = ReadLine[95:64];
5: DataWord = ReadLine[111:80];
6: DataWord = ReadLine[127:96];
7: DataWord = ReadLine[143:112];
8: DataWord = ReadLine[159:128];
9: DataWord = ReadLine[175:144];
10: DataWord = ReadLine[191:160];
11: DataWord = ReadLine[207:176];
12: DataWord = ReadLine[223:192];
13: DataWord = ReadLine[239:208];
14: DataWord = ReadLine[255:224];
15: DataWord = {16'b0, ReadLine[255:240]};
endcase
end
genvar i;
generate
for (i=0; i < LINESIZE/WORDSIZE; i++) begin
assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
end
endgenerate
// Correctly handle the valid bits
always_ff @(posedge clk, posedge reset) begin
if (reset) begin
ValidOut <= {NUMLINES{1'b0}};
end else if (flush) begin
ValidOut <= {NUMLINES{1'b0}};
end else begin
if (WriteEnable) begin
ValidOut[PCNextIndexF[SETEND:SETBEGIN]] <= 1;
end
end
DataValidBit <= ValidOut[PCNextIndexF[SETEND:SETBEGIN]];
end
assign DataValid = DataValidBit && (DataTag == PCTagF[TAGEND:TAGBEGIN]);
endmodule

28
wally-pipelined/src/ifu/ifu.sv
View File

@ -63,14 +63,29 @@ module ifu (
output logic IllegalIEUInstrFaultD, output logic IllegalIEUInstrFaultD,
output logic InstrMisalignedFaultM, output logic InstrMisalignedFaultM,
output logic [`XLEN-1:0] InstrMisalignedAdrM, output logic [`XLEN-1:0] InstrMisalignedAdrM,
// TLB management
// mmu management
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] PageTableEntryF, input logic [`XLEN-1:0] PageTableEntryF,
input logic [1:0] PageTypeF, input logic [1:0] PageTypeF,
input logic [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM, input logic STATUS_MXR, STATUS_SUM,
input logic ITLBWriteF, ITLBFlushF, input logic ITLBWriteF, ITLBFlushF,
output logic ITLBMissF, ITLBHitF output logic ITLBMissF, ITLBHitF,
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
input logic [31:0] HADDR,
input logic [2:0] HSIZE, HBURST,
input logic HWRITE,
input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage.
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF,
output logic ISquashBusAccessF,
output logic [5:0] IHSELRegionsF
); );
logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; logic [`XLEN-1:0] UnalignedPCNextF, PCNextF;
@ -85,14 +100,21 @@ module ifu (
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage
// if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
.TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),
.AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else?
.SquashBusAccess(ISquashBusAccessF), .HSELRegions(IHSELRegionsF),
.*); .*);
// branch predictor signals // branch predictor signals
logic SelBPPredF; logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F; logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F;

2
wally-pipelined/src/mmu/cam_line.sv
View File

@ -32,7 +32,7 @@ module cam_line #(parameter KEY_BITS = 20,
parameter HIGH_SEGMENT_BITS = 10) ( parameter HIGH_SEGMENT_BITS = 10) (
input clk, reset, input clk, reset,
// input to scheck which SvMode is running // input to check which SvMode is running
input [`SVMODE_BITS-1:0] SvMode, input [`SVMODE_BITS-1:0] SvMode,
// The requested page number to compare against the key // The requested page number to compare against the key

98
wally-pipelined/src/mmu/mmu.sv Normal file
View File

@ -0,0 +1,98 @@
///////////////////////////////////////////
// mmu.sv
//
// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
// Modified:
//
// Purpose: Memory management unit, including TLB, PMA, PMP
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
// The TLB will have 2**ENTRY_BITS total entries
module mmu #(parameter ENTRY_BITS = 3,
parameter IMMU = 0) (
input logic clk, reset,
// Current value of satp CSR (from privileged unit)
input logic [`XLEN-1:0] SATP_REGW,
input logic STATUS_MXR, STATUS_SUM,
// Current privilege level of the processeor
input logic [1:0] PrivilegeModeW,
// 00 - TLB is not being accessed
// 1x - TLB is accessed for a read (or an instruction)
// x1 - TLB is accessed for a write
// 11 - TLB is accessed for both read and write
input logic [1:0] TLBAccessType,
// Virtual address input
input logic [`XLEN-1:0] VirtualAddress,
// Controls for writing a new entry to the TLB
input logic [`XLEN-1:0] PageTableEntryWrite,
input logic [1:0] PageTypeWrite,
input logic TLBWrite,
// Invalidate all TLB entries
input logic TLBFlush,
// Physical address outputs
output logic [`XLEN-1:0] PhysicalAddress,
output logic TLBMiss,
output logic TLBHit,
// Faults
output logic TLBPageFault,
// PMA checker signals
input logic [31:0] HADDR,
input logic [2:0] HSIZE, HBURST,
input logic HWRITE,
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
input logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
output logic SquashBusAccess, // *** send to privileged unit
output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,
output logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM,
output logic [5:0] HSELRegions
);
logic PMPSquashBusAccess, PMASquashBusAccess;
logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
// Translation lookaside buffer
tlb #(.ENTRY_BITS(ENTRY_BITS), .ITLB(IMMU)) tlb(.*);
///////////////////////////////////////////
// Check physical memory accesses
///////////////////////////////////////////
pmachecker pmachecker(.*);
pmpchecker pmpchecker(.*);
assign SquashBusAccess = PMASquashBusAccess || PMPSquashBusAccess;
endmodule

2
wally-pipelined/src/privileged/pmachecker.sv → wally-pipelined/src/mmu/pmachecker.sv
View File

@ -66,7 +66,7 @@ module pmachecker (
assign ValidBootTim = '1; assign ValidBootTim = '1;
assign ValidTim = '1; assign ValidTim = '1;
assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011) || (HSIZE == 3'b010)); assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011 && `XLEN==64) || (HSIZE == 3'b010 && `XLEN==32));
assign ValidGPIO = ~ExecuteAccessF && (HSIZE == 3'b010); assign ValidGPIO = ~ExecuteAccessF && (HSIZE == 3'b010);
assign ValidUART = ~ExecuteAccessF && (HSIZE == 3'b000); assign ValidUART = ~ExecuteAccessF && (HSIZE == 3'b000);
assign ValidPLIC = ~ExecuteAccessF && (HSIZE == 3'b010); assign ValidPLIC = ~ExecuteAccessF && (HSIZE == 3'b010);

0
wally-pipelined/src/privileged/pmpadrdec.sv → wally-pipelined/src/mmu/pmpadrdec.sv
View File

4
wally-pipelined/src/privileged/pmpchecker.sv → wally-pipelined/src/mmu/pmpchecker.sv
View File

@ -27,6 +27,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module pmpchecker ( module pmpchecker (
input logic clk, reset, input logic clk, reset,
@ -35,9 +36,6 @@ module pmpchecker (
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [1:0] STATUS_MPP,
input logic STATUS_MPRV,
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
// *** ModelSim has a switch -svinputport which controls whether input ports // *** ModelSim has a switch -svinputport which controls whether input ports

30
wally-pipelined/src/mmu/tlb.sv
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@ -51,39 +51,39 @@
// The TLB will have 2**ENTRY_BITS total entries // The TLB will have 2**ENTRY_BITS total entries
module tlb #(parameter ENTRY_BITS = 3, module tlb #(parameter ENTRY_BITS = 3,
parameter ITLB = 0) ( parameter ITLB = 0) (
input clk, reset, input logic clk, reset,
// Current value of satp CSR (from privileged unit) // Current value of satp CSR (from privileged unit)
input [`XLEN-1:0] SATP_REGW, input logic [`XLEN-1:0] SATP_REGW,
input STATUS_MXR, STATUS_SUM, input logic STATUS_MXR, STATUS_SUM,
// Current privilege level of the processeor // Current privilege level of the processeor
input [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
// 00 - TLB is not being accessed // 00 - TLB is not being accessed
// 1x - TLB is accessed for a read (or an instruction) // 1x - TLB is accessed for a read (or an instruction)
// x1 - TLB is accessed for a write // x1 - TLB is accessed for a write
// 11 - TLB is accessed for both read and write // 11 - TLB is accessed for both read and write
input [1:0] TLBAccessType, input logic [1:0] TLBAccessType,
// Virtual address input // Virtual address input
input [`XLEN-1:0] VirtualAddress, input logic [`XLEN-1:0] VirtualAddress,
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
input [`XLEN-1:0] PageTableEntryWrite, input logic [`XLEN-1:0] PageTableEntryWrite,
input [1:0] PageTypeWrite, input logic [1:0] PageTypeWrite,
input TLBWrite, input logic TLBWrite,
// Invalidate all TLB entries // Invalidate all TLB entries
input TLBFlush, input logic TLBFlush,
// Physical address outputs // Physical address outputs
output [`XLEN-1:0] PhysicalAddress, output logic [`XLEN-1:0] PhysicalAddress,
output TLBMiss, output logic TLBMiss,
output TLBHit, output logic TLBHit,
// Faults // Faults
output TLBPageFault output logic TLBPageFault
); );
logic Translate; logic Translate;
@ -143,7 +143,7 @@ module tlb #(parameter ENTRY_BITS = 3,
assign PageOffset = VirtualAddress[11:0]; assign PageOffset = VirtualAddress[11:0];
// TLB entries are evicted according to the LRU algorithm // TLB entries are evicted according to the LRU algorithm
tlb_lru lru(.*); tlb_lru #(ENTRY_BITS) lru(.*);
tlb_ram #(ENTRY_BITS) tlb_ram(.*); tlb_ram #(ENTRY_BITS) tlb_ram(.*);
tlb_cam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlb_cam(.*); tlb_cam #(ENTRY_BITS, `VPN_BITS, `VPN_SEGMENT_BITS) tlb_cam(.*);

1
wally-pipelined/src/privileged/csr.sv
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@ -26,6 +26,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module csr #(parameter module csr #(parameter
// Constants // Constants

1
wally-pipelined/src/privileged/csrc.sv
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@ -28,6 +28,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module csrc ( module csrc (
input logic clk, reset, input logic clk, reset,

1
wally-pipelined/src/privileged/csrsr.sv
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@ -25,6 +25,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module csrsr ( module csrsr (
input logic clk, reset, StallW, input logic clk, reset, StallW,

1
wally-pipelined/src/privileged/privdec.sv
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@ -25,6 +25,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module privdec ( module privdec (
input logic [31:20] InstrM, input logic [31:20] InstrM,

41
wally-pipelined/src/privileged/privileged.sv
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@ -25,7 +25,9 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
// *** remove signals not needed by PMA/PMP now that it is moved
module privileged ( module privileged (
input logic clk, reset, input logic clk, reset,
input logic FlushW, input logic FlushW,
@ -52,21 +54,24 @@ module privileged (
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
// Trap signals from pmp/pma in mmu
// *** do these need to be split up into one for dmem and one for ifu?
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
input logic PMAInstrAccessFaultF, PMPInstrAccessFaultF,
input logic PMALoadAccessFaultM, PMPLoadAccessFaultM,
input logic PMAStoreAccessFaultM, PMPStoreAccessFaultM,
output logic IllegalFPUInstrE, output logic IllegalFPUInstrE,
output logic [1:0] PrivilegeModeW, output logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] SATP_REGW, output logic [`XLEN-1:0] SATP_REGW,
output logic STATUS_MXR, STATUS_SUM, output logic STATUS_MXR, STATUS_SUM,
output logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW,
output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], //*** to be sent up through wallypipelinedhart into the pma/pmp in ifu and dmem. *** is it a bad idea to have this huge bus running all over?
output logic [2:0] FRM_REGW, output logic [2:0] FRM_REGW,
input logic FlushD, FlushE, FlushM, StallD, StallW, StallE, StallM, input logic FlushD, FlushE, FlushM, StallD, StallW, StallE, StallM
// PMA checker signals
input logic [31:0] HADDR,
input logic [2:0] HSIZE, HBURST,
input logic HWRITE,
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
output logic Cacheable, Idempotent, AtomicAllowed,
output logic SquashBusAccess,
output logic [5:0] HSELRegions
); );
logic [1:0] NextPrivilegeModeM; logic [1:0] NextPrivilegeModeM;
@ -91,18 +96,11 @@ module privileged (
logic InterruptM; logic InterruptM;
logic [1:0] STATUS_MPP; logic [1:0] STATUS_MPP;
logic STATUS_SPP, STATUS_TSR; logic STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it?
logic STATUS_MIE, STATUS_SIE; logic STATUS_MIE, STATUS_SIE;
logic STATUS_MPRV;
logic [11:0] MIP_REGW, MIE_REGW; logic [11:0] MIP_REGW, MIE_REGW;
logic md, sd; logic md, sd;
logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW;
logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15];
logic PMASquashBusAccess, PMPSquashBusAccess;
logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
/////////////////////////////////////////// ///////////////////////////////////////////
// track the current privilege level // track the current privilege level
@ -143,13 +141,6 @@ module privileged (
csr csr(.*); csr csr(.*);
///////////////////////////////////////////
// Check physical memory accesses
///////////////////////////////////////////
pmachecker pmachecker(.*);
pmpchecker pmpchecker(.*);
/////////////////////////////////////////// ///////////////////////////////////////////
// Extract exceptions by name and handle them // Extract exceptions by name and handle them
/////////////////////////////////////////// ///////////////////////////////////////////
@ -169,8 +160,6 @@ module privileged (
assign LoadAccessFaultM = PMALoadAccessFaultM || PMPLoadAccessFaultM; assign LoadAccessFaultM = PMALoadAccessFaultM || PMPLoadAccessFaultM;
assign StoreAccessFaultM = PMAStoreAccessFaultM || PMPStoreAccessFaultM; assign StoreAccessFaultM = PMAStoreAccessFaultM || PMPStoreAccessFaultM;
assign SquashBusAccess = PMASquashBusAccess || PMPSquashBusAccess;
// pipeline fault signals // pipeline fault signals
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
{InstrPageFaultF, InstrAccessFaultF}, {InstrPageFaultF, InstrAccessFaultF},

1
wally-pipelined/src/privileged/trap.sv
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@ -25,6 +25,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module trap ( module trap (
input logic clk, reset, input logic clk, reset,

12
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -99,7 +99,7 @@ module wallypipelinedhart (
logic FStallD; logic FStallD;
logic FWriteIntE, FWriteIntW, FWriteIntM; logic FWriteIntE, FWriteIntW, FWriteIntM;
logic [31:0] FSROutW; logic [31:0] FSROutW;
logic FDivSqrtDoneM; logic FDivBusyE;
logic IllegalFPUInstrD, IllegalFPUInstrE; logic IllegalFPUInstrD, IllegalFPUInstrE;
logic [`XLEN-1:0] FPUResultW; logic [`XLEN-1:0] FPUResultW;
@ -111,14 +111,18 @@ module wallypipelinedhart (
logic [`XLEN-1:0] SATP_REGW; logic [`XLEN-1:0] SATP_REGW;
logic STATUS_MXR, STATUS_SUM; logic STATUS_MXR, STATUS_SUM;
logic [1:0] PrivilegeModeW; logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM; logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
logic [1:0] PageTypeF, PageTypeM; logic [1:0] PageTypeF, PageTypeM;
// PMA checker signals // PMA checker signals
logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM; logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM;
logic Cacheable, Idempotent, AtomicAllowed; logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
logic SquashBusAccess; logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic DSquashBusAccessM, ISquashBusAccessF;
logic [5:0] DHSELRegionsM, IHSELRegionsF;
logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** again, this is a huge bus to be sending all around.
logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu.
assign HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?
// IMem stalls // IMem stalls
logic ICacheStallF; logic ICacheStallF;

1
wally-pipelined/testbench/testbench-busybear.sv
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@ -1,4 +1,5 @@
`include "wally-config.vh" `include "wally-config.vh"
`include "wally-constants.vh"
module testbench(); module testbench();

10
wally-pipelined/testbench/testbench-imperas.sv
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@ -122,6 +122,10 @@ string tests32f[] = '{
}; };
string tests64d[] = '{ string tests64d[] = '{
// "rv64d/I-FDIV-D-01", "2000",
"rv64d/I-FNMADD-D-01", "2000",
"rv64d/I-FNMSUB-D-01", "2000",
"rv64d/I-FMSUB-D-01", "2000",
"rv64d/I-FMAX-D-01", "2000", "rv64d/I-FMAX-D-01", "2000",
"rv64d/I-FMIN-D-01", "2000", "rv64d/I-FMIN-D-01", "2000",
"rv64d/I-FLE-D-01", "2000", "rv64d/I-FLE-D-01", "2000",
@ -139,16 +143,12 @@ string tests32f[] = '{
// "rv64d/I-FCVT-S-D-01", "2000", // "rv64d/I-FCVT-S-D-01", "2000",
// "rv64d/I-FCVT-W-D-01", "2000", // "rv64d/I-FCVT-W-D-01", "2000",
// "rv64d/I-FCVT-WU-D-01", "2000", // "rv64d/I-FCVT-WU-D-01", "2000",
// "rv64d/I-FDIV-D-01", "2000",
"rv64d/I-FSD-01", "2000", "rv64d/I-FSD-01", "2000",
"rv64d/I-FLD-01", "2420", "rv64d/I-FLD-01", "2420",
"rv64d/I-FMADD-D-01", "2000", "rv64d/I-FMADD-D-01", "2000",
// "rv64d/I-FMSUB-D-01", "2000", "rv64d/I-FMUL-D-01", "2000",
// "rv64d/I-FMUL-D-01", "2000",
"rv64d/I-FMV-D-X-01", "2000", "rv64d/I-FMV-D-X-01", "2000",
"rv64d/I-FMV-X-D-01", "2000", "rv64d/I-FMV-X-D-01", "2000",
// "rv64d/I-FNMADD-D-01", "2000",
// "rv64d/I-FNMSUB-D-01", "2000",
"rv64d/I-FSGNJ-D-01", "2000", "rv64d/I-FSGNJ-D-01", "2000",
"rv64d/I-FSGNJN-D-01", "2000", "rv64d/I-FSGNJN-D-01", "2000",
"rv64d/I-FSGNJX-D-01", "2000", "rv64d/I-FSGNJX-D-01", "2000",