Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

sim/coverage-exclusions-rv64gc.do

@@ -97,11 +97,31 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
 
+# Excluding so far un-used instruction sources for the ifu
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
 
 
 #Excluding the bootrom, uncoreran, and clint as sources for the lsu
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
-#set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
+
-#coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
+
+#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
+set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
+set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
+
+# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
+set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
+
+# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
+set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3

src/fpu/fctrl.sv

@@ -242,19 +242,19 @@ module fctrl (
   
   //    X - all except int->fp, store, load, mv int->fp
   assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)|                                                 // load/store
-                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                             // mv int to float - There was an issue here, this condition was not refering to mv int -> fp  // ((FResSelD==2'b11)&FRegWriteD)|
+                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float
                   ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2]));                           // cvt int to float
 
   //    Y - all except cvt, mv, load, class, sqrt
   assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|                                     // load or class 
-                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int
+                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float as above
-                  ((FResSelD==2'b11)&(PostProcSelD==2'b00))|                                    // mv float to int                   // mv both ways
+                  ((FResSelD==2'b11)&(PostProcSelD==2'b00))|                                       // mv float to int 
                   ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
 
-                  // Removed (FResSelD==2'b11)| removed to avoid redundancy 
+
 
   //    Z - fma ops only
-  assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]);                  // fma, add, sub   // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors.
+  assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]);                                    // fma, add, sub   
 
 
   //  Final Res Sel:

tests/coverage/pmpcfg.S

@@ -1,10 +1,52 @@
 // pmpcfg part 1
 // Kevin Wan, kewan@hmc.edu, 4/18/2023
+// Liam Chalk, lchalk@hmc.edu, 4/19/2023
 // locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
 // See the next part in pmpcfg1.S
 
 #include "WALLY-init-lib.h" 
 main: 
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg0, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr2, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg1, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg3, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg1, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg3, t0
+
     li t0, 0x8800000000000000
     csrw pmpcfg2, t0
     li t0, 0x88000000000000
@@ -36,6 +78,4 @@ main:
     li t0, 0x8800
     csrw pmpcfg0, t0
 
-
+    j done
-    j done
-