More cleanup

src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtuotfc4(
-  input  logic [3:0]   udigit,
+  input  logic [3:0]     udigit,
   input  logic [`DIVb:0] U, UM,
   input  logic [`DIVb:0] C,
   output logic [`DIVb:0] UNext, UMNext

src/generic/lzc.sv

@@ -24,7 +24,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module lzc #(parameter WIDTH = 1) (
-  input logic  [WIDTH-1:0]            num,    // number to count the leading zeroes of
+  input  logic [WIDTH-1:0]           num,     // number to count the leading zeroes of
   output logic [$clog2(WIDTH+1)-1:0]  ZeroCnt // the number of leading zeroes
 );
 

src/generic/onehotdecoder.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// oneHotDecoder.sv
+// onehotdecoder.sv
 //
 // Written: ross1728@gmail.com July 09, 2021
 // Modified: 

src/hazard/hazard.sv

@@ -30,13 +30,13 @@
 
 module hazard (
   // Detect hazards
-  input logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
+  input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
-  input logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
+  input  logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
-  input logic  LSUStallM, IFUStallF,
+  input  logic  LSUStallM, IFUStallF,
-  input logic  FCvtIntStallD, FPUStallD,
+  input  logic  FCvtIntStallD, FPUStallD,
-  input logic  DivBusyE, FDivBusyE,
+  input  logic  DivBusyE, FDivBusyE,
-  input logic  EcallFaultM, BreakpointFaultM,
+  input  logic  EcallFaultM, BreakpointFaultM,
-  input logic  wfiM, IntPendingM,
+  input  logic  wfiM, IntPendingM,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,
   output logic FlushD, FlushE, FlushM, FlushW

src/ieu/bmu/byte.sv

@@ -31,7 +31,7 @@
 
 module byteUnit #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,             // Operands
-  input  logic ByteSelect,                // LSB of Immediate
+  input  logic             ByteSelect,    // LSB of Immediate
   output logic [WIDTH-1:0] ByteResult);   // rev8, orcb result
 
   logic [WIDTH-1:0] OrcBResult, Rev8Result;

src/ieu/bmu/cnt.sv

@@ -32,8 +32,8 @@
 
 module cnt #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A, RevA,    // Operands
-  input  logic [1:0] B,                // Last 2 bits of immediate
+  input  logic [1:0]       B,          // Last 2 bits of immediate
-  input  logic W64,                    // Indicates word operation
+  input  logic             W64,        // Indicates word operation
   output logic [WIDTH-1:0] CntResult   // count result
 );
 

src/ieu/bmu/ext.sv

@@ -32,7 +32,7 @@
 
 module ext #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A,            // Operands
-  input  logic [1:0] ExtSelect,          // B[2], B[0] of immediate
+  input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
   output logic [WIDTH-1:0] ExtResult);   // Extend Result
 
   logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult;

src/ieu/bmu/popcnt.sv

@@ -27,7 +27,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module popcnt #(parameter WIDTH = 32) (
-  input logic  [WIDTH-1:0]        num,    // number to count total ones
+  input  logic [WIDTH-1:0]        num,    // number to count total ones
   output logic [$clog2(WIDTH):0]  PopCnt  // the total number of ones
 );
 

src/ieu/ieu.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module ieu (
-  input  logic               clk, reset,
+  input  logic              clk, reset,
   // Decode stage signals
   input  logic [31:0]       InstrD,                          // Instruction
   input  logic              IllegalIEUFPUInstrD,             // Illegal instruction

src/ieu/shifter.sv

@@ -35,9 +35,9 @@ module shifter (
   input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
   output logic [`XLEN-1:0]     Y);                            // Shifted result
 
-  logic [2*`XLEN-2:0]      Z, ZShift;                         // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [2*`XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
-  logic [`LOG_XLEN-1:0]    TruncAmt, Offset;                  // Shift amount adjusted for RV64, right-shift amount
+  logic [`LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
-  logic                    Sign;                              // Sign bit for sign extension
+  logic                        Sign;                          // Sign bit for sign extension
 
   assign Sign = A[`XLEN-1] & SubArith;  // sign bit for sign extension
   if (`XLEN==32) begin // rv32

src/ifu/bpred/bpred.sv

@@ -48,25 +48,25 @@ module bpred (
   input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
   input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
 
-  input logic [31:0]       PostSpillInstrRawF,        // Instruction
+  input  logic [31:0]      PostSpillInstrRawF,        // Instruction
 
   // Branch and jump outcome
-  input logic              InstrValidD, InstrValidE,
+  input  logic             InstrValidD, InstrValidE,
   input  logic             BranchD, BranchE,
   input  logic             JumpD, JumpE,
-  input logic              PCSrcE,                    // Executation stage branch is taken
+  input  logic             PCSrcE,                    // Executation stage branch is taken
-  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  IEUAdrM,                   // The branch/jump target address
+  input  logic [`XLEN-1:0] IEUAdrM,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
-  output logic             BPWrongE,              // Prediction is wrong
+  output logic             BPWrongE,                  // Prediction is wrong
-  output logic             BPWrongM,              // Prediction is wrong
+  output logic             BPWrongM,                  // Prediction is wrong
   output logic             BPDirPredWrongM,           // Prediction direction is wrong
-  output logic             BTAWrongM,           // Prediction target wrong
+  output logic             BTAWrongM,                 // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
-  output logic             IClassWrongM // Class prediction is wrong
+  output logic             IClassWrongM               // Class prediction is wrong
   );
 
   logic [1:0]              BPDirPredF;
@@ -187,7 +187,7 @@ module bpred (
   // Correct branch/jump target.
   mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
   
-  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
+  // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
   // Effectively this is PCM+4 or the non-existant PCLinkM
   if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
   else  assign NextValidPCE = PCE;
@@ -201,11 +201,11 @@ module bpred (
     // 3. target ras    (ras target wrong / class[2])
     // 4. direction     (br dir wrong / class[0])
 
-    // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
+    // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
     // could be wrong or the fall through address selected for branch predict not taken.
     // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
     // both without the above inaccuracies.
-  // **** use BPBTAWrongM from BTB.
+    // **** use BPBTAWrongM from BTB.
     assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 

src/ifu/bpred/btb.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // btb.sv
 //
-// Written: Ross Thomposn ross1728@gmail.com
+// Written: Ross Thompson ross1728@gmail.com
 // Created: February 15, 2021
 // Modified: 24 January 2023 
 //
@@ -34,19 +34,19 @@ module btb #(parameter Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
-  output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC
+  output logic [`XLEN-1:0] BPBTAF,                      // BTB's guess at PC
   output logic [`XLEN-1:0] BPBTAD,
   output logic [`XLEN-1:0] BPBTAE,
-  output logic [3:0]       BTBIClassF, // BTB's guess at instruction class
+  output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
   // update
-  input  logic             IClassWrongM, // BTB's instruction class guess was wrong
+  input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
   input  logic             IClassWrongE,
-  input  logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
+  input  logic [`XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
-  input  logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
+  input  logic [`XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
-  input  logic [3:0]       InstrClassD, // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassD,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassE, // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassE,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassM,                            // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassM,                 // Instruction class to insert into btb
   input  logic [3:0]       InstrClassW
 );
 
@@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) (
 
   // must output a valid PC and valid bit during reset.  Because only PCF, not PCNextF is reset, PCNextF is invalid
   // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
-  // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
+  // While the mux could be included in IFU it is not necessary for the IROM/I$/bus.
   // For now it is optimal to leave it here.
   assign ResetPC = `RESET_VECTOR;
   assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};