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ebu cleanup

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This commit is contained in:
David Harris 2023-01-14 19:29:45 -08:00
parent 17fd2d2a3b
commit 94d01d292e
2 changed files with 72 additions and 86 deletions
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4
pipelined/src/ebu/controllerinputstage.sv
View File

@ -32,8 +32,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module controllerinputstage #(parameter SAVE_ENABLED = 1) module controllerinputstage #(parameter SAVE_ENABLED = 1) (
(input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
input logic Save, Restore, Disable, input logic Save, Restore, Disable,
output logic Request, output logic Request,

22
pipelined/src/ebu/ebu.sv
View File

@ -32,8 +32,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ebu module ebu (
(
input logic clk, reset, input logic clk, reset,
// Signals from IFU // Signals from IFU
input logic [`PA_BITS-1:0] IFUHADDR, input logic [`PA_BITS-1:0] IFUHADDR,
@ -55,7 +54,7 @@ module ebu
// AHB-Lite external signals // AHB-Lite external signals
(* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) input logic HREADY, HRESP,
(* mark_debug = "true" *) output logic HCLK, HRESETn, (* mark_debug = "true" *) output logic HCLK, HRESETn,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR,
(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA, (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB, (* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB,
(* mark_debug = "true" *) output logic HWRITE, (* mark_debug = "true" *) output logic HWRITE,
@ -98,7 +97,6 @@ module ebu
assign HCLK = clk; assign HCLK = clk;
assign HRESETn = ~reset; assign HRESETn = ~reset;
// if two requests come in at once pick one to select and save the others Address phase // if two requests come in at once pick one to select and save the others Address phase
// inputs. Abritration scheme is LSU always goes first. // inputs. Abritration scheme is LSU always goes first.
@ -146,12 +144,7 @@ module ebu
// This part is only used when burst mode is supported. // This part is only used when burst mode is supported.
// Controller needs to count beats. // Controller needs to count beats.
flopenr #(4) flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount);
BeatCountReg(.clk(HCLK),
.reset(~HRESETn | CntReset | FinalBeat),
.en(BeatCntEn),
.d(NextBeatCount),
.q(BeatCount));
assign NextBeatCount = BeatCount + 1'b1; assign NextBeatCount = BeatCount + 1'b1;
assign CntReset = NextState == IDLE; assign CntReset = NextState == IDLE;
@ -159,12 +152,7 @@ module ebu
assign BeatCntEn = (NextState == ARBITRATE & HREADY); assign BeatCntEn = (NextState == ARBITRATE & HREADY);
// Used to store data from data phase of AHB. // Used to store data from data phase of AHB.
flopenr #(1) flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
FinalBeatReg(.clk(HCLK),
.reset(~HRESETn | CntReset),
.en(BeatCntEn),
.d(FinalBeat),
.q(FinalBeatD));
// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
always_comb begin always_comb begin
@ -176,7 +164,6 @@ module ebu
default: Threshold = 4'b0000; // INCR without end. default: Threshold = 4'b0000; // INCR without end.
endcase endcase
end end
// end of burst mode.
// basic arb always selects LSU when both // basic arb always selects LSU when both
// replace this block for more sophisticated arbitration as needed. // replace this block for more sophisticated arbitration as needed.
@ -191,5 +178,4 @@ module ebu
flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD); flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD);
endmodule endmodule