Merge pull request #688 from davidharrishmc/dev

Cleanup

Makefile

@@ -6,7 +6,7 @@ all:
 	make install
 	make riscof	
 	make testfloat
-	make verify
+#	make verify
 	make coverage
 	make benchmarks
 

benchmarks/coremark/coremark_sweep.py

@@ -1,3 +1,4 @@
+#!/usr/bin/python 
 ##################################################
 ## coremark_sweep.py
 

bin/docker.sh

@@ -0,0 +1,25 @@
+# script to install docker
+# based on https://docs.docker.com/engine/install/ubuntu/
+# from Kunlin Han, entered by David Harris
+
+# Add Docker's official GPG key:
+sudo apt-get update
+sudo apt-get install ca-certificates curl
+sudo install -m 0755 -d /etc/apt/keyrings
+sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
+sudo chmod a+r /etc/apt/keyrings/docker.asc
+
+# Add the repository to Apt sources:
+echo \
+  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
+  $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
+  sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
+sudo apt-get update
+sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
+
+# verify
+sudo docker run hello-world
+
+# install podman
+sudo apt-get -y install podman
+ 

bin/wally-tool-chain-install.sh

@@ -46,7 +46,7 @@ sudo mkdir -p $RISCV
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 sudo apt update -y
 sudo apt upgrade -y
-sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc 
+sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt
 # Other python libraries used through the book.
 sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown 
 
@@ -60,12 +60,10 @@ fi
 # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
 # To install GCC from source can take hours to compile. 
 # This configuration enables multilib to target many flavors of RISC-V.   
-# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
+# This book is tested with GCC 13.2.0
-# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
+# Versions newer than 2023-12-20 fail to compile the RISC-V arch test with an error:
-# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
+# cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b'
-# However GCC12.x is needed for bit manipulation instructions.  There is an open issue to fix this:
+# PR *** submitted to fix riscv-arch-test to be compatible with latest GCC by modifying test_macros.h for TEST_JALR_OP
-# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
-
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
@@ -99,7 +97,7 @@ make install
 
 # Spike (https://github.com/riscv-software-src/riscv-isa-sim)
 # Spike also takes a while to install and compile, but this can be done concurrently 
-#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions.
+# with the GCC installation. 
 cd $RISCV
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 mkdir -p riscv-isa-sim/build
@@ -107,10 +105,7 @@ cd riscv-isa-sim/build
 ../configure --prefix=$RISCV 
 make -j ${NUM_THREADS}
 make install 
-cd ../arch_test_target/spike/device
+
-# dh 2/5/24: these should be obsolete
-#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
-#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 
 # Wally needs Verilator 5.021 or later.
 # Verilator needs to be built from scratch to get the latest version

sim/wave.do

@@ -256,7 +256,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-c
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE
 add wave -noupdate -expand -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay
@@ -265,7 +264,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
 add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay
@@ -294,7 +293,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
@@ -316,7 +314,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelData}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
@@ -426,7 +423,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM

src/lsu/amoalu.sv

@@ -37,38 +37,53 @@ module amoalu import cvw::*;  #(parameter cvw_t P) (
 );
 
   logic [P.XLEN-1:0] a, b, y;
+  logic               lt, cmp, sngd, sngd32, eq32, lt32, w64;
 
-  // *** see how synthesis generates this and optimize more structurally if necessary to share hardware
+  // Rename inputs
-  // a single carry chain should be shared for + and the four min/max
+  assign a = ReadDataM;
-  // and the same mux can be used to select b for swap.
+  assign b = IHWriteDataM;
+
+  // Share hardware among the four amomin/amomax comparators
+  assign sngd = ~LSUFunct7M[5]; // Funct7[5] = 0 for signed amomin/max
+  assign w64 = (LSUFunct3M[1:0] == 2'b10); // operate on bottom 32 bits
+  assign sngd32 = sngd & (P.XLEN == 32 | w64); // flip sign in lower 32 bits on 32-bit comparisons only
+
+  comparator #(32) cmp32(a[31:0], b[31:0], sngd32, {eq32, lt32});
+  if (P.XLEN == 32) begin
+    assign lt = lt32;
+  end else begin
+    logic equpper, ltupper, lt64;
+
+    comparator #(32) cmpupper(a[63:32], b[63:32], sngd, {equpper, ltupper});
+    assign lt64 = ltupper | equpper & lt32;
+    assign lt = w64 ? lt32 : lt64;
+  end
+
+  assign cmp = lt ^ LSUFunct7M[4]; // flip sense of comparison for maximums
+
+  // AMO ALU
   always_comb 
     case (LSUFunct7M[6:2])
-      5'b00001: y = b;                                      // amoswap
+      5'b00001: y = b;           // amoswap
-      5'b00000: y = a + b;                                  // amoadd
+      5'b00000: y = a + b;       // amoadd
-      5'b00100: y = a ^ b;                                  // amoxor
+      5'b00100: y = a ^ b;       // amoxor
-      5'b01100: y = a & b;                                  // amoand
+      5'b01100: y = a & b;       // amoand
-      5'b01000: y = a | b;                                  // amoor
+      5'b01000: y = a | b;       // amoor
-      5'b10000: y = ($signed(a) < $signed(b)) ? a : b;      // amomin
+      5'b10000: y = cmp ? a : b; // amomin
-      5'b10100: y = ($signed(a) >= $signed(b)) ? a : b;     // amomax
+      5'b10100: y = cmp ? a : b; // amomax
-      5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b;  // amominu
+      5'b11000: y = cmp ? a : b; // amominu
-      5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
+      5'b11100: y = cmp ? a : b; // amomaxu
-      default:  y = 'x;                                     // undefined; *** could change to b for efficiency
+      default:  y = 'x;          // undefined; *** could change to b for efficiency
     endcase
 
-  // sign extend if necessary
+  // sign extend output if necessary for w64
   if (P.XLEN == 32) begin:sext
-    assign a = ReadDataM;
-    assign b = IHWriteDataM;
     assign AMOResultM = y;
   end else begin:sext // P.XLEN = 64
     always_comb 
-      if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
+      if (w64) begin // sign-extend word-length operations
-        a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
-        b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
         AMOResultM = {{32{y[31]}}, y[31:0]};
       end else begin
-        a = ReadDataM;
-        b = IHWriteDataM;
         AMOResultM = y;
       end
   end

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output

@@ -1,8 +0,0 @@
-fffffffe
-00000000
-0000002a
-fffffffd
-00000001
-0000002a
-00000000
-00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output

@@ -1,24 +0,0 @@
-fffffffe
-ffffffff
-00000000
-00000000
-0000002a
-00000000
-fffffffd
-ffffffff
-00000001
-00000000
-0000002a
-00000000
-fffffffb
-fffffff7
-00000000
-00000000
-0000002c
-00000000
-ffffffef
-ffffffdf
-00000001
-00000000
-0000002c
-00000000