diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 2e0d92fb8..bacd6f17a 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -31,7 +31,7 @@
`define XLEN 64
//`define MISA (32'h00000105)
-`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
+`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0 | 1 << 3)
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv
index 51f90aefc..994cb1e6f 100755
--- a/wally-pipelined/src/fpu/fctrl.sv
+++ b/wally-pipelined/src/fpu/fctrl.sv
@@ -200,7 +200,7 @@ module fctrl (
// fmv.d.w = ?101
// {?, is mv, is store, is double or fcvt.d.w}
3'b111 : OpCtrlD = {1'b0, OpD[6:5], Funct3D[0] | (OpD[6]&Funct7D[0])};
- default : begin OpCtrlD = 4'bxxxx; IllegalFPUInstrD = isFP; end
+ default : begin OpCtrlD = 4'bxxxx; IllegalFPUInstrD = 1'b1; end
endcase
end
diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index 7fb77e261..76a46498b 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -48,9 +48,9 @@ module fpu (
localparam PipeEnable = 1'b1;
always_comb begin
- PipeEnableDE = StallE;
- PipeEnableEM = StallM;
- PipeEnableMW = StallW;
+ PipeEnableDE = ~StallE;
+ PipeEnableEM = ~StallM;
+ PipeEnableMW = ~StallW;
PipeClearDE = FlushE;
PipeClearEM = FlushM;
PipeClearMW = FlushW;
diff --git a/wally-pipelined/src/privileged/privdec.sv b/wally-pipelined/src/privileged/privdec.sv
index 5e3581ff8..1330a62bc 100644
--- a/wally-pipelined/src/privileged/privdec.sv
+++ b/wally-pipelined/src/privileged/privdec.sv
@@ -47,7 +47,7 @@ module privdec (
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001);
assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
- assign IllegalInstrFaultM = IllegalIEUInstrFaultM | IllegalFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions
+ assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM; // *** generalize this for other instructions
// *** initially, wfi and sfencevma are nop
// *** zfenci extension?
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 509f769aa..2e3af3e2c 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -52,6 +52,7 @@ module privileged (
input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
input logic [4:0] SetFflagsM,
+ output logic IllegalFPUInstrE,
output logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] SATP_REGW,
output logic STATUS_MXR, STATUS_SUM,
@@ -78,7 +79,7 @@ module privileged (
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
- logic IllegalFPUInstrE, IllegalFPUInstrM;
+ logic IllegalFPUInstrM;
logic LoadPageFaultM, StorePageFaultM;
logic InstrPageFaultF, InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
logic InstrAccessFaultF, InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index f93c6b285..2c7ccc053 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -96,7 +96,7 @@ module wallypipelinedhart (
logic SquashSCW;
logic [31:0] FSROutW;
logic DivSqrtDoneE;
- logic IllegalFPUInstrD;
+ logic IllegalFPUInstrD, IllegalFPUInstrE;
logic [`XLEN-1:0] FPUResultW;
// memory management unit signals
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 488fd6002..310207ab0 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -52,11 +52,110 @@ module testbench();
"rv64mmu/WALLY-VIRTUALMEMORY", "2000"
};
+
+string tests32f[] = '{
+ "rv32f/I-FADD-S-01", "2000",
+ "rv32f/I-FCLASS-S-01", "2000",
+ "rv32f/I-FCVT-S-L-01", "2000",
+ "rv32f/I-FCVT-S-LU-01", "2000",
+ "rv32f/I-FCVT-S-W-01", "2000",
+ "rv32f/I-FCVT-S-WU-01", "2000",
+ "rv32f/I-FCVT-L-S-01", "2000",
+ "rv32f/I-FCVT-LU-S-01", "2000",
+ "rv32f/I-FCVT-W-S-01", "2000",
+ "rv32f/I-FCVT-WU-S-01", "2000",
+ "rv32f/I-FDIV-S-01", "2000",
+ "rv32f/I-FEQ-S-01", "2000",
+ "rv32f/I-FLE-S-01", "2000",
+ "rv32f/I-FLT-S-01", "2000",
+ "rv32f/I-FMADD-S-01", "2000",
+ "rv32f/I-FMAX-S-01", "2000",
+ "rv32f/I-FMIN-S-01", "2000",
+ "rv32f/I-FMSUB-S-01", "2000",
+ "rv32f/I-FMUL-S-01", "2000",
+ "rv32f/I-FMV-W-X-01", "2000",
+ "rv32f/I-FMV-X-W-01", "2000",
+ "rv32f/I-FNMADD-S-01", "2000",
+ "rv32f/I-FNMSUB-S-01", "2000",
+ "rv32f/I-FSGNJ-S-01", "2000",
+ "rv32f/I-FSGNJN-S-01", "2000",
+ "rv32f/I-FSGNJX-S-01", "2000",
+ "rv32f/I-FSQRT-S-01", "2000",
+ "rv32f/I-FSW-01", "2000",
+ "rv32f/I-FLW-01", "2000",
+ "rv32f/I-FSUB-S-01", "2000"
+ };
+
string tests64f[] = '{
"rv64f/I-FADD-S-01", "2000",
- "rv64f/I-FCLASS-S-01", "2000"
+ "rv64f/I-FCLASS-S-01", "2000",
+ "rv64f/I-FCVT-S-L-01", "2000",
+ "rv64f/I-FCVT-S-LU-01", "2000",
+ "rv64f/I-FCVT-S-W-01", "2000",
+ "rv64f/I-FCVT-S-WU-01", "2000",
+ "rv64f/I-FCVT-L-S-01", "2000",
+ "rv64f/I-FCVT-LU-S-01", "2000",
+ "rv64f/I-FCVT-W-S-01", "2000",
+ "rv64f/I-FCVT-WU-S-01", "2000",
+ "rv64f/I-FDIV-S-01", "2000",
+ "rv64f/I-FEQ-S-01", "2000",
+ "rv64f/I-FLE-S-01", "2000",
+ "rv64f/I-FLT-S-01", "2000",
+ "rv64f/I-FMADD-S-01", "2000",
+ "rv64f/I-FMAX-S-01", "2000",
+ "rv64f/I-FMIN-S-01", "2000",
+ "rv64f/I-FMSUB-S-01", "2000",
+ "rv64f/I-FMUL-S-01", "2000",
+ "rv64f/I-FMV-W-X-01", "2000",
+ "rv64f/I-FNMADD-S-01", "2000",
+ "rv64f/I-FNMSUB-S-01", "2000",
+ "rv64f/I-FSGNJ-S-01", "2000",
+ "rv64f/I-FSGNJN-S-01", "2000",
+ "rv64f/I-FSGNJX-S-01", "2000",
+ "rv64f/I-FSQRT-S-01", "2000",
+ "rv64f/I-FSW-01", "2000",
+ "rv64f/I-FLW-01", "2000",
+ "rv64f/I-FSUB-S-01", "2000"
};
+
+ string tests64d[] = '{
+ "rv64d/I-FMV-X-D-01", "2000",
+ "rv64d/I-FADD-D-01", "2000",
+ "rv64d/I-FCLASS-D-01", "2000",
+ "rv64d/I-FCVT-D-L-01", "2000",
+ "rv64d/I-FCVT-D-LU-01", "2000",
+ "rv64d/I-FCVT-D-S-01", "2000",
+ "rv64d/I-FCVT-D-W-01", "2000",
+ "rv64d/I-FCVT-D-WU-01", "2000",
+ "rv64d/I-FCVT-L-D-01", "2000",
+ "rv64d/I-FCVT-LU-D-01", "2000",
+ "rv64d/I-FCVT-S-D-01", "2000",
+ "rv64d/I-FCVT-W-D-01", "2000",
+ "rv64d/I-FCVT-WU-D-01", "2000",
+ "rv64d/I-FDIV-D-01", "2000",
+ "rv64d/I-FEQ-D-01", "2000",
+ "rv64d/I-FLD-D-01", "2000",
+ "rv64d/I-FLE-D-01", "2000",
+ "rv64d/I-FLT-D-01", "2000",
+ "rv64d/I-FMADD-D-01", "2000",
+ "rv64d/I-FMAX-D-01", "2000",
+ "rv64d/I-FMIN-D-01", "2000",
+ "rv64d/I-FMSUB-D-01", "2000",
+ "rv64d/I-FMUL-D-01", "2000",
+ "rv64d/I-FMV-D-X-01", "2000",
+ "rv64d/I-FNMADD-D-01", "2000",
+ "rv64d/I-FNMSUB-D-01", "2000",
+ "rv64d/I-FSD-01", "2000",
+ "rv64d/I-FSGNJ-D-01", "2000",
+ "rv64d/I-FSGNJN-D-01", "2000",
+ "rv64d/I-FSGNJX-D-01", "2000",
+ "rv64d/I-FSQRTD-01", "2000",
+ "rv64d/I-FSUB-D-01", "2000"
+ };
+
+
+
string tests64a[] = '{
"rv64a/WALLY-AMO", "2110",
"rv64a/WALLY-LRSC", "2110"
@@ -426,10 +525,10 @@ module testbench();
if (`C_SUPPORTED) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m};
- // if (`F_SUPPORTED) tests = {tests64f, tests};
- // if (`D_SUPPORTED) tests = {tests64d, tests};
if (`A_SUPPORTED) tests = {tests, tests64a};
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
+ // if (`F_SUPPORTED) tests = {tests64f, tests};
+ // if (`D_SUPPORTED) tests = {tests64d, tests};
end
//tests = {tests64a, tests};
end else begin // RV32
@@ -555,6 +654,7 @@ module testbench();
errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
+ // $stop;//***debug
end
end
i = i + 1;
@@ -633,11 +733,13 @@ module instrNameDecTB(
logic [2:0] funct3;
logic [6:0] funct7;
logic [11:0] imm;
+ logic [4:0] rs2;
assign op = instr[6:0];
assign funct3 = instr[14:12];
assign funct7 = instr[31:25];
assign imm = instr[31:20];
+ assign rs2 = instr[24:20];
// it would be nice to add the operands to the name
// create another variable called decoded
@@ -761,6 +863,67 @@ module instrNameDecTB(
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
else name = "ILLEGAL";
10'b0001111_???: name = "FENCE";
+ 10'b1000011_???: name = "FMADD";
+ 10'b1000111_???: name = "FMSUB";
+ 10'b1001011_???: name = "FNMSUB";
+ 10'b1001111_???: name = "FNMADD";
+ 10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
+ else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
+ else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE
+ else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
+ else if (funct7[6:2] == 5'b00101) name = "FMIN";
+ else if (funct7[6:2] == 5'b10100) name = "FLE";
+ else name = "ILLEGAL";
+ 10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
+ else if (funct7[6:2] == 5'b00101) name = "FMAX";
+ else if (funct7[6:2] == 5'b10100) name = "FLT";
+ else if (funct7[6:2] == 5'b11100) name = "FCLASS";
+ else name = "ILLEGAL";
+ 10'b0101111_010: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
+ else if (funct7[6:2] == 5'b10100) name = "FEQ";
+ else name = "ILLEGAL";
+ 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else name = "ILLEGAL";
+ 10'b0000111_010: name = "FLW";
+ 10'b0100111_010: name = "FSW";
+ 10'b0000111_010: name = "FLD";
+ 10'b0100111_010: name = "FSD";
default: name = "ILLEGAL";
endcase
endmodule