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Fixed spelling of operation in FPU

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This commit is contained in:
David Harris 2024-02-15 17:22:32 -08:00
parent c664c9717d
commit 944e33dcd6
13 changed files with 45 additions and 45 deletions
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10
src/fpu/fctrl.sv
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@ -46,11 +46,11 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
// input mux selections
output logic XEnD, YEnD, ZEnD, // enable inputs
output logic XEnE, YEnE, ZEnE, // enable inputs
// opperation mux selections
output logic FCvtIntE, FCvtIntW, // convert to integer opperation
// operation mux selections
output logic FCvtIntE, FCvtIntW, // convert to integer operation
output logic [2:0] FrmM, // FP rounding mode
output logic [P.FMTBITS-1:0] FmtE, FmtM, // FP format
output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component
output logic [2:0] OpCtrlE, OpCtrlM, // Select which operation to do in each component
output logic FpLoadStoreM, // FP load or store instruction
output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit
output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage
@ -72,7 +72,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
logic FRegWriteD; // FP register write enable
logic FDivStartD; // start division/sqrt
logic FWriteIntD; // integer register write enable
logic [2:0] OpCtrlD; // Select which opperation to do in each component
logic [2:0] OpCtrlD; // Select which operation to do in each component
logic [1:0] PostProcSelD; // select result in the post processing unit
logic [1:0] FResSelD; // Select one of the results that finish in the memory stage
logic [2:0] FrmD, FrmE; // FP rounding mode
@ -80,7 +80,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
logic [1:0] Fmt, Fmt2; // format - before possible reduction
logic SupportedFmt; // is the format supported
logic SupportedFmt2; // is the source format supported for fp -> fp
logic FCvtIntD, FCvtIntM; // convert to integer opperation
logic FCvtIntD, FCvtIntM; // convert to integer operation
logic ZfaD; // Zfa variants of instructions
// FPU Instruction Decoder

8
src/fpu/fcvt.sv
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@ -31,7 +31,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
input logic [P.NE-1:0] Xe, // input's exponent
input logic [P.NF:0] Xm, // input's fraction
input logic [P.XLEN-1:0] Int, // integer input - from IEU
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
input logic [2:0] OpCtrl, // choose which operation (look below for values)
input logic ToInt, // is fp->int (since it's writting to the integer register)
input logic XZero, // is the input zero
input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
@ -58,9 +58,9 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size
logic [P.NE-2:0] NewBias; // the bias of the final result
logic [P.NE-1:0] OldExp; // the old exponent
logic Signed; // is the opperation with a signed integer?
logic Signed; // is the operation with a signed integer?
logic Int64; // is the integer 64 bits?
logic IntToFp; // is the opperation an int->fp conversion?
logic IntToFp; // is the operation an int->fp conversion?
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
@ -69,7 +69,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
assign Int64 = OpCtrl[1];
assign IntToFp = OpCtrl[2];
// choose the output format depending on the opperation
// choose the output format depending on the operation
// - fp -> fp: OpCtrl contains the precision of the output
// - int -> fp: Fmt contains the precision of the output
if (P.FPSIZES == 2)

4
src/fpu/fma/fma.sv
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@ -36,7 +36,7 @@ module fma import cvw::*; #(parameter cvw_t P) (
output logic ASticky, // sticky bit that is calculated during alignment
output logic [3*P.NF+3:0] Sm, // the positive sum's significand
output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
output logic As, // the aligned addend's sign (modified Z sign for other opperations)
output logic As, // the aligned addend's sign (modified Z sign for other operations)
output logic Ps, // the product's sign
output logic Ss, // the sum's sign
output logic [P.NE+1:0] Se, // the sum's exponent
@ -74,7 +74,7 @@ module fma import cvw::*; #(parameter cvw_t P) (
// multiplication of the mantissa's
fmamult #(P) mult(.Xm, .Ym, .Pm);
// calculate the signs and take the opperation into account
// calculate the signs and take the operation into account
fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA);
///////////////////////////////////////////////////////////////////////////////

2
src/fpu/fma/fmaadd.sv
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@ -30,7 +30,7 @@
module fmaadd import cvw::*; #(parameter cvw_t P) (
input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
input logic [P.NE-1:0] Ze, // exponent of Z
input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other operations)
input logic [P.NE+1:0] Pe, // product's exponet
input logic [2*P.NF+1:0] Pm, // the product's mantissa
input logic InvA, // invert the aligned addend

6
src/fpu/fma/fmasign.sv
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@ -28,10 +28,10 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fmasign(
input logic [2:0] OpCtrl, // opperation contol
input logic [2:0] OpCtrl, // operation contol
input logic Xs, Ys, Zs, // sign of the inputs
output logic Ps, // the product's sign - takes opperation into account
output logic As, // aligned addend sign used in fma - takes opperation into account
output logic Ps, // the product's sign - takes operation into account
output logic As, // aligned addend sign used in fma - takes operation into account
output logic InvA // Effective subtraction: invert addend
);

2
src/fpu/fpu.sv
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@ -75,7 +75,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
logic FDivStartE, IDivStartE; // Start division or squareroot
logic FWriteIntM; // Write to integer register
logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component
logic [2:0] OpCtrlE, OpCtrlM; // Select which operation to do in each component
logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage
logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit
logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input

6
src/fpu/postproc/flags.sv
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@ -42,7 +42,7 @@ module flags import cvw::*; #(parameter cvw_t P) (
input logic Round, Guard, Sticky, // bits used to determine rounding
input logic UfPlus1, // do you add one for rounding for the unbounded exponent result
// convert
input logic CvtOp, // conversion opperation?
input logic CvtOp, // conversion operation?
input logic ToInt, // convert to integer
input logic IntToFp, // convert integer to floating point
input logic Int64, // convert to 64 bit integer
@ -50,10 +50,10 @@ module flags import cvw::*; #(parameter cvw_t P) (
input logic [P.NE:0] CvtCe, // the calculated expoent - Cvt
input logic [1:0] CvtNegResMsbs, // the negative integer result's most significant bits
// divsqrt
input logic DivOp, // conversion opperation?
input logic DivOp, // conversion operation?
input logic Sqrt, // Sqrt?
// fma
input logic FmaOp, // Fma opperation?
input logic FmaOp, // Fma operation?
input logic FmaAs, FmaPs, // the product and modified Z signs
// flags
output logic DivByZero, // divide by zero flag

18
src/fpu/postproc/postprocess.sv
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@ -33,7 +33,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
input logic [P.NF:0] Xm, Ym, Zm, // input mantissas
input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
input logic [P.FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
input logic [2:0] OpCtrl, // choose which operation (look below for values)
input logic XZero, YZero, // inputs are zero
input logic XInf, YInf, ZInf, // inputs are infinity
input logic XNaN, YNaN, ZNaN, // inputs are NaN
@ -104,14 +104,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
logic CvtResUf; // did the convert result underflow
logic IntInvalid; // invalid integer flag
// readability signals
logic Mult; // multiply opperation
logic Sqrt; // is the divsqrt opperation sqrt
logic Mult; // multiply operation
logic Sqrt; // is the divsqrt operation sqrt
logic Int64; // is the integer 64 bits?
logic Signed; // is the opperation with a signed integer?
logic IntToFp; // is the opperation an int->fp conversion?
logic CvtOp; // convertion opperation
logic FmaOp; // fma opperation
logic DivOp; // divider opperation
logic Signed; // is the operation with a signed integer?
logic IntToFp; // is the operation an int->fp conversion?
logic CvtOp; // convertion operation
logic FmaOp; // fma operation
logic DivOp; // divider operation
logic InfIn; // are any of the inputs infinity
logic NaNIn; // are any of the inputs NaN
@ -129,7 +129,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
assign InfIn = XInf|YInf|ZInf;
assign NaNIn = XNaN|YNaN|ZNaN;
// choose the output format depending on the opperation
// choose the output format depending on the operation
// - fp -> fp: OpCtrl contains the precision of the output
// - otherwise: Fmt contains the precision of the output
if (P.FPSIZES == 2)

6
src/fpu/postproc/resultsign.sv
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@ -30,7 +30,7 @@
module resultsign(
input logic [2:0] Frm, // rounding mode
input logic FmaOp, // is the operation an Fma
input logic Mult, // is the fma opperation multipy
input logic Mult, // is the fma operation multipy
input logic ZInf, // is Z infinity
input logic InfIn, // are any of the inputs infinity
input logic FmaSZero, // is the fma sum zero
@ -49,7 +49,7 @@ module resultsign(
// determine the sign for a result of 0
// The IEEE754-2019 standard specifies:
// - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity
// - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result
// - when the exact result of an FMA operation is non-zero, but is zero due to rounding, use the sign of the exact result
// - if x = +0 or -0 then x+x=x and x-(-x)=x
// - the sign of a product is the exclisive or or the opperand's signs
// Zero sign will only be selected if:
@ -58,7 +58,7 @@ module resultsign(
// - P is killed and Z is zero - Psgn
// - Z is killed and P is zero - impossible
// Zero sign calculation:
// - if a multiply opperation is done, then use the products sign(Ps)
// - if a multiply operation is done, then use the products sign(Ps)
// - if the zero sum is not exactly zero i.e. Round|Sticky use the sign of the exact result (which is the product's sign)
// - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign
assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;

8
src/fpu/postproc/round.sv
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@ -34,15 +34,15 @@ module round import cvw::*; #(parameter cvw_t P) (
input logic Ms, // normalized sign
input logic [P.CORRSHIFTSZ-1:0] Mf, // normalized fraction
// fma
input logic FmaOp, // is an fma opperation being done?
input logic FmaOp, // is an fma operation being done?
input logic [P.NE+1:0] FmaMe, // exponent of the normalized sum for fma
input logic FmaASticky, // addend's sticky bit
// divsqrt
input logic DivOp, // is a division opperation being done
input logic DivOp, // is a division operation being done
input logic DivSticky, // divsqrt sticky bit
input logic [P.NE+1:0] Ue, // the divsqrt calculated expoent
// cvt
input logic CvtOp, // is a convert opperation being done
input logic CvtOp, // is a convert operation being done
input logic ToInt, // is the cvt op a cvt to integer
input logic CvtResSubnormUf, // is the cvt result subnormal or underflow
input logic CvtResUf, // does the cvt result underflow
@ -181,7 +181,7 @@ module round import cvw::*; #(parameter cvw_t P) (
end
// only add the Addend sticky if doing an FMA opperation
// only add the Addend sticky if doing an FMA operation
// - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[P.NE+1]&FmaOp | DivSticky&DivOp;

6
src/fpu/postproc/roundsign.sv
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@ -33,9 +33,9 @@ module roundsign(
input logic CvtCs, // convert result sign
input logic FmaSs, // fma sum sign
input logic Sqrt, // sqrt oppertion? (when using divsqrt unit)
input logic FmaOp, // is fma opperation
input logic DivOp, // is divsqrt opperation
input logic CvtOp, // is cvt opperation
input logic FmaOp, // is fma operation
input logic DivOp, // is divsqrt operation
input logic CvtOp, // is cvt operation
output logic Ms // normalized result sign
);

4
src/fpu/postproc/shiftcorrection.sv
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@ -30,12 +30,12 @@
module shiftcorrection import cvw::*; #(parameter cvw_t P) (
input logic [P.NORMSHIFTSZ-1:0] Shifted, // the shifted sum before LZA correction
// divsqrt
input logic DivOp, // is it a divsqrt opperation
input logic DivOp, // is it a divsqrt operation
input logic DivResSubnorm, // is the divsqrt result subnormal
input logic [P.NE+1:0] DivUe, // the divsqrt result's exponent
input logic DivSubnormShiftPos, // is the subnorm divider shift amount positive (ie not underflowed)
//fma
input logic FmaOp, // is it an fma opperation
input logic FmaOp, // is it an fma operation
input logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results
input logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
input logic FmaSZero,

10
src/fpu/postproc/specialcase.sv
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@ -44,14 +44,14 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
input logic [P.NE+1:0] FullRe, // Result full exponent
input logic [P.NF-1:0] Rf, // Result fraction
// fma
input logic FmaOp, // is it a fma opperation
input logic FmaOp, // is it a fma operation
// divsqrt
input logic DivOp, // is it a divsqrt opperation
input logic DivOp, // is it a divsqrt operation
input logic DivByZero, // divide by zero flag
// cvt
input logic CvtOp, // is it a conversion opperation
input logic CvtOp, // is it a conversion operation
input logic IntZero, // is the integer input zero
input logic IntToFp, // is cvt int -> fp opperation
input logic IntToFp, // is cvt int -> fp operation
input logic Int64, // is the integer 64 bits
input logic Signed, // is the integer signed
input logic Zfa, // Zfa conversion operation: fcvtmod.w.d
@ -356,7 +356,7 @@ module specialcase import cvw::*; #(parameter cvw_t P) (
// select the integer output
// - if the input is invalid (out of bounds NaN or Inf) then output overflow res
// - if the input underflows
// - if rounding and signed opperation and negative input, output -1
// - if rounding and signed operation and negative input, output -1
// - otherwise output a rounded 0
// - otherwise output the normal res (trmined and sign extended if nessisary)
always_comb