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Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.

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Rose Thompson 2024-07-23 17:44:37 -05:00
parent 6c212ebf0e
commit 9404a339ee
1 changed files with 6 additions and 0 deletions
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6
src/rvvi/rvvisynth.sv
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@ -88,6 +88,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
{FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} : {FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} :
'0; '0;
/* verilator lint_off UNOPTFLAT */
// For some reason verilator complains about CSRWenFilterMatrix being in a circular loop when it is not.
// the CSRs are complex // the CSRs are complex
// 1. we need to get the CSR values // 1. we need to get the CSR values
// 2. we check if the CSR value changes by registering the value then XORing with the old value. // 2. we check if the CSR value changes by registering the value then XORing with the old value.
@ -121,9 +124,12 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
always_comb begin always_comb begin
CSRCountShort = '0; CSRCountShort = '0;
for(index2 = 0; index2 < MAX_CSRS; index2++) begin for(index2 = 0; index2 < MAX_CSRS; index2++) begin
/* verilator lint_off WIDTHEXPAND */
CSRCountShort += EnabledCSRs[index2]; CSRCountShort += EnabledCSRs[index2];
/* verilator lint_on WIDTHEXPAND */
end end
end end
/* verilator lint_on UNOPTFLAT */
assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort};
assign rvvi = {CSRs, Registers, Required}; assign rvvi = {CSRs, Registers, Required};