From 0cc0cdeae231c5e30089c5f6487676940edb7efa Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 18:31:17 -0600 Subject: [PATCH 01/47] initial seed of AES engine --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 103 ++++++++ src/ieu/aes_common/aes_inv_sbox.sv | 295 ++++++++++++++++++++++ src/ieu/aes_common/aes_inv_sbox_128.sv | 42 ++++ src/ieu/aes_common/aes_inv_sbox_word.sv | 42 ++++ src/ieu/aes_common/aes_inv_shiftrow.sv | 97 ++++++++ src/ieu/aes_common/aes_mixcolumns.sv | 130 ++++++++++ src/ieu/aes_common/aes_sbox.sv | 296 +++++++++++++++++++++++ src/ieu/aes_common/aes_sbox_word.sv | 46 ++++ src/ieu/aes_common/aes_shiftrow.sv | 98 ++++++++ src/ieu/aes_common/galois_func.sv | 167 +++++++++++++ src/ieu/aes_common/rotateleft.sv | 34 +++ 11 files changed, 1350 insertions(+) create mode 100644 src/ieu/aes_common/aes_inv_mixcolumns.sv create mode 100644 src/ieu/aes_common/aes_inv_sbox.sv create mode 100644 src/ieu/aes_common/aes_inv_sbox_128.sv create mode 100644 src/ieu/aes_common/aes_inv_sbox_word.sv create mode 100644 src/ieu/aes_common/aes_inv_shiftrow.sv create mode 100644 src/ieu/aes_common/aes_mixcolumns.sv create mode 100644 src/ieu/aes_common/aes_sbox.sv create mode 100644 src/ieu/aes_common/aes_sbox_word.sv create mode 100644 src/ieu/aes_common/aes_shiftrow.sv create mode 100644 src/ieu/aes_common/galois_func.sv create mode 100644 src/ieu/aes_common/rotateleft.sv diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv new file mode 100644 index 000000000..ed82f053e --- /dev/null +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -0,0 +1,103 @@ +/////////////////////////////////////////// +// aes_inv_mixcolumns.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V AES Mix Columns +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word); + + // Instantiate Internal Logic + logic [7:0] b0, b1, b2, b3; + logic [7:0] mb0, mb1, mb2, mb3; + + logic [7:0] gm9_mb0, gm11_mb0, gm13_mb0, gm14_mb0; + logic [7:0] gm9_mb1, gm11_mb1, gm13_mb1, gm14_mb1; + logic [7:0] gm9_mb2, gm11_mb2, gm13_mb2, gm14_mb2; + logic [7:0] gm9_mb3, gm11_mb3, gm13_mb3, gm14_mb3; + + // Break up word into 1 byte slices + assign b0 = word[31:24]; + assign b1 = word[23:16]; + assign b2 = word[15:8]; + assign b3 = word[7:0]; + + // mb0 Galois components + gm9 gm9_0(.gm9_in(b1), .gm9_out(gm9_mb0)); + gm11 gm11_0(.gm11_in(b3), .gm11_out(gm11_mb0)); + gm13 gm13_0(.gm13_in(b2), .gm13_out(gm13_mb0)); + gm14 gm14_0(.gm14_in(b0), .gm14_out(gm14_mb0)); + + // mb1 Galois components + gm9 gm9_1(.gm9_in(b2), .gm9_out(gm9_mb1)); + gm11 gm11_1(.gm11_in(b0), .gm11_out(gm11_mb1)); + gm13 gm13_1(.gm13_in(b3), .gm13_out(gm13_mb1)); + gm14 gm14_1(.gm14_in(b1), .gm14_out(gm14_mb1)); + + // mb2 Galois components + gm9 gm9_2(.gm9_in(b3), .gm9_out(gm9_mb2)); + gm11 gm11_2(.gm11_in(b1), .gm11_out(gm11_mb2)); + gm13 gm13_2(.gm13_in(b0), .gm13_out(gm13_mb2)); + gm14 gm14_2(.gm14_in(b2), .gm14_out(gm14_mb2)); + + // mb3 Galois components + gm9 gm9_3(.gm9_in(b0), .gm9_out(gm9_mb3)); + gm11 gm11_3(.gm11_in(b2), .gm11_out(gm11_mb3)); + gm13 gm13_3(.gm13_in(b1), .gm13_out(gm13_mb3)); + gm14 gm14_3(.gm14_in(b3), .gm14_out(gm14_mb3)); + + // XOR Galois components and assign output + assign mb0 = gm9_mb0 ^ gm11_mb0 ^ gm13_mb0 ^ gm14_mb0; + assign mb1 = gm9_mb1 ^ gm11_mb1 ^ gm13_mb1 ^ gm14_mb1; + assign mb2 = gm9_mb2 ^ gm11_mb2 ^ gm13_mb2 ^ gm14_mb2; + assign mb3 = gm9_mb3 ^ gm11_mb3 ^ gm13_mb3 ^ gm14_mb3; + assign mixed_word = {mb0, mb1, mb2, mb3}; + +endmodule // inv_mixword + +module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col); + + // Declare Internal logic + logic [31:0] w0, w1, w2, w3; + logic [31:0] ws0, ws1, ws2, ws3; + + // Break up input data into word components + assign w0 = data[127:96]; + assign w1 = data[95:64]; + assign w2 = data[63:32]; + assign w3 = data[31:0]; + + // Declare mixword components + inv_mixword mw_0(.word(w0), .mixed_word(ws0)); + inv_mixword mw_1(.word(w1), .mixed_word(ws1)); + inv_mixword mw_2(.word(w2), .mixed_word(ws2)); + inv_mixword mw_3(.word(w3), .mixed_word(ws3)); + + // Assign output to mixed word + assign mixed_col = {ws0, ws1, ws2, ws3}; + +endmodule // inv_mixcols + + diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv new file mode 100644 index 000000000..ca6c1c054 --- /dev/null +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -0,0 +1,295 @@ +/////////////////////////////////////////// +// aes_inv_sbox.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V Rinjdael Inverted S-BOX +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_inv_sbox(input logic [7:0] in, + output logic [7:0] out); + + always_comb + begin + case(in) + 8'h00 : out = 8'h52; + 8'h01 : out = 8'h09; + 8'h02 : out = 8'h6A; + 8'h03 : out = 8'hD5; + 8'h04 : out = 8'h30; + 8'h05 : out = 8'h36; + 8'h06 : out = 8'hA5; + 8'h07 : out = 8'h38; + 8'h08 : out = 8'hBF; + 8'h09 : out = 8'h40; + 8'h0A : out = 8'hA3; + 8'h0B : out = 8'h9E; + 8'h0C : out = 8'h81; + 8'h0D : out = 8'hF3; + 8'h0E : out = 8'hD7; + 8'h0F : out = 8'hFB; + 8'h10 : out = 8'h7C; + 8'h11 : out = 8'hE3; + 8'h12 : out = 8'h39; + 8'h13 : out = 8'h82; + 8'h14 : out = 8'h9B; + 8'h15 : out = 8'h2F; + 8'h16 : out = 8'hFF; + 8'h17 : out = 8'h87; + 8'h18 : out = 8'h34; + 8'h19 : out = 8'h8E; + 8'h1A : out = 8'h43; + 8'h1B : out = 8'h44; + 8'h1C : out = 8'hC4; + 8'h1D : out = 8'hDE; + 8'h1E : out = 8'hE9; + 8'h1F : out = 8'hCB; + 8'h20 : out = 8'h54; + 8'h21 : out = 8'h7B; + 8'h22 : out = 8'h94; + 8'h23 : out = 8'h32; + 8'h24 : out = 8'hA6; + 8'h25 : out = 8'hC2; + 8'h26 : out = 8'h23; + 8'h27 : out = 8'h3D; + 8'h28 : out = 8'hEE; + 8'h29 : out = 8'h4C; + 8'h2A : out = 8'h95; + 8'h2B : out = 8'h0B; + 8'h2C : out = 8'h42; + 8'h2D : out = 8'hFA; + 8'h2E : out = 8'hC3; + 8'h2F : out = 8'h4E; + 8'h30 : out = 8'h08; + 8'h31 : out = 8'h2E; + 8'h32 : out = 8'hA1; + 8'h33 : out = 8'h66; + 8'h34 : out = 8'h28; + 8'h35 : out = 8'hD9; + 8'h36 : out = 8'h24; + 8'h37 : out = 8'hB2; + 8'h38 : out = 8'h76; + 8'h39 : out = 8'h5B; + 8'h3A : out = 8'hA2; + 8'h3B : out = 8'h49; + 8'h3C : out = 8'h6D; + 8'h3D : out = 8'h8B; + 8'h3E : out = 8'hD1; + 8'h3F : out = 8'h25; + 8'h40 : out = 8'h72; + 8'h41 : out = 8'hF8; + 8'h42 : out = 8'hF6; + 8'h43 : out = 8'h64; + 8'h44 : out = 8'h86; + 8'h45 : out = 8'h68; + 8'h46 : out = 8'h98; + 8'h47 : out = 8'h16; + 8'h48 : out = 8'hD4; + 8'h49 : out = 8'hA4; + 8'h4A : out = 8'h5C; + 8'h4B : out = 8'hCC; + 8'h4C : out = 8'h5D; + 8'h4D : out = 8'h65; + 8'h4E : out = 8'hB6; + 8'h4F : out = 8'h92; + 8'h50 : out = 8'h6C; + 8'h51 : out = 8'h70; + 8'h52 : out = 8'h48; + 8'h53 : out = 8'h50; + 8'h54 : out = 8'hFD; + 8'h55 : out = 8'hED; + 8'h56 : out = 8'hB9; + 8'h57 : out = 8'hDA; + 8'h58 : out = 8'h5E; + 8'h59 : out = 8'h15; + 8'h5A : out = 8'h46; + 8'h5B : out = 8'h57; + 8'h5C : out = 8'hA7; + 8'h5D : out = 8'h8D; + 8'h5E : out = 8'h9D; + 8'h5F : out = 8'h84; + 8'h60 : out = 8'h90; + 8'h61 : out = 8'hD8; + 8'h62 : out = 8'hAB; + 8'h63 : out = 8'h00; + 8'h64 : out = 8'h8C; + 8'h65 : out = 8'hBC; + 8'h66 : out = 8'hD3; + 8'h67 : out = 8'h0A; + 8'h68 : out = 8'hF7; + 8'h69 : out = 8'hE4; + 8'h6A : out = 8'h58; + 8'h6B : out = 8'h05; + 8'h6C : out = 8'hB8; + 8'h6D : out = 8'hB3; + 8'h6E : out = 8'h45; + 8'h6F : out = 8'h06; + 8'h70 : out = 8'hD0; + 8'h71 : out = 8'h2C; + 8'h72 : out = 8'h1E; + 8'h73 : out = 8'h8F; + 8'h74 : out = 8'hCA; + 8'h75 : out = 8'h3F; + 8'h76 : out = 8'h0F; + 8'h77 : out = 8'h02; + 8'h78 : out = 8'hC1; + 8'h79 : out = 8'hAF; + 8'h7A : out = 8'hBD; + 8'h7B : out = 8'h03; + 8'h7C : out = 8'h01; + 8'h7D : out = 8'h13; + 8'h7E : out = 8'h8A; + 8'h7F : out = 8'h6B; + 8'h80 : out = 8'h3A; + 8'h81 : out = 8'h91; + 8'h82 : out = 8'h11; + 8'h83 : out = 8'h41; + 8'h84 : out = 8'h4F; + 8'h85 : out = 8'h67; + 8'h86 : out = 8'hDC; + 8'h87 : out = 8'hEA; + 8'h88 : out = 8'h97; + 8'h89 : out = 8'hF2; + 8'h8A : out = 8'hCF; + 8'h8B : out = 8'hCE; + 8'h8C : out = 8'hF0; + 8'h8D : out = 8'hB4; + 8'h8E : out = 8'hE6; + 8'h8F : out = 8'h73; + 8'h90 : out = 8'h96; + 8'h91 : out = 8'hAC; + 8'h92 : out = 8'h74; + 8'h93 : out = 8'h22; + 8'h94 : out = 8'hE7; + 8'h95 : out = 8'hAD; + 8'h96 : out = 8'h35; + 8'h97 : out = 8'h85; + 8'h98 : out = 8'hE2; + 8'h99 : out = 8'hF9; + 8'h9A : out = 8'h37; + 8'h9B : out = 8'hE8; + 8'h9C : out = 8'h1C; + 8'h9D : out = 8'h75; + 8'h9E : out = 8'hDF; + 8'h9F : out = 8'h6E; + 8'hA0 : out = 8'h47; + 8'hA1 : out = 8'hF1; + 8'hA2 : out = 8'h1A; + 8'hA3 : out = 8'h71; + 8'hA4 : out = 8'h1D; + 8'hA5 : out = 8'h29; + 8'hA6 : out = 8'hC5; + 8'hA7 : out = 8'h89; + 8'hA8 : out = 8'h6F; + 8'hA9 : out = 8'hB7; + 8'hAA : out = 8'h62; + 8'hAB : out = 8'h0E; + 8'hAC : out = 8'hAA; + 8'hAD : out = 8'h18; + 8'hAE : out = 8'hBE; + 8'hAF : out = 8'h1B; + 8'hB0 : out = 8'hFC; + 8'hB1 : out = 8'h56; + 8'hB2 : out = 8'h3E; + 8'hB3 : out = 8'h4B; + 8'hB4 : out = 8'hC6; + 8'hB5 : out = 8'hD2; + 8'hB6 : out = 8'h79; + 8'hB7 : out = 8'h20; + 8'hB8 : out = 8'h9A; + 8'hB9 : out = 8'hDB; + 8'hBA : out = 8'hC0; + 8'hBB : out = 8'hFE; + 8'hBC : out = 8'h78; + 8'hBD : out = 8'hCD; + 8'hBE : out = 8'h5A; + 8'hBF : out = 8'hF4; + 8'hC0 : out = 8'h1F; + 8'hC1 : out = 8'hDD; + 8'hC2 : out = 8'hA8; + 8'hC3 : out = 8'h33; + 8'hC4 : out = 8'h88; + 8'hC5 : out = 8'h07; + 8'hC6 : out = 8'hC7; + 8'hC7 : out = 8'h31; + 8'hC8 : out = 8'hB1; + 8'hC9 : out = 8'h12; + 8'hCA : out = 8'h10; + 8'hCB : out = 8'h59; + 8'hCC : out = 8'h27; + 8'hCD : out = 8'h80; + 8'hCE : out = 8'hEC; + 8'hCF : out = 8'h5F; + 8'hD0 : out = 8'h60; + 8'hD1 : out = 8'h51; + 8'hD2 : out = 8'h7F; + 8'hD3 : out = 8'hA9; + 8'hD4 : out = 8'h19; + 8'hD5 : out = 8'hB5; + 8'hD6 : out = 8'h4A; + 8'hD7 : out = 8'h0D; + 8'hD8 : out = 8'h2D; + 8'hD9 : out = 8'hE5; + 8'hDA : out = 8'h7A; + 8'hDB : out = 8'h9F; + 8'hDC : out = 8'h93; + 8'hDD : out = 8'hC9; + 8'hDE : out = 8'h9C; + 8'hDF : out = 8'hEF; + 8'hE0 : out = 8'hA0; + 8'hE1 : out = 8'hE0; + 8'hE2 : out = 8'h3B; + 8'hE3 : out = 8'h4D; + 8'hE4 : out = 8'hAE; + 8'hE5 : out = 8'h2A; + 8'hE6 : out = 8'hF5; + 8'hE7 : out = 8'hB0; + 8'hE8 : out = 8'hC8; + 8'hE9 : out = 8'hEB; + 8'hEA : out = 8'hBB; + 8'hEB : out = 8'h3C; + 8'hEC : out = 8'h83; + 8'hED : out = 8'h53; + 8'hEE : out = 8'h99; + 8'hEF : out = 8'h61; + 8'hF0 : out = 8'h17; + 8'hF1 : out = 8'h2B; + 8'hF2 : out = 8'h04; + 8'hF3 : out = 8'h7E; + 8'hF4 : out = 8'hBA; + 8'hF5 : out = 8'h77; + 8'hF6 : out = 8'hD6; + 8'hF7 : out = 8'h26; + 8'hF8 : out = 8'hE1; + 8'hF9 : out = 8'h69; + 8'hFA : out = 8'h14; + 8'hFB : out = 8'h63; + 8'hFC : out = 8'h55; + 8'hFD : out = 8'h21; + 8'hFE : out = 8'h0C; + 8'hFF : out = 8'h7D; + endcase + end + +endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox_128.sv b/src/ieu/aes_common/aes_inv_sbox_128.sv new file mode 100644 index 000000000..a5c6faa3f --- /dev/null +++ b/src/ieu/aes_common/aes_inv_sbox_128.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// aes_inv_sbox_128.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V 128-bit Inverse Substitution box +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_inv_sbox_128(input logic [127:0] in, + output logic [127:0] out); + + //Declare the SBOX for (least significant) word 0 of the input + aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0])); + //Declare the SBOX for word 1 of the input + aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32])); + //Declare the SBOX for word 2 of the input + aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64])); + //Declare the SBOX for word 3 of the input + aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96])); + +endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv new file mode 100644 index 000000000..7e6c9efd7 --- /dev/null +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// aes_inv_sbox.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V Rinjdael Inverted S-BOX +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_inv_sbox_word(input logic [31:0] in, + output logic [31:0] out); + + //Declare the SBOX for (least significant) byte 0 of the input + aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + //Declare the SBOX for byte 1 of the input + aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + //Declare the SBOX for byte 2 of the input + aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + //Declare the SBOX for byte 3 of the input + aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + +endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv new file mode 100644 index 000000000..7ff605d15 --- /dev/null +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -0,0 +1,97 @@ +/////////////////////////////////////////// +// aes_inv_shiftrow.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V AES Shiftrow +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_inv_shiftrow(input logic [127:0] dataIn, + output logic [127:0] dataOut); + + //Seperate the first (Least Significant) word into bytes + logic [7:0] w0_b0 = dataIn[7:0]; + logic [7:0] w0_b1 = dataIn[15:8]; + logic [7:0] w0_b2 = dataIn[23:16]; + logic [7:0] w0_b3 = dataIn[31:24]; + //Seperate the second word into bytes + logic [7:0] w1_b0 = dataIn[39:32]; + logic [7:0] w1_b1 = dataIn[47:40]; + logic [7:0] w1_b2 = dataIn[55:48]; + logic [7:0] w1_b3 = dataIn[63:56]; + //Seperate the third word into bytes + logic [7:0] w2_b0 = dataIn[71:64]; + logic [7:0] w2_b1 = dataIn[79:72]; + logic [7:0] w2_b2 = dataIn[87:80]; + logic [7:0] w2_b3 = dataIn[95:88]; + //Seperate the fourth (Most significant) word into bytes + logic [7:0] w3_b0 = dataIn[103:96]; + logic [7:0] w3_b1 = dataIn[111:104]; + logic [7:0] w3_b2 = dataIn[119:112]; + logic [7:0] w3_b3 = dataIn[127:120]; + + //The output words are composed of sets of the input bytes. + logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + + assign dataOut = {out_w0, out_w1, out_w2, out_w3}; + +endmodule + + +/* + Purpose : This next module provides an alternative way to shift the values. + in which it takes the shift number (essentially row number) as + an input and shifts cyclically to the left by that number of bits. + the complexity here is removed from the module and is more complex in + input selection. + */ + +module aes_shiftword(input logic[1:0] shiftAmt, + input logic [31:0] dataIn, + output logic [31:0] dataOut); + + + logic [7:0] b0 = dataIn[7:0]; + logic [7:0] b1 = dataIn[15:8]; + logic [7:0] b2 = dataIn[23:16]; + logic [7:0] b3 = dataIn[31:24]; + + always_comb + begin + case(shiftAmt) + //00 : Barrel Shift no bytes + 2'b00 : dataOut = {b3, b2, b1, b0}; + //01 : Barrel Shift one byte + 2'b01 : dataOut = {b0, b3, b2, b1}; + //10 : Barrel Shift two bytes + 2'b10 : dataOut = {b1, b0, b3, b2}; + //11 : Barrel Shift three bytes + default : dataOut = {b2, b1, b0, b3}; + endcase + end // always_comb + +endmodule diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv new file mode 100644 index 000000000..0fa5d4b77 --- /dev/null +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -0,0 +1,130 @@ +/////////////////////////////////////////// +// aes_mixcolumns.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V "Mix Columns" +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +/* + * Purpose : The "mix columns" operation is essentially composed of a + * nice little Galois field multiplication (of 1, 2 or 3) in the field + * x^8 + x^4 + x^3 + x + 1. + * The actual matrix you multiply by is + * [2 3 1 1][a_0,j] + * [1 2 3 1][a_1,j] + * [1 1 2 3][a_2,j] + * [3 1 1 2][a_3,j] + * + * Reference: secworks repo + */ + +module aes_mixcolumns(data, mixedcols); + + // Declare Inputs/Outputs + input logic [127:0] data; + output logic [127:0] mixedcols; + + // Declare internal Logic + logic [31:0] w0, w1, w2, w3; + logic [31:0] ws0, ws1, ws2, ws3; + + // Break up data into individual words + assign w0 = data[127:96]; + assign w1 = data[95:64]; + assign w2 = data[63:32]; + assign w3 = data[31:0]; + + // Instantiate The mix words components for the words + mixword mw0(.word(w0), .mixed_word(ws0)); + mixword mw1(.word(w1), .mixed_word(ws1)); + mixword mw2(.word(w2), .mixed_word(ws2)); + mixword mw3(.word(w3), .mixed_word(ws3)); + + // Assign Output + assign mixedcols = {ws0, ws1, ws2, ws3}; + +endmodule // mixcolumns + +//This applies the Galois field operations to an individual 32 bit word. +module mixword (word, mixed_word); + + // Declare Inputs/Outputs + input logic [31:0] word; + output logic [31:0] mixed_word; + + // Declare Internal Signals + logic [7:0] b0, b1, b2, b3; + logic [7:0] mb0, mb1, mb2, mb3; + + logic [7:0] gm2_0_out; + logic [7:0] gm3_0_out; + + logic [7:0] gm2_1_out; + logic [7:0] gm3_1_out; + + logic [7:0] gm2_2_out; + logic [7:0] gm3_2_out; + + logic [7:0] gm2_3_out; + logic [7:0] gm3_3_out; + + // Break word into bytes + assign b0 = word[31:24]; + assign b1 = word[23:16]; + assign b2 = word[15:8]; + assign b3 = word[7:0]; + + // mb0 Galois components + gm2 gm2_0(.gm2_in(b0), + .gm2_out(gm2_0_out)); + gm3 gm3_0(.gm3_in(b3), + .gm3_out(gm3_0_out)); + + // mb1 Galois components + gm2 gm2_1(.gm2_in(b1), + .gm2_out(gm2_1_out)); + gm3 gm3_1(.gm3_in(b0), + .gm3_out(gm3_1_out)); + + // mb2 Galois components + gm2 gm2_2(.gm2_in(b2), + .gm2_out(gm2_2_out)); + gm3 gm3_2(.gm3_in(b1), + .gm3_out(gm3_2_out)); + + // mb3 Galois components + gm2 gm2_3(.gm2_in(b3), + .gm2_out(gm2_3_out)); + gm3 gm3_3(.gm3_in(b2), + .gm3_out(gm3_3_out)); + + // Combine Componenets into mixed word + assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; + assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3; + assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3; + assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1; + assign mixed_word = {mb0, mb1, mb2, mb3}; + +endmodule diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv new file mode 100644 index 000000000..8f6901cdc --- /dev/null +++ b/src/ieu/aes_common/aes_sbox.sv @@ -0,0 +1,296 @@ +/////////////////////////////////////////// +// aes_mixcolumns.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V Rinjdael forward S-BOX in the form of a LUT +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_sbox(input logic [7:0] in, + output logic [7:0] out); + + // case statement to lookup the value in the rijndael table + always_comb + begin + case(in) + 8'h00 : out = 8'h63; + 8'h01 : out = 8'h7C; + 8'h02 : out = 8'h77; + 8'h03 : out = 8'h7B; + 8'h04 : out = 8'hF2; + 8'h05 : out = 8'h6B; + 8'h06 : out = 8'h6F; + 8'h07 : out = 8'hC5; + 8'h08 : out = 8'h30; + 8'h09 : out = 8'h01; + 8'h0A : out = 8'h67; + 8'h0B : out = 8'h2B; + 8'h0C : out = 8'hFE; + 8'h0D : out = 8'hD7; + 8'h0E : out = 8'hAB; + 8'h0F : out = 8'h76; + 8'h10 : out = 8'hCA; + 8'h11 : out = 8'h82; + 8'h12 : out = 8'hC9; + 8'h13 : out = 8'h7D; + 8'h14 : out = 8'hFA; + 8'h15 : out = 8'h59; + 8'h16 : out = 8'h47; + 8'h17 : out = 8'hF0; + 8'h18 : out = 8'hAD; + 8'h19 : out = 8'hD4; + 8'h1A : out = 8'hA2; + 8'h1B : out = 8'hAF; + 8'h1C : out = 8'h9C; + 8'h1D : out = 8'hA4; + 8'h1E : out = 8'h72; + 8'h1F : out = 8'hC0; + 8'h20 : out = 8'hB7; + 8'h21 : out = 8'hFD; + 8'h22 : out = 8'h93; + 8'h23 : out = 8'h26; + 8'h24 : out = 8'h36; + 8'h25 : out = 8'h3F; + 8'h26 : out = 8'hF7; + 8'h27 : out = 8'hCC; + 8'h28 : out = 8'h34; + 8'h29 : out = 8'hA5; + 8'h2A : out = 8'hE5; + 8'h2B : out = 8'hF1; + 8'h2C : out = 8'h71; + 8'h2D : out = 8'hD8; + 8'h2E : out = 8'h31; + 8'h2F : out = 8'h15; + 8'h30 : out = 8'h04; + 8'h31 : out = 8'hC7; + 8'h32 : out = 8'h23; + 8'h33 : out = 8'hC3; + 8'h34 : out = 8'h18; + 8'h35 : out = 8'h96; + 8'h36 : out = 8'h05; + 8'h37 : out = 8'h9A; + 8'h38 : out = 8'h07; + 8'h39 : out = 8'h12; + 8'h3A : out = 8'h80; + 8'h3B : out = 8'hE2; + 8'h3C : out = 8'hEB; + 8'h3D : out = 8'h27; + 8'h3E : out = 8'hB2; + 8'h3F : out = 8'h75; + 8'h40 : out = 8'h09; + 8'h41 : out = 8'h83; + 8'h42 : out = 8'h2C; + 8'h43 : out = 8'h1A; + 8'h44 : out = 8'h1B; + 8'h45 : out = 8'h6E; + 8'h46 : out = 8'h5A; + 8'h47 : out = 8'hA0; + 8'h48 : out = 8'h52; + 8'h49 : out = 8'h3B; + 8'h4A : out = 8'hD6; + 8'h4B : out = 8'hB3; + 8'h4C : out = 8'h29; + 8'h4D : out = 8'hE3; + 8'h4E : out = 8'h2F; + 8'h4F : out = 8'h84; + 8'h50 : out = 8'h53; + 8'h51 : out = 8'hD1; + 8'h52 : out = 8'h00; + 8'h53 : out = 8'hED; + 8'h54 : out = 8'h20; + 8'h55 : out = 8'hFC; + 8'h56 : out = 8'hB1; + 8'h57 : out = 8'h5B; + 8'h58 : out = 8'h6A; + 8'h59 : out = 8'hCB; + 8'h5A : out = 8'hBE; + 8'h5B : out = 8'h39; + 8'h5C : out = 8'h4A; + 8'h5D : out = 8'h4C; + 8'h5E : out = 8'h58; + 8'h5F : out = 8'hCF; + 8'h60 : out = 8'hD0; + 8'h61 : out = 8'hEF; + 8'h62 : out = 8'hAA; + 8'h63 : out = 8'hFB; + 8'h64 : out = 8'h43; + 8'h65 : out = 8'h4D; + 8'h66 : out = 8'h33; + 8'h67 : out = 8'h85; + 8'h68 : out = 8'h45; + 8'h69 : out = 8'hF9; + 8'h6A : out = 8'h02; + 8'h6B : out = 8'h7F; + 8'h6C : out = 8'h50; + 8'h6D : out = 8'h3C; + 8'h6E : out = 8'h9F; + 8'h6F : out = 8'hA8; + 8'h70 : out = 8'h51; + 8'h71 : out = 8'hA3; + 8'h72 : out = 8'h40; + 8'h73 : out = 8'h8F; + 8'h74 : out = 8'h92; + 8'h75 : out = 8'h9D; + 8'h76 : out = 8'h38; + 8'h77 : out = 8'hF5; + 8'h78 : out = 8'hBC; + 8'h79 : out = 8'hB6; + 8'h7A : out = 8'hDA; + 8'h7B : out = 8'h21; + 8'h7C : out = 8'h10; + 8'h7D : out = 8'hFF; + 8'h7E : out = 8'hF3; + 8'h7F : out = 8'hD2; + 8'h80 : out = 8'hCD; + 8'h81 : out = 8'h0C; + 8'h82 : out = 8'h13; + 8'h83 : out = 8'hEC; + 8'h84 : out = 8'h5F; + 8'h85 : out = 8'h97; + 8'h86 : out = 8'h44; + 8'h87 : out = 8'h17; + 8'h88 : out = 8'hC4; + 8'h89 : out = 8'hA7; + 8'h8A : out = 8'h7E; + 8'h8B : out = 8'h3D; + 8'h8C : out = 8'h64; + 8'h8D : out = 8'h5D; + 8'h8E : out = 8'h19; + 8'h8F : out = 8'h73; + 8'h90 : out = 8'h60; + 8'h91 : out = 8'h81; + 8'h92 : out = 8'h4F; + 8'h93 : out = 8'hDC; + 8'h94 : out = 8'h22; + 8'h95 : out = 8'h2A; + 8'h96 : out = 8'h90; + 8'h97 : out = 8'h88; + 8'h98 : out = 8'h46; + 8'h99 : out = 8'hEE; + 8'h9A : out = 8'hB8; + 8'h9B : out = 8'h14; + 8'h9C : out = 8'hDE; + 8'h9D : out = 8'h5E; + 8'h9E : out = 8'h0B; + 8'h9F : out = 8'hDB; + 8'hA0 : out = 8'hE0; + 8'hA1 : out = 8'h32; + 8'hA2 : out = 8'h3A; + 8'hA3 : out = 8'h0A; + 8'hA4 : out = 8'h49; + 8'hA5 : out = 8'h06; + 8'hA6 : out = 8'h24; + 8'hA7 : out = 8'h5C; + 8'hA8 : out = 8'hC2; + 8'hA9 : out = 8'hD3; + 8'hAA : out = 8'hAC; + 8'hAB : out = 8'h62; + 8'hAC : out = 8'h91; + 8'hAD : out = 8'h95; + 8'hAE : out = 8'hE4; + 8'hAF : out = 8'h79; + 8'hB0 : out = 8'hE7; + 8'hB1 : out = 8'hC8; + 8'hB2 : out = 8'h37; + 8'hB3 : out = 8'h6D; + 8'hB4 : out = 8'h8D; + 8'hB5 : out = 8'hD5; + 8'hB6 : out = 8'h4E; + 8'hB7 : out = 8'hA9; + 8'hB8 : out = 8'h6C; + 8'hB9 : out = 8'h56; + 8'hBA : out = 8'hF4; + 8'hBB : out = 8'hEA; + 8'hBC : out = 8'h65; + 8'hBD : out = 8'h7A; + 8'hBE : out = 8'hAE; + 8'hBF : out = 8'h08; + 8'hC0 : out = 8'hBA; + 8'hC1 : out = 8'h78; + 8'hC2 : out = 8'h25; + 8'hC3 : out = 8'h2E; + 8'hC4 : out = 8'h1C; + 8'hC5 : out = 8'hA6; + 8'hC6 : out = 8'hB4; + 8'hC7 : out = 8'hC6; + 8'hC8 : out = 8'hE8; + 8'hC9 : out = 8'hDD; + 8'hCA : out = 8'h74; + 8'hCB : out = 8'h1F; + 8'hCC : out = 8'h4B; + 8'hCD : out = 8'hBD; + 8'hCE : out = 8'h8B; + 8'hCF : out = 8'h8A; + 8'hD0 : out = 8'h70; + 8'hD1 : out = 8'h3E; + 8'hD2 : out = 8'hB5; + 8'hD3 : out = 8'h66; + 8'hD4 : out = 8'h48; + 8'hD5 : out = 8'h03; + 8'hD6 : out = 8'hF6; + 8'hD7 : out = 8'h0E; + 8'hD8 : out = 8'h61; + 8'hD9 : out = 8'h35; + 8'hDA : out = 8'h57; + 8'hDB : out = 8'hB9; + 8'hDC : out = 8'h86; + 8'hDD : out = 8'hC1; + 8'hDE : out = 8'h1D; + 8'hDF : out = 8'h9E; + 8'hE0 : out = 8'hE1; + 8'hE1 : out = 8'hF8; + 8'hE2 : out = 8'h98; + 8'hE3 : out = 8'h11; + 8'hE4 : out = 8'h69; + 8'hE5 : out = 8'hD9; + 8'hE6 : out = 8'h8E; + 8'hE7 : out = 8'h94; + 8'hE8 : out = 8'h9B; + 8'hE9 : out = 8'h1E; + 8'hEA : out = 8'h87; + 8'hEB : out = 8'hE9; + 8'hEC : out = 8'hCE; + 8'hED : out = 8'h55; + 8'hEE : out = 8'h28; + 8'hEF : out = 8'hDF; + 8'hF0 : out = 8'h8C; + 8'hF1 : out = 8'hA1; + 8'hF2 : out = 8'h89; + 8'hF3 : out = 8'h0D; + 8'hF4 : out = 8'hBF; + 8'hF5 : out = 8'hE6; + 8'hF6 : out = 8'h42; + 8'hF7 : out = 8'h68; + 8'hF8 : out = 8'h41; + 8'hF9 : out = 8'h99; + 8'hFA : out = 8'h2D; + 8'hFB : out = 8'h0F; + 8'hFC : out = 8'hB0; + 8'hFD : out = 8'h54; + 8'hFE : out = 8'hBB; + 8'hFF : out = 8'h16; + endcase + end + +endmodule diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv new file mode 100644 index 000000000..7f04eb7c0 --- /dev/null +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -0,0 +1,46 @@ +/////////////////////////////////////////// +// aes_sbox_word.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously. +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_sbox_word(input logic [31:0] in, + output logic [31:0] out); + + // Declare the SBOX for (least significant) byte 0 of the input + aes_sbox sbox_b0(.in(in[7:0]), + .out(out[7:0])); + // Declare the SBOX for byte 1 of the input + aes_sbox sbox_b1(.in(in[15:8]), + .out(out[15:8])); + // Declare the SBOX for byte 2 of the input + aes_sbox sbox_b2(.in(in[23:16]), + .out(out[23:16])); + // Declare the SBOX for byte 3 of the input + aes_sbox sbox_b3(.in(in[31:24]), + .out(out[31:24])); + +endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv new file mode 100644 index 000000000..58a3582b3 --- /dev/null +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -0,0 +1,98 @@ +/////////////////////////////////////////// +// aes_shiftrow.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V aes_shiftrow for taking in first data line +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_shiftrow(input logic [127:0] dataIn, + output logic [127:0] dataOut); + + // (This form of writing it may seem like more effort but I feel + // like it is more self-explanatory this way without losing efficiency) + + //Seperate the first (Least Significant) word into bytes + logic [7:0] w0_b0 = dataIn[7:0]; + logic [7:0] w0_b1 = dataIn[79:72]; + logic [7:0] w0_b2 = dataIn[23:16]; + logic [7:0] w0_b3 = dataIn[95:88]; + //Seperate the second word into bytes + logic [7:0] w1_b0 = dataIn[39:32]; + logic [7:0] w1_b1 = dataIn[111:104]; + logic [7:0] w1_b2 = dataIn[55:48]; + logic [7:0] w1_b3 = dataIn[127:120]; + //Seperate the third word into bytes + logic [7:0] w2_b0 = dataIn[71:64]; + logic [7:0] w2_b1 = dataIn[15:8]; + logic [7:0] w2_b2 = dataIn[87:80]; + logic [7:0] w2_b3 = dataIn[31:24]; + //Seperate the fourth (Most significant) word into bytes + logic [7:0] w3_b0 = dataIn[103:96]; + logic [7:0] w3_b1 = dataIn[47:40]; + logic [7:0] w3_b2 = dataIn[119:112]; + logic [7:0] w3_b3 = dataIn[63:56]; + + //The output words are composed of sets of the input bytes. + logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + + assign dataOut = {out_w0, out_w1, out_w2, out_w3}; + +endmodule + +/* + * Purpose : This next module provides an alternative way to shift the values. + in which it takes the shift number (essentially row number) as + an input and shifts cyclically to the left by that number of bits. + the complexity here is removed from the module and is more complex in + input selection (eww more thinking bad return to monkeh) + */ + +module aes_shiftwordbrutherr(input logic[1:0] shiftAmt, + input logic [31:0] dataIn, + output logic [31:0] dataOut); + + logic [7:0] b0 = dataIn[7:0]; + logic [7:0] b1 = dataIn[15:8]; + logic [7:0] b2 = dataIn[23:16]; + logic [7:0] b3 = dataIn[31:24]; + + always_comb + begin + case(shiftAmt) + //00 : Barrel Shift no bytes + 2'b00 : dataOut = {b3, b2, b1, b0}; + //01 : Barrel Shift one byte + 2'b01 : dataOut = {b2, b1, b0, b3}; + //10 : Barrel Shift two bytes + 2'b10 : dataOut = {b1, b0, b2, b3}; + //11 : Barrel Shift three bytes + default : dataOut = {b0, b1, b2, b3}; + endcase + end + +endmodule diff --git a/src/ieu/aes_common/galois_func.sv b/src/ieu/aes_common/galois_func.sv new file mode 100644 index 000000000..520764d60 --- /dev/null +++ b/src/ieu/aes_common/galois_func.sv @@ -0,0 +1,167 @@ +/////////////////////////////////////////// +// galois_func.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V Galois field operations for mix columns operation +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm2 (gm2_in, gm2_out); + + input logic [7:0] gm2_in; + output logic [7:0] gm2_out; + + // Set output to Galois Mult 2 + assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); + +endmodule // gm2 + +module gm3 (gm3_in, gm3_out); + + input logic [7:0] gm3_in; + output logic [7:0] gm3_out; + + // Internal Logic + logic [7:0] gm2_0_out; + + // Sub-Modules for gm2 multiplication + gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out)); + + // Assign Output + assign gm3_out = gm2_0_out ^ gm3_in; + +endmodule + +module gm4 (gm4_in, gm4_out); + + input logic [7:0] gm4_in; + output logic [7:0] gm4_out; + + // Internal Logic + logic [7:0] gm2_0_out; + logic [7:0] gm2_1_out; + + // Sub-Modules for multiple gm2 multiplications + gm2 gm2_0 (.gm2_in(gm4_in), + .gm2_out(gm2_0_out)); + gm2 gm2_1 (.gm2_in(gm2_0_out), + .gm2_out(gm2_1_out)); + + // Assign output to second gm2 output + assign gm4_out = gm2_1_out; + +endmodule + +module gm8 (gm8_in, gm8_out); + + input logic [7:0] gm8_in; + output logic [7:0] gm8_out; + + // Internal Logic + logic [7:0] gm2_0_out; + logic [7:0] gm4_0_out; + + // Sub-Modules for sub-galois operations + gm4 gm4_0 (.gm4_in(gm8_in), + .gm4_out(gm4_0_out)); + gm2 gm2_0 (.gm2_in(gm4_0_out), + .gm2_out(gm2_0_out)); + + // Assign output to gm2 output + assign gm8_out = gm2_0_out; + +endmodule // gm8 + +module gm9 (gm9_in, gm9_out); + + input logic [7:0] gm9_in; + output logic [7:0] gm9_out; + + // Internal Logic + logic [7:0] gm8_0_out; + + // Sub-Modules for sub-galois operations + gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); + + // Set output to gm8(in) ^ in + assign gm9_out = gm8_0_out ^ gm9_in; + +endmodule + +module gm11 (gm11_in, gm11_out); + + input logic [7:0] gm11_in; + output logic [7:0] gm11_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm2_0_out; + + // Sub-Modules for sub-galois operations + gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); + gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); + + // Set output to gm8(in) ^ gm2(in) ^ in + assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; + +endmodule // gm11 + +module gm13 (gm13_in, gm13_out); + + input logic [7:0] gm13_in; + output logic [7:0] gm13_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm4_0_out; + + // Sub-Modules for sub-galois operations + gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); + gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); + + // Set output to gm8(in) ^ gm4(in) ^ in + assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; + +endmodule // gm13 + +module gm14 (gm14_in, gm14_out); + + input logic [7:0] gm14_in; + output logic [7:0] gm14_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm4_0_out; + logic [7:0] gm2_0_out; + + // Sub-Modules for sub-galois operations + gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); + gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); + gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); + + //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) + assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; + +endmodule // gm14 + diff --git a/src/ieu/aes_common/rotateleft.sv b/src/ieu/aes_common/rotateleft.sv new file mode 100644 index 000000000..db7cb93fe --- /dev/null +++ b/src/ieu/aes_common/rotateleft.sv @@ -0,0 +1,34 @@ +/////////////////////////////////////////// +// rotateleft.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: RISC-V 32-bit left rotate +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rotate_left(input logic [31:0] input_data, + input logic [4:0] shamt, + output logic [31:0] rot_data); + + assign rot_data = (input_data << shamt) | (input_data >> (32 - shamt)); + +endmodule From 488583aed9620135b7e0faef2d5c83ca9f46b6d4 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 18:42:34 -0600 Subject: [PATCH 02/47] minor tweak --- src/ieu/aes_common/aes_inv_sbox_word.sv | 2 +- src/ieu/aes_common/aes_inv_shiftrow.sv | 23 ++++++++--------- src/ieu/aes_common/aes_mixcolumns.sv | 26 +++++++------------ src/ieu/aes_common/aes_sbox_word.sv | 12 +++------ src/ieu/aes_common/aes_shiftrow.sv | 29 ++++++++++----------- src/ieu/aes_common/galois_func.sv | 34 +++++++++++-------------- 6 files changed, 54 insertions(+), 72 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index 7e6c9efd7..cc92207ac 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox.sv +// aes_inv_sbox_word.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 7ff605d15..167c4cbb4 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -30,28 +30,28 @@ module aes_inv_shiftrow(input logic [127:0] dataIn, output logic [127:0] dataOut); - //Seperate the first (Least Significant) word into bytes + // Seperate the first (Least Significant) word into bytes logic [7:0] w0_b0 = dataIn[7:0]; logic [7:0] w0_b1 = dataIn[15:8]; logic [7:0] w0_b2 = dataIn[23:16]; logic [7:0] w0_b3 = dataIn[31:24]; - //Seperate the second word into bytes + // Seperate the second word into bytes logic [7:0] w1_b0 = dataIn[39:32]; logic [7:0] w1_b1 = dataIn[47:40]; logic [7:0] w1_b2 = dataIn[55:48]; logic [7:0] w1_b3 = dataIn[63:56]; - //Seperate the third word into bytes + // Seperate the third word into bytes logic [7:0] w2_b0 = dataIn[71:64]; logic [7:0] w2_b1 = dataIn[79:72]; logic [7:0] w2_b2 = dataIn[87:80]; logic [7:0] w2_b3 = dataIn[95:88]; - //Seperate the fourth (Most significant) word into bytes + // Seperate the fourth (Most significant) word into bytes logic [7:0] w3_b0 = dataIn[103:96]; logic [7:0] w3_b1 = dataIn[111:104]; logic [7:0] w3_b2 = dataIn[119:112]; logic [7:0] w3_b3 = dataIn[127:120]; - //The output words are composed of sets of the input bytes. + // The output words are composed of sets of the input bytes. logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; @@ -70,8 +70,7 @@ endmodule input selection. */ -module aes_shiftword(input logic[1:0] shiftAmt, - input logic [31:0] dataIn, +module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] dataIn, output logic [31:0] dataOut); @@ -83,15 +82,15 @@ module aes_shiftword(input logic[1:0] shiftAmt, always_comb begin case(shiftAmt) - //00 : Barrel Shift no bytes + // 00 : Barrel Shift no bytes 2'b00 : dataOut = {b3, b2, b1, b0}; - //01 : Barrel Shift one byte + // 01 : Barrel Shift one byte 2'b01 : dataOut = {b0, b3, b2, b1}; - //10 : Barrel Shift two bytes + // 10 : Barrel Shift two bytes 2'b10 : dataOut = {b1, b0, b3, b2}; - //11 : Barrel Shift three bytes + // 11 : Barrel Shift three bytes default : dataOut = {b2, b1, b0, b3}; endcase - end // always_comb + end endmodule diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index 0fa5d4b77..e3e953409 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -67,7 +67,7 @@ module aes_mixcolumns(data, mixedcols); endmodule // mixcolumns -//This applies the Galois field operations to an individual 32 bit word. +// This applies the Galois field operations to an individual 32 bit word. module mixword (word, mixed_word); // Declare Inputs/Outputs @@ -97,28 +97,20 @@ module mixword (word, mixed_word); assign b3 = word[7:0]; // mb0 Galois components - gm2 gm2_0(.gm2_in(b0), - .gm2_out(gm2_0_out)); - gm3 gm3_0(.gm3_in(b3), - .gm3_out(gm3_0_out)); + gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out)); + gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out)); // mb1 Galois components - gm2 gm2_1(.gm2_in(b1), - .gm2_out(gm2_1_out)); - gm3 gm3_1(.gm3_in(b0), - .gm3_out(gm3_1_out)); + gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out)); + gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out)); // mb2 Galois components - gm2 gm2_2(.gm2_in(b2), - .gm2_out(gm2_2_out)); - gm3 gm3_2(.gm3_in(b1), - .gm3_out(gm3_2_out)); + gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out)); + gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out)); // mb3 Galois components - gm2 gm2_3(.gm2_in(b3), - .gm2_out(gm2_3_out)); - gm3 gm3_3(.gm3_in(b2), - .gm3_out(gm3_3_out)); + gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out)); + gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out)); // Combine Componenets into mixed word assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 7f04eb7c0..588df6d90 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -31,16 +31,12 @@ module aes_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_sbox sbox_b0(.in(in[7:0]), - .out(out[7:0])); + aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_sbox sbox_b1(.in(in[15:8]), - .out(out[15:8])); + aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_sbox sbox_b2(.in(in[23:16]), - .out(out[23:16])); + aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_sbox sbox_b3(.in(in[31:24]), - .out(out[31:24])); + aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 58a3582b3..19bbdba8b 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -33,32 +33,31 @@ module aes_shiftrow(input logic [127:0] dataIn, // (This form of writing it may seem like more effort but I feel // like it is more self-explanatory this way without losing efficiency) - //Seperate the first (Least Significant) word into bytes + // Seperate the first (Least Significant) word into bytes logic [7:0] w0_b0 = dataIn[7:0]; logic [7:0] w0_b1 = dataIn[79:72]; logic [7:0] w0_b2 = dataIn[23:16]; logic [7:0] w0_b3 = dataIn[95:88]; - //Seperate the second word into bytes + // Seperate the second word into bytes logic [7:0] w1_b0 = dataIn[39:32]; logic [7:0] w1_b1 = dataIn[111:104]; logic [7:0] w1_b2 = dataIn[55:48]; logic [7:0] w1_b3 = dataIn[127:120]; - //Seperate the third word into bytes + // Seperate the third word into bytes logic [7:0] w2_b0 = dataIn[71:64]; logic [7:0] w2_b1 = dataIn[15:8]; logic [7:0] w2_b2 = dataIn[87:80]; logic [7:0] w2_b3 = dataIn[31:24]; - //Seperate the fourth (Most significant) word into bytes + // Seperate the fourth (Most significant) word into bytes logic [7:0] w3_b0 = dataIn[103:96]; logic [7:0] w3_b1 = dataIn[47:40]; logic [7:0] w3_b2 = dataIn[119:112]; - logic [7:0] w3_b3 = dataIn[63:56]; - - //The output words are composed of sets of the input bytes. - logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + logic [7:0] w3_b3 = dataIn[63:56]; + // The output words are composed of sets of the input bytes. + logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; assign dataOut = {out_w0, out_w1, out_w2, out_w3}; @@ -84,13 +83,13 @@ module aes_shiftwordbrutherr(input logic[1:0] shiftAmt, always_comb begin case(shiftAmt) - //00 : Barrel Shift no bytes + // 00 : Barrel Shift no bytes 2'b00 : dataOut = {b3, b2, b1, b0}; - //01 : Barrel Shift one byte + // 01 : Barrel Shift one byte 2'b01 : dataOut = {b2, b1, b0, b3}; - //10 : Barrel Shift two bytes + // 10 : Barrel Shift two bytes 2'b10 : dataOut = {b1, b0, b2, b3}; - //11 : Barrel Shift three bytes + // 11 : Barrel Shift three bytes default : dataOut = {b0, b1, b2, b3}; endcase end diff --git a/src/ieu/aes_common/galois_func.sv b/src/ieu/aes_common/galois_func.sv index 520764d60..a1a167df2 100644 --- a/src/ieu/aes_common/galois_func.sv +++ b/src/ieu/aes_common/galois_func.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// galois_func.sv +// Galois_func.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -35,7 +35,7 @@ module gm2 (gm2_in, gm2_out); // Set output to Galois Mult 2 assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); -endmodule // gm2 +endmodule module gm3 (gm3_in, gm3_out); @@ -63,10 +63,8 @@ module gm4 (gm4_in, gm4_out); logic [7:0] gm2_1_out; // Sub-Modules for multiple gm2 multiplications - gm2 gm2_0 (.gm2_in(gm4_in), - .gm2_out(gm2_0_out)); - gm2 gm2_1 (.gm2_in(gm2_0_out), - .gm2_out(gm2_1_out)); + gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out)); + gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out)); // Assign output to second gm2 output assign gm4_out = gm2_1_out; @@ -82,16 +80,14 @@ module gm8 (gm8_in, gm8_out); logic [7:0] gm2_0_out; logic [7:0] gm4_0_out; - // Sub-Modules for sub-galois operations - gm4 gm4_0 (.gm4_in(gm8_in), - .gm4_out(gm4_0_out)); - gm2 gm2_0 (.gm2_in(gm4_0_out), - .gm2_out(gm2_0_out)); + // Sub-Modules for sub-Galois operations + gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out)); + gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out)); // Assign output to gm2 output assign gm8_out = gm2_0_out; -endmodule // gm8 +endmodule module gm9 (gm9_in, gm9_out); @@ -101,7 +97,7 @@ module gm9 (gm9_in, gm9_out); // Internal Logic logic [7:0] gm8_0_out; - // Sub-Modules for sub-galois operations + // Sub-Modules for sub-Galois operations gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); // Set output to gm8(in) ^ in @@ -118,14 +114,14 @@ module gm11 (gm11_in, gm11_out); logic [7:0] gm8_0_out; logic [7:0] gm2_0_out; - // Sub-Modules for sub-galois operations + // Sub-Modules for sub-Galois operations gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); // Set output to gm8(in) ^ gm2(in) ^ in assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; -endmodule // gm11 +endmodule module gm13 (gm13_in, gm13_out); @@ -136,14 +132,14 @@ module gm13 (gm13_in, gm13_out); logic [7:0] gm8_0_out; logic [7:0] gm4_0_out; - // Sub-Modules for sub-galois operations + // Sub-Modules for sub-Galois operations gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); // Set output to gm8(in) ^ gm4(in) ^ in assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; -endmodule // gm13 +endmodule module gm14 (gm14_in, gm14_out); @@ -155,7 +151,7 @@ module gm14 (gm14_in, gm14_out); logic [7:0] gm4_0_out; logic [7:0] gm2_0_out; - // Sub-Modules for sub-galois operations + // Sub-Modules for sub-Galois operations gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); @@ -163,5 +159,5 @@ module gm14 (gm14_in, gm14_out); //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; -endmodule // gm14 +endmodule From 93d9bb4bc47ad06d0d6bfb60e19d1808063fb378 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 19:13:11 -0600 Subject: [PATCH 03/47] minor changes + date change on copyright --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 6 ++---- src/ieu/aes_common/aes_inv_sbox.sv | 6 ++---- src/ieu/aes_common/aes_inv_sbox_128.sv | 14 ++++++-------- src/ieu/aes_common/aes_inv_sbox_word.sv | 14 ++++++-------- src/ieu/aes_common/aes_inv_shiftrow.sv | 17 +++++++---------- src/ieu/aes_common/aes_mixcolumns.sv | 21 ++++++--------------- src/ieu/aes_common/aes_sbox.sv | 6 ++---- src/ieu/aes_common/aes_sbox_word.sv | 6 ++---- src/ieu/aes_common/aes_shiftrow.sv | 6 ++---- src/ieu/aes_common/galois_func.sv | 8 +++----- src/ieu/aes_common/rotateleft.sv | 4 ++-- 11 files changed, 40 insertions(+), 68 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index ed82f053e..0270bd084 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V AES Mix Columns +// Purpose: AES Inverted Mix Column Function for use with AES // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index ca6c1c054..a364f75db 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V Rinjdael Inverted S-BOX +// Purpose: Rinjdael Inverted S-BOX in form of a LUT // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/aes_inv_sbox_128.sv b/src/ieu/aes_common/aes_inv_sbox_128.sv index a5c6faa3f..5c1bc10be 100644 --- a/src/ieu/aes_common/aes_inv_sbox_128.sv +++ b/src/ieu/aes_common/aes_inv_sbox_128.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V 128-bit Inverse Substitution box +// Purpose: 128-bit Inverse Substitution box comprised of 4x32-bit inverse s-boxes // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -30,13 +28,13 @@ module aes_inv_sbox_128(input logic [127:0] in, output logic [127:0] out); - //Declare the SBOX for (least significant) word 0 of the input + // Declare the SBOX for (least significant) word 0 of the input aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0])); - //Declare the SBOX for word 1 of the input + // Declare the SBOX for word 1 of the input aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32])); - //Declare the SBOX for word 2 of the input + // Declare the SBOX for word 2 of the input aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64])); - //Declare the SBOX for word 3 of the input + // Declare the SBOX for word 3 of the input aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96])); endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index cc92207ac..d2b18d7db 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V Rinjdael Inverted S-BOX +// Purpose: 4 sets of Rinjdael Inverse S-BOX for whole word look up // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -30,13 +28,13 @@ module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out); - //Declare the SBOX for (least significant) byte 0 of the input + // Declare the SBOX for (least significant) byte 0 of the input aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); - //Declare the SBOX for byte 1 of the input + // Declare the SBOX for byte 1 of the input aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); - //Declare the SBOX for byte 2 of the input + // Declare the SBOX for byte 2 of the input aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); - //Declare the SBOX for byte 3 of the input + // Declare the SBOX for byte 3 of the input aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 167c4cbb4..8cd94b7d3 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V AES Shiftrow +// Purpose: AES Shiftrow // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -30,27 +28,26 @@ module aes_inv_shiftrow(input logic [127:0] dataIn, output logic [127:0] dataOut); - // Seperate the first (Least Significant) word into bytes + // Separate the first (Least Significant) word into bytes logic [7:0] w0_b0 = dataIn[7:0]; logic [7:0] w0_b1 = dataIn[15:8]; logic [7:0] w0_b2 = dataIn[23:16]; logic [7:0] w0_b3 = dataIn[31:24]; - // Seperate the second word into bytes + // Separate the second word into bytes logic [7:0] w1_b0 = dataIn[39:32]; logic [7:0] w1_b1 = dataIn[47:40]; logic [7:0] w1_b2 = dataIn[55:48]; logic [7:0] w1_b3 = dataIn[63:56]; - // Seperate the third word into bytes + // Separate the third word into bytes logic [7:0] w2_b0 = dataIn[71:64]; logic [7:0] w2_b1 = dataIn[79:72]; logic [7:0] w2_b2 = dataIn[87:80]; logic [7:0] w2_b3 = dataIn[95:88]; - // Seperate the fourth (Most significant) word into bytes + // Separate the fourth (Most significant) word into bytes logic [7:0] w3_b0 = dataIn[103:96]; logic [7:0] w3_b1 = dataIn[111:104]; logic [7:0] w3_b2 = dataIn[119:112]; - logic [7:0] w3_b3 = dataIn[127:120]; - + logic [7:0] w3_b3 = dataIn[127:120]; // The output words are composed of sets of the input bytes. logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index e3e953409..701fa9420 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V "Mix Columns" +// Purpose: AES "Mix Columns" Operation // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -76,17 +74,13 @@ module mixword (word, mixed_word); // Declare Internal Signals logic [7:0] b0, b1, b2, b3; - logic [7:0] mb0, mb1, mb2, mb3; - + logic [7:0] mb0, mb1, mb2, mb3; logic [7:0] gm2_0_out; - logic [7:0] gm3_0_out; - + logic [7:0] gm3_0_out; logic [7:0] gm2_1_out; - logic [7:0] gm3_1_out; - + logic [7:0] gm3_1_out; logic [7:0] gm2_2_out; - logic [7:0] gm3_2_out; - + logic [7:0] gm3_2_out; logic [7:0] gm2_3_out; logic [7:0] gm3_3_out; @@ -99,15 +93,12 @@ module mixword (word, mixed_word); // mb0 Galois components gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out)); gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out)); - // mb1 Galois components gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out)); gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out)); - // mb2 Galois components gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out)); gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out)); - // mb3 Galois components gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out)); gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out)); diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv index 8f6901cdc..2b4491986 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aes_sbox.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V Rinjdael forward S-BOX in the form of a LUT +// Purpose: Rinjdael forward S-BOX in the form of a LUT // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 588df6d90..17312585b 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously. +// Purpose: 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously. // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 19bbdba8b..ac82d38f8 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -4,14 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V aes_shiftrow for taking in first data line +// Purpose: aes_shiftrow for taking in first data line // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/galois_func.sv b/src/ieu/aes_common/galois_func.sv index a1a167df2..d18bc91f9 100644 --- a/src/ieu/aes_common/galois_func.sv +++ b/src/ieu/aes_common/galois_func.sv @@ -1,17 +1,15 @@ /////////////////////////////////////////// -// Galois_func.sv +// galois_func.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V Galois field operations for mix columns operation +// Purpose: Galois field operations for mix columns operation // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) -// // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // diff --git a/src/ieu/aes_common/rotateleft.sv b/src/ieu/aes_common/rotateleft.sv index db7cb93fe..363e3526c 100644 --- a/src/ieu/aes_common/rotateleft.sv +++ b/src/ieu/aes_common/rotateleft.sv @@ -4,12 +4,12 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: RISC-V 32-bit left rotate +// Purpose: 32-bit left rotate for AES // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // From 2cf1d43ec57acc21ec7398a2e61153b385a7f8b5 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 19:39:26 -0600 Subject: [PATCH 04/47] add aes instructions --- src/ieu/aes_instructions/aes32dsi.sv | 55 ++++++++++++ src/ieu/aes_instructions/aes32dsmi.sv | 58 +++++++++++++ src/ieu/aes_instructions/aes32esi.sv | 56 ++++++++++++ src/ieu/aes_instructions/aes32esmi.sv | 59 +++++++++++++ src/ieu/aes_instructions/aes64ds.sv | 45 ++++++++++ src/ieu/aes_instructions/aes64dsm.sv | 53 ++++++++++++ src/ieu/aes_instructions/aes64es.sv | 41 +++++++++ src/ieu/aes_instructions/aes64esm.sv | 47 ++++++++++ src/ieu/aes_instructions/aes64im.sv | 34 ++++++++ src/ieu/aes_instructions/aes64ks1i.sv | 120 ++++++++++++++++++++++++++ src/ieu/aes_instructions/aes64ks2.sv | 40 +++++++++ 11 files changed, 608 insertions(+) create mode 100644 src/ieu/aes_instructions/aes32dsi.sv create mode 100644 src/ieu/aes_instructions/aes32dsmi.sv create mode 100644 src/ieu/aes_instructions/aes32esi.sv create mode 100644 src/ieu/aes_instructions/aes32esmi.sv create mode 100644 src/ieu/aes_instructions/aes64ds.sv create mode 100644 src/ieu/aes_instructions/aes64dsm.sv create mode 100644 src/ieu/aes_instructions/aes64es.sv create mode 100644 src/ieu/aes_instructions/aes64esm.sv create mode 100644 src/ieu/aes_instructions/aes64im.sv create mode 100644 src/ieu/aes_instructions/aes64ks1i.sv create mode 100644 src/ieu/aes_instructions/aes64ks2.sv diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv new file mode 100644 index 000000000..914ec8994 --- /dev/null +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// aes32dsi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32dsi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32dsi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] so_rotate; + + // shamt = bs * 8 + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte + assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box + assign so = {24'h000000,sbox_out}; + // Rotate the substitution box output left by shamt (bs * 8) + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" + assign data_out = rs1 ^ so_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv new file mode 100644 index 000000000..e3b750b79 --- /dev/null +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// aes32dsmi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32dsmi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32dsmi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] mixed; + logic [31:0] mixed_rotate; + + // shamt = bs * 8 + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte + assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box + assign so = {24'h000000,sbox_out}; + // Run so through the mixword AES function + inv_mixword mix(.word(so),.mixed_word(mixed)); + // Rotate the substitution box output left by shamt (bs * 8) + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" + assign data_out = rs1 ^ mixed_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv new file mode 100644 index 000000000..2281c6f4e --- /dev/null +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// aes32esi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32esi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32esi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] so_rotate; + + // Shift bs by 3 to get shamt + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box + assign sbox_in = sbox_in_32[7:0]; + // Substitute + aes_sbox subbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output + assign so = {24'h000000,sbox_out}; + // Rotate so left by shamt + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); + assign data_out = rs1 ^ so_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv new file mode 100644 index 000000000..382c1da5d --- /dev/null +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// aes32esmi.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32esmi instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32esmi(input logic [1:0] bs, + input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare Intermediary logic + logic [4:0] shamt; + logic [31:0] sbox_in_32; + logic [7:0] sbox_in; + logic [7:0] sbox_out; + logic [31:0] so; + logic [31:0] mixed; + logic [31:0] mixed_rotate; + + // Shift bs by 3 to get shamt + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box + assign sbox_in = sbox_in_32[7:0]; + // Substitute + aes_sbox sbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output + assign so = {24'h000000,sbox_out}; + // Mix Word using aes_mixword component + mixword mwd(.word(so),.mixed_word(mixed)); + // Rotate so left by shamt + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); + assign data_out = rs1 ^ mixed_rotate; + +endmodule diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv new file mode 100644 index 000000000..4ba657ea7 --- /dev/null +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// aes64ds.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ds instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ds(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Logic + logic [127:0] shiftRow_out; + logic [31:0] sbox_out_0; + logic [31:0] sbox_out_1; + + // Apply inverse shiftrows to rs2 and rs1 + aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Concatenate the two substitution outputs to get result + assign data_out = {sbox_out_1, sbox_out_0}; + +endmodule diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv new file mode 100644 index 000000000..4ed5eef13 --- /dev/null +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// aes64dsm.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64dsm instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64dsm(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Logic + logic [127:0] shiftRow_out; + logic [31:0] sbox_out_0; + logic [31:0] sbox_out_1; + logic [31:0] mixcol_out_0; + logic [31:0] mixcol_out_1; + + // Apply inverse shiftrows to rs2 and rs1 + aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Apply inverse mixword to sbox outputs + inv_mixword inv_mw_0(.word(sbox_out_0),.mixed_word(mixcol_out_0)); + inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1)); + // Concatenate mixed words for output + assign data_out = {mixcol_out_1,mixcol_out_0}; + +endmodule + + + diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv new file mode 100644 index 000000000..4f665f030 --- /dev/null +++ b/src/ieu/aes_instructions/aes64es.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// aes64es.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64es instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64es(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Signals + logic [127:0] shiftRow_out; + + // AES shiftrow unit + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(data_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(data_out[63:32])); + +endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv new file mode 100644 index 000000000..51c5474ac --- /dev/null +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// aes64esm.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64esm instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64esm(input logic [63:0] rs1, + input logic [63:0] rs2, + output logic [63:0] data_out); + + // Intermediary Signals + logic [127:0] shiftRow_out; + logic [63:0] sbox_out; + + // AES shiftrow unit + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32])); + // Apply mix columns operations + mixword mw0(.word(sbox_out[31:0]),.mixed_word(data_out[31:0])); + mixword mw1(.word(sbox_out[63:32]),.mixed_word(data_out[63:32])); + +endmodule + + diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv new file mode 100644 index 000000000..9a898ef89 --- /dev/null +++ b/src/ieu/aes_instructions/aes64im.sv @@ -0,0 +1,34 @@ +/////////////////////////////////////////// +// aes64im.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64im instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64im(input logic [63:0] rs1, + output logic [63:0] data_out); + + inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0])); + inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32])); + +endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv new file mode 100644 index 000000000..6ebfe35eb --- /dev/null +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -0,0 +1,120 @@ +/////////////////////////////////////////// +// aes64ks1i.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks1i(input logic [3:0] roundnum, + input logic [63:0] rs1, + output logic [63:0] rd); + + // Instantiate intermediary logic signals + logic [7:0] rcon_preshift; + logic [31:0] rcon; + logic lastRoundFlag; + logic [31:0] rs1_rotate; + logic [31:0] tmp2; + logic [31:0] sbox_out; + + // Get rcon value from table + rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + // Shift RCON value + assign rcon = {24'b0, rcon_preshift}; + // Flag will be set if roundnum = 0xA = 0b1010 + assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0]; + // Get rotated value fo ruse in tmp2 + rrot8 rr(.x(rs1[63:32]), .result(rs1_rotate)); + // Assign tmp2 to a mux based on lastRoundFlag + assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; + // Substitute bytes of value obtained for tmp2 using Rijndael sbox + aes_sbox_word sbox(.in(tmp2),.out(sbox_out)); + assign rd[31:0] = sbox_out ^ rcon; + assign rd[63:32] = sbox_out ^ rcon; + + // There may be some errors with this instruction. + // Regression tests are passed successfully, but + // the algorithm seems wrong. Check later. + +endmodule + +module rcon_lut_128(input logic [3:0] RD, + output logic [7:0] rcon_out); + + always_comb + begin + case(RD) + 4'h0 : rcon_out = 8'h01; + 4'h1 : rcon_out = 8'h02; + 4'h2 : rcon_out = 8'h04; + 4'h3 : rcon_out = 8'h08; + 4'h4 : rcon_out = 8'h10; + 4'h5 : rcon_out = 8'h20; + 4'h6 : rcon_out = 8'h40; + 4'h7 : rcon_out = 8'h80; + 4'h8 : rcon_out = 8'h1b; + 4'h9 : rcon_out = 8'h36; + 4'hA : rcon_out = 8'h00; + default : rcon_out = 8'h00; + endcase + end + +endmodule + +module rrot8(input logic[31:0] x, + output logic [31:0] result); + + assign result[0] = x[8]; + assign result[1] = x[9]; + assign result[2] = x[10]; + assign result[3] = x[11]; + assign result[4] = x[12]; + assign result[5] = x[13]; + assign result[6] = x[14]; + assign result[7] = x[15]; + assign result[8] = x[16]; + assign result[9] = x[17]; + assign result[10] = x[18]; + assign result[11] = x[19]; + assign result[12] = x[20]; + assign result[13] = x[21]; + assign result[14] = x[22]; + assign result[15] = x[23]; + assign result[16] = x[24]; + assign result[17] = x[25]; + assign result[18] = x[26]; + assign result[19] = x[27]; + assign result[20] = x[28]; + assign result[21] = x[29]; + assign result[22] = x[30]; + assign result[23] = x[31]; + assign result[24] = x[0]; + assign result[25] = x[1]; + assign result[26] = x[2]; + assign result[27] = x[3]; + assign result[28] = x[4]; + assign result[29] = x[5]; + assign result[30] = x[6]; + assign result[31] = x[7]; + +endmodule diff --git a/src/ieu/aes_instructions/aes64ks2.sv b/src/ieu/aes_instructions/aes64ks2.sv new file mode 100644 index 000000000..c2381bcd5 --- /dev/null +++ b/src/ieu/aes_instructions/aes64ks2.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// aes64ks2.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks2 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks2(input logic [63:0] rs2, + input logic [63:0] rs1, + output logic [63:0] rd); + + // Instantiate Intermediary logic + logic [31:0] w0; + logic [31:0] w1; + + assign w0 = rs1[63:32] ^ rs2[31:0]; + assign w1 = rs1[63:32] ^ rs2[31:0] ^ rs2[63:32]; + assign rd = {w1, w0}; + +endmodule From 38348f9784c0689636cc0018addb6034915d38ff Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 20:01:12 -0600 Subject: [PATCH 05/47] Add SHA instructions --- src/ieu/sha_instructions/sha256sig0.sv | 48 +++++++++++++++++++++ src/ieu/sha_instructions/sha256sig1.sv | 48 +++++++++++++++++++++ src/ieu/sha_instructions/sha256sum0.sv | 48 +++++++++++++++++++++ src/ieu/sha_instructions/sha256sum1.sv | 48 +++++++++++++++++++++ src/ieu/sha_instructions/sha512sig0.sv | 41 ++++++++++++++++++ src/ieu/sha_instructions/sha512sig0h.sv | 53 ++++++++++++++++++++++++ src/ieu/sha_instructions/sha512sig0l.sv | 54 ++++++++++++++++++++++++ src/ieu/sha_instructions/sha512sig1.sv | 41 ++++++++++++++++++ src/ieu/sha_instructions/sha512sig1h.sv | 52 +++++++++++++++++++++++ src/ieu/sha_instructions/sha512sig1l.sv | 54 ++++++++++++++++++++++++ src/ieu/sha_instructions/sha512sum0.sv | 41 ++++++++++++++++++ src/ieu/sha_instructions/sha512sum0r.sv | 55 +++++++++++++++++++++++++ src/ieu/sha_instructions/sha512sum1.sv | 41 ++++++++++++++++++ src/ieu/sha_instructions/sha512sum1r.sv | 55 +++++++++++++++++++++++++ 14 files changed, 679 insertions(+) create mode 100644 src/ieu/sha_instructions/sha256sig0.sv create mode 100644 src/ieu/sha_instructions/sha256sig1.sv create mode 100644 src/ieu/sha_instructions/sha256sum0.sv create mode 100644 src/ieu/sha_instructions/sha256sum1.sv create mode 100644 src/ieu/sha_instructions/sha512sig0.sv create mode 100644 src/ieu/sha_instructions/sha512sig0h.sv create mode 100644 src/ieu/sha_instructions/sha512sig0l.sv create mode 100644 src/ieu/sha_instructions/sha512sig1.sv create mode 100644 src/ieu/sha_instructions/sha512sig1h.sv create mode 100644 src/ieu/sha_instructions/sha512sig1l.sv create mode 100644 src/ieu/sha_instructions/sha512sum0.sv create mode 100644 src/ieu/sha_instructions/sha512sum0r.sv create mode 100644 src/ieu/sha_instructions/sha512sum1.sv create mode 100644 src/ieu/sha_instructions/sha512sum1r.sv diff --git a/src/ieu/sha_instructions/sha256sig0.sv b/src/ieu/sha_instructions/sha256sig0.sv new file mode 100644 index 000000000..069e99a29 --- /dev/null +++ b/src/ieu/sha_instructions/sha256sig0.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// sha256sig0.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha256sig0 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha256sig0 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] rs1, + output logic [WIDTH-1:0] result); + + logic [31:0] ror7; + logic [31:0] ror18; + logic [31:0] sh3; + logic [31:0] exts; + + assign ror7 = {rs1[6:0], rs1[31:7]}; + assign ror18 = {rs1[17:0], rs1[31:18]}; + assign sh3 = {3'b0, rs1[31:3]}; + + // Assign output to xor of 3 rotates + assign exts = ror7 ^ ror18 ^ sh3; + if (WIDTH==32) + assign result = exts; + else + assign result = {{32{exts[31]}}, exts}; + +endmodule diff --git a/src/ieu/sha_instructions/sha256sig1.sv b/src/ieu/sha_instructions/sha256sig1.sv new file mode 100644 index 000000000..44f383d25 --- /dev/null +++ b/src/ieu/sha_instructions/sha256sig1.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// sha256sig1.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha256sig1 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha256sig1 #(parameter WIDTH=32) + (input logic [WIDTH-1:0] rs1, + output logic [WIDTH-1:0] result); + + logic [31:0] ror17; + logic [31:0] ror19; + logic [31:0] sh10; + logic [31:0] exts; + + assign ror17 = {rs1[16:0], rs1[31:17]}; + assign ror19 = {rs1[18:0], rs1[31:19]}; + assign sh10 = {10'b0, rs1[31:10]}; + + // Assign output to xor of 3 rotates + assign exts = ror17 ^ ror19 ^ sh10; + if (WIDTH==32) + assign result = exts; + else + assign result = {{32{exts[31]}}, exts}; + +endmodule diff --git a/src/ieu/sha_instructions/sha256sum0.sv b/src/ieu/sha_instructions/sha256sum0.sv new file mode 100644 index 000000000..27a59bb21 --- /dev/null +++ b/src/ieu/sha_instructions/sha256sum0.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// sha256sum0.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha256sum0 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha256sum0 #(parameter WIDTH=32) + (input logic [WIDTH-1:0] rs1, + output logic [WIDTH-1:0] result); + + logic [31:0] ror2; + logic [31:0] ror13; + logic [31:0] ror22; + logic [31:0] exts; + + assign ror2 = {rs1[1:0], rs1[31:2]}; + assign ror13 = {rs1[12:0], rs1[31:13]}; + assign ror22 = {rs1[21:0], rs1[31:22]}; + + // Assign output to xor of 3 rotates + assign exts = ror2 ^ ror13 ^ ror22; + if (WIDTH==32) + assign result = exts; + else + assign result = {{32{exts[31]}}, exts}; + +endmodule diff --git a/src/ieu/sha_instructions/sha256sum1.sv b/src/ieu/sha_instructions/sha256sum1.sv new file mode 100644 index 000000000..e1a0560b6 --- /dev/null +++ b/src/ieu/sha_instructions/sha256sum1.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// sha256sum1.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha256sum1 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha256sum1 #(parameter WIDTH=32) + (input logic [WIDTH-1:0] rs1, + output logic [WIDTH-1:0] result); + + logic [31:0] ror6; + logic [31:0] ror11; + logic [31:0] ror25; + logic [31:0] exts; + + assign ror6 = {rs1[5:0], rs1[31:6]}; + assign ror11 = {rs1[10:0], rs1[31:11]}; + assign ror25 = {rs1[24:0], rs1[31:25]}; + + // Assign output to xor of 3 rotates + assign exts = ror6 ^ ror11 ^ ror25; + if (WIDTH==32) + assign result = exts; + else + assign result = {{32{exts[31]}}, exts}; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sig0.sv b/src/ieu/sha_instructions/sha512sig0.sv new file mode 100644 index 000000000..9f2cec04a --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig0.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// sha512sig0.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha512sig0 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig0 (input logic [63:0] rs1, output logic [63:0] result); + + logic [63:0] ror1; + logic [63:0] ror8; + logic [63:0] sh7; + + assign ror1 = {rs1[0], rs1[63:1]}; + assign ror8 = {rs1[7:0], rs1[63:8]}; + assign sh7 = rs1 >> 7; + + // Assign output to xor of 3 rotates + assign result = ror1 ^ ror8 ^ sh7; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sig0h.sv b/src/ieu/sha_instructions/sha512sig0h.sv new file mode 100644 index 000000000..fb23c135a --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig0h.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// sha512sig0h.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha512sig0h instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig0h(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // RS1 Shifts + logic [31:0] shift1; + logic [31:0] shift7; + logic [31:0] shift8; + + // RS2 Shifts + logic [31:0] shift31; + logic [31:0] shift24; + + // Shift rs1 + assign shift1 = rs1 >> 1; + assign shift7 = rs1 >> 7; + assign shift8 = rs1 >> 8; + + // Shift rs2 + assign shift31 = rs2 << 31; + assign shift24 = rs2 << 24; + + // XOR to get result + assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sig0l.sv b/src/ieu/sha_instructions/sha512sig0l.sv new file mode 100644 index 000000000..3702b18bb --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig0l.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// sha512sig0l.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha512sig0l instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig0l(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // rs1 operations + logic [31:0] shift1; + logic [31:0] shift7; + logic [31:0] shift8; + + // rs2 operations + logic [31:0] shift31; + logic [31:0] shift25; + logic [31:0] shift24; + + // rs1 shifts + assign shift1 = rs1 >> 1; + assign shift7 = rs1 >> 7; + assign shift8 = rs1 >> 8; + + // rs2 shifts + assign shift31 = rs2 << 31; + assign shift25 = rs2 << 25; + assign shift24 = rs2 << 24; + + assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sig1.sv b/src/ieu/sha_instructions/sha512sig1.sv new file mode 100644 index 000000000..1299df813 --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig1.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// sha512sig1.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 6 February 2024 +// +// Purpose: sha512sig1 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig1 (input logic [63:0] rs1, output logic [63:0] result); + + logic [63:0] ror19; + logic [63:0] ror61; + logic [63:0] sh6; + + assign ror19 = {rs1[18:0], rs1[63:19]}; + assign ror61 = {rs1[60:0], rs1[63:61]}; + assign sh6 = rs1 >> 6; + + // Assign output to xor of 3 rotates + assign result = ror19 ^ ror61 ^ sh6; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sig1h.sv b/src/ieu/sha_instructions/sha512sig1h.sv new file mode 100644 index 000000000..05fd66cd1 --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig1h.sv @@ -0,0 +1,52 @@ +/////////////////////////////////////////// +// sha512sig1h.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha512sig1h instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig1h(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // rs1 shifts + logic [31:0] shift3; + logic [31:0] shift6; + logic [31:0] shift19; + // rs2 shifts + logic [31:0] shift29; + logic [31:0] shift13; + + // shift rs1 + assign shift3 = rs1 << 3; + assign shift6 = rs1 >> 6; + assign shift19 = rs1 >> 19; + // shift rs2 + assign shift29 = rs2 >> 29; + assign shift13 = rs2 << 13; + + // XOR Shifted registers for output + assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13; + +endmodule + diff --git a/src/ieu/sha_instructions/sha512sig1l.sv b/src/ieu/sha_instructions/sha512sig1l.sv new file mode 100644 index 000000000..570664a26 --- /dev/null +++ b/src/ieu/sha_instructions/sha512sig1l.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// sha512sig1l.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: sha512sig1l instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sig1l(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // rs1 shift logic + logic [31:0] shift3; + logic [31:0] shift6; + logic [31:0] shift19; + + // rs2 shift logics + logic [31:0] shift29; + logic [31:0] shift26; + logic [31:0] shift13; + + // Shift rs1 + assign shift3 = rs1 << 3; + assign shift6 = rs1 >> 6; + assign shift19 = rs1 >> 19; + + // Shift rs2 + assign shift29 = rs2 >> 29; + assign shift26 = rs2 << 26; + assign shift13 = rs2 << 13; + + assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sum0.sv b/src/ieu/sha_instructions/sha512sum0.sv new file mode 100644 index 000000000..dcd8c97d4 --- /dev/null +++ b/src/ieu/sha_instructions/sha512sum0.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// sha512sum0.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 6 February 2024 +// +// Purpose: sha512sum0 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sum0 (input logic [63:0] rs1, output logic [63:0] result); + + logic [63:0] ror28; + logic [63:0] ror34; + logic [63:0] ror39; + + assign ror28 = {rs1[27:0], rs1[63:28]}; + assign ror34 = {rs1[33:0], rs1[63:34]}; + assign ror39 = {rs1[38:0], rs1[63:39]}; + + // Assign output to xor of 3 rotates + assign result = ror28 ^ ror34 ^ ror39; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sum0r.sv b/src/ieu/sha_instructions/sha512sum0r.sv new file mode 100644 index 000000000..bee3b7551 --- /dev/null +++ b/src/ieu/sha_instructions/sha512sum0r.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// sha512sum0r.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 6 February 2024 +// +// Purpose: sha512sum0r instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sum0r(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // RS1 shifts + logic [31:0] shift25; + logic [31:0] shift30; + logic [31:0] shift28; + + // RS2 shifts + logic [31:0] shift7; + logic [31:0] shift2; + logic [31:0] shift4; + + // Shift rs1 + assign shift25 = rs1 << 25; + assign shift30 = rs1 << 30; + assign shift28 = rs1 >> 28; + + // Shift rs2 + assign shift7 = rs2 >> 7; + assign shift2 = rs2 >> 2; + assign shift4 = rs2 << 4; + + // Set output to XOR of shifted values + assign data_out = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sum1.sv b/src/ieu/sha_instructions/sha512sum1.sv new file mode 100644 index 000000000..91c60ef7b --- /dev/null +++ b/src/ieu/sha_instructions/sha512sum1.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// sha512sum1.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 6 February 2024 +// +// Purpose: sha512sum1 instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sum1 (input logic [63:0] rs1, output logic [63:0] result); + + logic [63:0] ror14; + logic [63:0] ror18; + logic [63:0] ror41; + + assign ror14 = {rs1[13:0], rs1[63:14]}; + assign ror18 = {rs1[17:0], rs1[63:18]}; + assign ror41 = {rs1[40:0], rs1[63:41]}; + + // Assign output to xor of 3 rotates + assign result = ror14 ^ ror18 ^ ror41; + +endmodule diff --git a/src/ieu/sha_instructions/sha512sum1r.sv b/src/ieu/sha_instructions/sha512sum1r.sv new file mode 100644 index 000000000..48428a69f --- /dev/null +++ b/src/ieu/sha_instructions/sha512sum1r.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// sha512sum1r.sv +// +// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 6 February 2024 +// +// Purpose: sha512sum1r instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512sum1r(input logic [31:0] rs1, + input logic [31:0] rs2, + output logic [31:0] data_out); + + // Declare logic for rs1 shifts + logic [31:0] shift1_23; + logic [31:0] shift1_14; + logic [31:0] shift1_18; + + // Declare logic for rs2 shifts + logic [31:0] shift2_9; + logic [31:0] shift2_18; + logic [31:0] shift2_14; + + // Shift RS1 + assign shift1_23 = rs1 << 23; + assign shift1_14 = rs1 >> 14; + assign shift1_18 = rs1 >> 18; + + // Shift RS2 + assign shift2_9 = rs2 >> 9; + assign shift2_18 = rs2 << 18; + assign shift2_14 = rs2 << 14; + + // Assign output to xor of shifts + assign data_out = shift1_23 ^ shift1_14 ^ shift1_18 ^ shift2_9 ^ shift2_18 ^ shift2_14; + +endmodule From 32be22565a34458638715fc957e0f76c76f6e063 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 20:18:50 -0600 Subject: [PATCH 06/47] add kmu instruction --- src/ieu/kmu/packer.sv | 67 +++++++++++++++++++++++++++++++++++++++ src/ieu/kmu/revop.sv | 44 ++++++++++++++++++++++++++ src/ieu/kmu/zbkb.sv | 46 +++++++++++++++++++++++++++ src/ieu/kmu/zbkc.sv | 55 ++++++++++++++++++++++++++++++++ src/ieu/kmu/zbkx.sv | 50 +++++++++++++++++++++++++++++ src/ieu/kmu/zipper.sv | 47 +++++++++++++++++++++++++++ src/ieu/kmu/zknd_32.sv | 44 ++++++++++++++++++++++++++ src/ieu/kmu/zknd_64.sv | 51 ++++++++++++++++++++++++++++++ src/ieu/kmu/zkne_32.sv | 44 ++++++++++++++++++++++++++ src/ieu/kmu/zkne_64.sv | 50 +++++++++++++++++++++++++++++ src/ieu/kmu/zknh_32.sv | 72 ++++++++++++++++++++++++++++++++++++++++++ src/ieu/kmu/zknh_64.sv | 65 ++++++++++++++++++++++++++++++++++++++ 12 files changed, 635 insertions(+) create mode 100644 src/ieu/kmu/packer.sv create mode 100644 src/ieu/kmu/revop.sv create mode 100644 src/ieu/kmu/zbkb.sv create mode 100644 src/ieu/kmu/zbkc.sv create mode 100644 src/ieu/kmu/zbkx.sv create mode 100644 src/ieu/kmu/zipper.sv create mode 100644 src/ieu/kmu/zknd_32.sv create mode 100644 src/ieu/kmu/zknd_64.sv create mode 100644 src/ieu/kmu/zkne_32.sv create mode 100644 src/ieu/kmu/zkne_64.sv create mode 100644 src/ieu/kmu/zknh_32.sv create mode 100644 src/ieu/kmu/zknh_64.sv diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv new file mode 100644 index 000000000..42702d89c --- /dev/null +++ b/src/ieu/kmu/packer.sv @@ -0,0 +1,67 @@ +/////////////////////////////////////////// +// packer.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 5 October 2023 +// +// Purpose: RISCV kbitmanip pack operation unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module packer #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] PackSelect, + output logic [WIDTH-1:0] PackResult); + + logic [WIDTH/2-1:0] low_half, high_half; + logic [7:0] low_halfh, high_halfh; + logic [15:0] low_halfw, high_halfw; + + logic [WIDTH-1:0] Pack; + logic [WIDTH-1:0] PackH; + logic [WIDTH-1:0] PackW; + logic [1:0] MuxSelect; + + assign low_half = A[WIDTH/2-1:0]; + assign high_half = B[WIDTH/2-1:0]; + assign low_halfh = A[7:0]; + assign high_halfh = B[7:0]; + assign low_halfw = A[15:0]; + assign high_halfw = B[15:0]; + + assign Pack = {high_half, low_half}; + assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; + assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; + + // TODO: FIX THIS ... this is completely incorrect way to use if statements + // Solution for now: + always_comb + begin + if (PackSelect[1:0] == 2'b11) + MuxSelect = 2'b01; + else if (PackSelect[2] == 1'b0) + MuxSelect = 2'b00; + else + MuxSelect = 2'b10; + end + + mux3 #(WIDTH) PackMux(Pack, PackH, PackW, MuxSelect, PackResult); + +endmodule diff --git a/src/ieu/kmu/revop.sv b/src/ieu/kmu/revop.sv new file mode 100644 index 000000000..901e1532e --- /dev/null +++ b/src/ieu/kmu/revop.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// revop.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 5 October 2023 +// +// Purpose: RISCV kbitmanip reverse byte-wise operation unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module revop #(parameter WIDTH=32) + (input logic [WIDTH-1:0] A, // Operands + input logic [WIDTH-1:0] RevA, // A Reversed + input logic revType, // rev8 or brev8 (LSB of immediate) + output logic [WIDTH-1:0] RevResult); // results + + logic [WIDTH-1:0] Rev8Result, Brev8Result; + genvar i; + + for (i=0; i> i) & 1; + if(if_temp[0]) temp = temp ^ (A >> (WIDTH-i)); + else temp = temp; + end + end + else begin // clmul + for (i=0; i> i) & 1; + if(if_temp[0]) temp = temp ^ (A << i); + else temp = temp; + end + end + end + assign ZBKCResult = temp; + +endmodule diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv new file mode 100644 index 000000000..9d42dd372 --- /dev/null +++ b/src/ieu/kmu/zbkx.sv @@ -0,0 +1,50 @@ +/////////////////////////////////////////// +// zbkx.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 1 February 2024 +// +// Purpose: RISC-V ZBKX top level unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module zbkx #(parameter WIDTH=32) + (input logic [WIDTH-1:0] A, B, + input logic [2:0] ZBKXSelect, + output logic [WIDTH-1:0] ZBKXResult); + + logic [WIDTH-1:0] xperm_lookup[0:WIDTH]; + logic [WIDTH-1:0] XPERM8_Result; + logic [WIDTH-1:0] XPERM4_Result; + genvar i; + + for(i=0; i> {B[i+7:i], 3'b0}; + assign XPERM8_Result[i+7:i] = xperm_lookup[i][7:0]; + end + + for(i=0; i> {B[i+3:i], 2'b0}; + assign XPERM4_Result[i+3:i] = xperm_lookup[i+1][3:0]; + end + + mux2 #(WIDTH) ZbkxMux (XPERM8_Result, XPERM4_Result, ZBKXSelect[0], ZBKXResult); + +endmodule diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv new file mode 100644 index 000000000..acbd36355 --- /dev/null +++ b/src/ieu/kmu/zipper.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// zipper.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 9 October 2023 +// +// Purpose: RISCV kbitmanip zip operation unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module zipper #(parameter WIDTH=64) + (input logic [WIDTH-1:0] A, + input logic ZipSelect, + output logic [WIDTH-1:0] ZipResult); + + logic [WIDTH-1:0] zip; + logic [WIDTH-1:0] unzip; + genvar i; + + for (i=0; i Date: Tue, 20 Feb 2024 22:55:34 -0600 Subject: [PATCH 07/47] separate galois function SV per the style file --- src/ieu/aes_common/galois_func.sv | 161 ------------------------------ src/ieu/aes_common/gm11.sv | 44 ++++++++ src/ieu/aes_common/gm13.sv | 44 ++++++++ src/ieu/aes_common/gm14.sv | 47 +++++++++ src/ieu/aes_common/gm2.sv | 36 +++++++ src/ieu/aes_common/gm3.sv | 42 ++++++++ src/ieu/aes_common/gm4.sv | 44 ++++++++ src/ieu/aes_common/gm8.sv | 44 ++++++++ src/ieu/aes_common/gm9.sv | 42 ++++++++ 9 files changed, 343 insertions(+), 161 deletions(-) delete mode 100644 src/ieu/aes_common/galois_func.sv create mode 100644 src/ieu/aes_common/gm11.sv create mode 100644 src/ieu/aes_common/gm13.sv create mode 100644 src/ieu/aes_common/gm14.sv create mode 100644 src/ieu/aes_common/gm2.sv create mode 100644 src/ieu/aes_common/gm3.sv create mode 100644 src/ieu/aes_common/gm4.sv create mode 100644 src/ieu/aes_common/gm8.sv create mode 100644 src/ieu/aes_common/gm9.sv diff --git a/src/ieu/aes_common/galois_func.sv b/src/ieu/aes_common/galois_func.sv deleted file mode 100644 index d18bc91f9..000000000 --- a/src/ieu/aes_common/galois_func.sv +++ /dev/null @@ -1,161 +0,0 @@ -/////////////////////////////////////////// -// galois_func.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm2 (gm2_in, gm2_out); - - input logic [7:0] gm2_in; - output logic [7:0] gm2_out; - - // Set output to Galois Mult 2 - assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); - -endmodule - -module gm3 (gm3_in, gm3_out); - - input logic [7:0] gm3_in; - output logic [7:0] gm3_out; - - // Internal Logic - logic [7:0] gm2_0_out; - - // Sub-Modules for gm2 multiplication - gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out)); - - // Assign Output - assign gm3_out = gm2_0_out ^ gm3_in; - -endmodule - -module gm4 (gm4_in, gm4_out); - - input logic [7:0] gm4_in; - output logic [7:0] gm4_out; - - // Internal Logic - logic [7:0] gm2_0_out; - logic [7:0] gm2_1_out; - - // Sub-Modules for multiple gm2 multiplications - gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out)); - gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out)); - - // Assign output to second gm2 output - assign gm4_out = gm2_1_out; - -endmodule - -module gm8 (gm8_in, gm8_out); - - input logic [7:0] gm8_in; - output logic [7:0] gm8_out; - - // Internal Logic - logic [7:0] gm2_0_out; - logic [7:0] gm4_0_out; - - // Sub-Modules for sub-Galois operations - gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out)); - gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out)); - - // Assign output to gm2 output - assign gm8_out = gm2_0_out; - -endmodule - -module gm9 (gm9_in, gm9_out); - - input logic [7:0] gm9_in; - output logic [7:0] gm9_out; - - // Internal Logic - logic [7:0] gm8_0_out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); - - // Set output to gm8(in) ^ in - assign gm9_out = gm8_0_out ^ gm9_in; - -endmodule - -module gm11 (gm11_in, gm11_out); - - input logic [7:0] gm11_in; - output logic [7:0] gm11_out; - - // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm2_0_out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); - gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); - - // Set output to gm8(in) ^ gm2(in) ^ in - assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; - -endmodule - -module gm13 (gm13_in, gm13_out); - - input logic [7:0] gm13_in; - output logic [7:0] gm13_out; - - // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm4_0_out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); - gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); - - // Set output to gm8(in) ^ gm4(in) ^ in - assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; - -endmodule - -module gm14 (gm14_in, gm14_out); - - input logic [7:0] gm14_in; - output logic [7:0] gm14_out; - - // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm4_0_out; - logic [7:0] gm2_0_out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); - gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); - gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); - - //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) - assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; - -endmodule - diff --git a/src/ieu/aes_common/gm11.sv b/src/ieu/aes_common/gm11.sv new file mode 100644 index 000000000..c4537e269 --- /dev/null +++ b/src/ieu/aes_common/gm11.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// gm11.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm11 (gm11_in, gm11_out); + + input logic [7:0] gm11_in; + output logic [7:0] gm11_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm2_0_out; + + // Sub-Modules for sub-Galois operations + gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); + gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); + + // Set output to gm8(in) ^ gm2(in) ^ in + assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; + +endmodule diff --git a/src/ieu/aes_common/gm13.sv b/src/ieu/aes_common/gm13.sv new file mode 100644 index 000000000..0dfe3c8dd --- /dev/null +++ b/src/ieu/aes_common/gm13.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// gm13.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm13 (gm13_in, gm13_out); + + input logic [7:0] gm13_in; + output logic [7:0] gm13_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm4_0_out; + + // Sub-Modules for sub-Galois operations + gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); + gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); + + // Set output to gm8(in) ^ gm4(in) ^ in + assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; + +endmodule diff --git a/src/ieu/aes_common/gm14.sv b/src/ieu/aes_common/gm14.sv new file mode 100644 index 000000000..48dd90251 --- /dev/null +++ b/src/ieu/aes_common/gm14.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// gm14.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm14 (gm14_in, gm14_out); + + input logic [7:0] gm14_in; + output logic [7:0] gm14_out; + + // Internal Logic + logic [7:0] gm8_0_out; + logic [7:0] gm4_0_out; + logic [7:0] gm2_0_out; + + // Sub-Modules for sub-Galois operations + gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); + gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); + gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); + + //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) + assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; + +endmodule + diff --git a/src/ieu/aes_common/gm2.sv b/src/ieu/aes_common/gm2.sv new file mode 100644 index 000000000..073d252b6 --- /dev/null +++ b/src/ieu/aes_common/gm2.sv @@ -0,0 +1,36 @@ +/////////////////////////////////////////// +// gm2.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm2 (gm2_in, gm2_out); + + input logic [7:0] gm2_in; + output logic [7:0] gm2_out; + + // Set output to Galois Mult 2 + assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); + +endmodule diff --git a/src/ieu/aes_common/gm3.sv b/src/ieu/aes_common/gm3.sv new file mode 100644 index 000000000..602a1778f --- /dev/null +++ b/src/ieu/aes_common/gm3.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// gm3.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm3 (gm3_in, gm3_out); + + input logic [7:0] gm3_in; + output logic [7:0] gm3_out; + + // Internal Logic + logic [7:0] gm2_0_out; + + // Sub-Modules for gm2 multiplication + gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out)); + + // Assign Output + assign gm3_out = gm2_0_out ^ gm3_in; + +endmodule diff --git a/src/ieu/aes_common/gm4.sv b/src/ieu/aes_common/gm4.sv new file mode 100644 index 000000000..2371c3aa9 --- /dev/null +++ b/src/ieu/aes_common/gm4.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// gm4.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm4 (gm4_in, gm4_out); + + input logic [7:0] gm4_in; + output logic [7:0] gm4_out; + + // Internal Logic + logic [7:0] gm2_0_out; + logic [7:0] gm2_1_out; + + // Sub-Modules for multiple gm2 multiplications + gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out)); + gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out)); + + // Assign output to second gm2 output + assign gm4_out = gm2_1_out; + +endmodule diff --git a/src/ieu/aes_common/gm8.sv b/src/ieu/aes_common/gm8.sv new file mode 100644 index 000000000..ad66c7958 --- /dev/null +++ b/src/ieu/aes_common/gm8.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// gm8.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm8 (gm8_in, gm8_out); + + input logic [7:0] gm8_in; + output logic [7:0] gm8_out; + + // Internal Logic + logic [7:0] gm2_0_out; + logic [7:0] gm4_0_out; + + // Sub-Modules for sub-Galois operations + gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out)); + gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out)); + + // Assign output to gm2 output + assign gm8_out = gm2_0_out; + +endmodule diff --git a/src/ieu/aes_common/gm9.sv b/src/ieu/aes_common/gm9.sv new file mode 100644 index 000000000..a26414e2f --- /dev/null +++ b/src/ieu/aes_common/gm9.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// gm9.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm9 (gm9_in, gm9_out); + + input logic [7:0] gm9_in; + output logic [7:0] gm9_out; + + // Internal Logic + logic [7:0] gm8_0_out; + + // Sub-Modules for sub-Galois operations + gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); + + // Set output to gm8(in) ^ in + assign gm9_out = gm8_0_out ^ gm9_in; + +endmodule From 3d65ea7aba3fa915c3f596781e556d3528f0c27d Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Feb 2024 22:57:59 -0600 Subject: [PATCH 08/47] separate aes_shiftword per style file --- src/ieu/aes_common/aes_inv_shiftrow.sv | 34 --------------- src/ieu/aes_common/aes_shiftword.sv | 59 ++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 34 deletions(-) create mode 100644 src/ieu/aes_common/aes_shiftword.sv diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 8cd94b7d3..1330b0685 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -57,37 +57,3 @@ module aes_inv_shiftrow(input logic [127:0] dataIn, assign dataOut = {out_w0, out_w1, out_w2, out_w3}; endmodule - - -/* - Purpose : This next module provides an alternative way to shift the values. - in which it takes the shift number (essentially row number) as - an input and shifts cyclically to the left by that number of bits. - the complexity here is removed from the module and is more complex in - input selection. - */ - -module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] dataIn, - output logic [31:0] dataOut); - - - logic [7:0] b0 = dataIn[7:0]; - logic [7:0] b1 = dataIn[15:8]; - logic [7:0] b2 = dataIn[23:16]; - logic [7:0] b3 = dataIn[31:24]; - - always_comb - begin - case(shiftAmt) - // 00 : Barrel Shift no bytes - 2'b00 : dataOut = {b3, b2, b1, b0}; - // 01 : Barrel Shift one byte - 2'b01 : dataOut = {b0, b3, b2, b1}; - // 10 : Barrel Shift two bytes - 2'b10 : dataOut = {b1, b0, b3, b2}; - // 11 : Barrel Shift three bytes - default : dataOut = {b2, b1, b0, b3}; - endcase - end - -endmodule diff --git a/src/ieu/aes_common/aes_shiftword.sv b/src/ieu/aes_common/aes_shiftword.sv new file mode 100644 index 000000000..9df834b65 --- /dev/null +++ b/src/ieu/aes_common/aes_shiftword.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// aes_shiftword.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: AES Shiftrow shifting values +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +/* + Purpose : This next module provides an alternative way to shift the values. + in which it takes the shift number (essentially row number) as + an input and shifts cyclically to the left by that number of bits. + the complexity here is removed from the module and is more complex in + input selection. + */ + +module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] dataIn, + output logic [31:0] dataOut); + + + logic [7:0] b0 = dataIn[7:0]; + logic [7:0] b1 = dataIn[15:8]; + logic [7:0] b2 = dataIn[23:16]; + logic [7:0] b3 = dataIn[31:24]; + + always_comb + begin + case(shiftAmt) + // 00 : Barrel Shift no bytes + 2'b00 : dataOut = {b3, b2, b1, b0}; + // 01 : Barrel Shift one byte + 2'b01 : dataOut = {b0, b3, b2, b1}; + // 10 : Barrel Shift two bytes + 2'b10 : dataOut = {b1, b0, b3, b2}; + // 11 : Barrel Shift three bytes + default : dataOut = {b2, b1, b0, b3}; + endcase + end + +endmodule From ac9068d22c4bbb8342457ed0088c1299b4c07ef9 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 21 Feb 2024 17:05:58 -0600 Subject: [PATCH 09/47] update aes_common with style on separate sv --- src/ieu/aes_common/aes_inv_mixcols.sv | 51 +++++++++++++++++ src/ieu/aes_common/aes_inv_mixcolumns.sv | 25 -------- src/ieu/aes_common/aes_mixcolumns.sv | 47 ---------------- src/ieu/aes_common/aes_shiftrow.sv | 33 ----------- src/ieu/aes_common/mixword.sv | 72 ++++++++++++++++++++++++ 5 files changed, 123 insertions(+), 105 deletions(-) create mode 100644 src/ieu/aes_common/aes_inv_mixcols.sv create mode 100644 src/ieu/aes_common/mixword.sv diff --git a/src/ieu/aes_common/aes_inv_mixcols.sv b/src/ieu/aes_common/aes_inv_mixcols.sv new file mode 100644 index 000000000..c40ce5a8f --- /dev/null +++ b/src/ieu/aes_common/aes_inv_mixcols.sv @@ -0,0 +1,51 @@ +/////////////////////////////////////////// +// aes_inv_mixcols.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: AES Inverted Mix Column Function for use with AES +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col); + + // Declare Internal logic + logic [31:0] w0, w1, w2, w3; + logic [31:0] ws0, ws1, ws2, ws3; + + // Break up input data into word components + assign w0 = data[127:96]; + assign w1 = data[95:64]; + assign w2 = data[63:32]; + assign w3 = data[31:0]; + + // Declare mixword components + inv_mixword mw_0(.word(w0), .mixed_word(ws0)); + inv_mixword mw_1(.word(w1), .mixed_word(ws1)); + inv_mixword mw_2(.word(w2), .mixed_word(ws2)); + inv_mixword mw_3(.word(w3), .mixed_word(ws3)); + + // Assign output to mixed word + assign mixed_col = {ws0, ws1, ws2, ws3}; + +endmodule // inv_mixcols + + diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index 0270bd084..6d4b619c8 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -74,28 +74,3 @@ module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word); assign mixed_word = {mb0, mb1, mb2, mb3}; endmodule // inv_mixword - -module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col); - - // Declare Internal logic - logic [31:0] w0, w1, w2, w3; - logic [31:0] ws0, ws1, ws2, ws3; - - // Break up input data into word components - assign w0 = data[127:96]; - assign w1 = data[95:64]; - assign w2 = data[63:32]; - assign w3 = data[31:0]; - - // Declare mixword components - inv_mixword mw_0(.word(w0), .mixed_word(ws0)); - inv_mixword mw_1(.word(w1), .mixed_word(ws1)); - inv_mixword mw_2(.word(w2), .mixed_word(ws2)); - inv_mixword mw_3(.word(w3), .mixed_word(ws3)); - - // Assign output to mixed word - assign mixed_col = {ws0, ws1, ws2, ws3}; - -endmodule // inv_mixcols - - diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index 701fa9420..e16c28abb 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -64,50 +64,3 @@ module aes_mixcolumns(data, mixedcols); assign mixedcols = {ws0, ws1, ws2, ws3}; endmodule // mixcolumns - -// This applies the Galois field operations to an individual 32 bit word. -module mixword (word, mixed_word); - - // Declare Inputs/Outputs - input logic [31:0] word; - output logic [31:0] mixed_word; - - // Declare Internal Signals - logic [7:0] b0, b1, b2, b3; - logic [7:0] mb0, mb1, mb2, mb3; - logic [7:0] gm2_0_out; - logic [7:0] gm3_0_out; - logic [7:0] gm2_1_out; - logic [7:0] gm3_1_out; - logic [7:0] gm2_2_out; - logic [7:0] gm3_2_out; - logic [7:0] gm2_3_out; - logic [7:0] gm3_3_out; - - // Break word into bytes - assign b0 = word[31:24]; - assign b1 = word[23:16]; - assign b2 = word[15:8]; - assign b3 = word[7:0]; - - // mb0 Galois components - gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out)); - gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out)); - // mb1 Galois components - gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out)); - gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out)); - // mb2 Galois components - gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out)); - gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out)); - // mb3 Galois components - gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out)); - gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out)); - - // Combine Componenets into mixed word - assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; - assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3; - assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3; - assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1; - assign mixed_word = {mb0, mb1, mb2, mb3}; - -endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index ac82d38f8..3c5ed4484 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -60,36 +60,3 @@ module aes_shiftrow(input logic [127:0] dataIn, assign dataOut = {out_w0, out_w1, out_w2, out_w3}; endmodule - -/* - * Purpose : This next module provides an alternative way to shift the values. - in which it takes the shift number (essentially row number) as - an input and shifts cyclically to the left by that number of bits. - the complexity here is removed from the module and is more complex in - input selection (eww more thinking bad return to monkeh) - */ - -module aes_shiftwordbrutherr(input logic[1:0] shiftAmt, - input logic [31:0] dataIn, - output logic [31:0] dataOut); - - logic [7:0] b0 = dataIn[7:0]; - logic [7:0] b1 = dataIn[15:8]; - logic [7:0] b2 = dataIn[23:16]; - logic [7:0] b3 = dataIn[31:24]; - - always_comb - begin - case(shiftAmt) - // 00 : Barrel Shift no bytes - 2'b00 : dataOut = {b3, b2, b1, b0}; - // 01 : Barrel Shift one byte - 2'b01 : dataOut = {b2, b1, b0, b3}; - // 10 : Barrel Shift two bytes - 2'b10 : dataOut = {b1, b0, b2, b3}; - // 11 : Barrel Shift three bytes - default : dataOut = {b0, b1, b2, b3}; - endcase - end - -endmodule diff --git a/src/ieu/aes_common/mixword.sv b/src/ieu/aes_common/mixword.sv new file mode 100644 index 000000000..462658c53 --- /dev/null +++ b/src/ieu/aes_common/mixword.sv @@ -0,0 +1,72 @@ +/////////////////////////////////////////// +// mixword.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operation to an individual 32-bit word +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module mixword (word, mixed_word); + + // Declare Inputs/Outputs + input logic [31:0] word; + output logic [31:0] mixed_word; + + // Declare Internal Signals + logic [7:0] b0, b1, b2, b3; + logic [7:0] mb0, mb1, mb2, mb3; + logic [7:0] gm2_0_out; + logic [7:0] gm3_0_out; + logic [7:0] gm2_1_out; + logic [7:0] gm3_1_out; + logic [7:0] gm2_2_out; + logic [7:0] gm3_2_out; + logic [7:0] gm2_3_out; + logic [7:0] gm3_3_out; + + // Break word into bytes + assign b0 = word[31:24]; + assign b1 = word[23:16]; + assign b2 = word[15:8]; + assign b3 = word[7:0]; + + // mb0 Galois components + gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out)); + gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out)); + // mb1 Galois components + gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out)); + gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out)); + // mb2 Galois components + gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out)); + gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out)); + // mb3 Galois components + gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out)); + gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out)); + + // Combine Componenets into mixed word + assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; + assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3; + assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3; + assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1; + assign mixed_word = {mb0, mb1, mb2, mb3}; + +endmodule From 7097b17785f5cb2e1ddb7b2da9fff374846d4953 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 21 Feb 2024 17:11:34 -0600 Subject: [PATCH 10/47] update aes_instructions --- src/ieu/aes_instructions/aes32dsi.sv | 15 ++++-- src/ieu/aes_instructions/aes32dsmi.sv | 18 ++++--- src/ieu/aes_instructions/aes64ds.sv | 2 + src/ieu/aes_instructions/aes64dsm.sv | 12 ++--- src/ieu/aes_instructions/aes64es.sv | 3 +- src/ieu/aes_instructions/aes64esm.sv | 8 +-- src/ieu/aes_instructions/aes64im.sv | 4 +- src/ieu/aes_instructions/rcon_lut_128.sv | 49 ++++++++++++++++++ src/ieu/aes_instructions/rrot8.sv | 64 ++++++++++++++++++++++++ 9 files changed, 151 insertions(+), 24 deletions(-) create mode 100644 src/ieu/aes_instructions/rcon_lut_128.sv create mode 100644 src/ieu/aes_instructions/rrot8.sv diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 914ec8994..7ecd5310e 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -39,16 +39,21 @@ module aes32dsi(input logic [1:0] bs, logic [31:0] so_rotate; // shamt = bs * 8 - assign shamt = {bs, 3'b0}; + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte assign sbox_in_32 = (rs2 >> shamt); - assign sbox_in = sbox_in_32[7:0]; + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box - assign so = {24'h000000,sbox_out}; + assign so = {24'h000000,sbox_out}; + // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign data_out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index e3b750b79..1cf033ffc 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -40,18 +40,24 @@ module aes32dsmi(input logic [1:0] bs, logic [31:0] mixed_rotate; // shamt = bs * 8 - assign shamt = {bs, 3'b0}; + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt and take the lower byte assign sbox_in_32 = (rs2 >> shamt); - assign sbox_in = sbox_in_32[7:0]; + assign sbox_in = sbox_in_32[7:0]; + // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + // Pad output of inverse substitution box - assign so = {24'h000000,sbox_out}; + assign so = {24'h000000,sbox_out}; + // Run so through the mixword AES function - inv_mixword mix(.word(so),.mixed_word(mixed)); + inv_mixword mix(.word(so),.mixed_word(mixed)); + // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign data_out = rs1 ^ mixed_rotate; diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index 4ba657ea7..2481413b6 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -36,9 +36,11 @@ module aes64ds(input logic [63:0] rs1, // Apply inverse shiftrows to rs2 and rs1 aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Concatenate the two substitution outputs to get result assign data_out = {sbox_out_1, sbox_out_0}; diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 4ed5eef13..247041341 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,17 +37,17 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] mixcol_out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply full word inverse substitution to lower 2 words of shiftrow out aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); - aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + // Apply inverse mixword to sbox outputs inv_mixword inv_mw_0(.word(sbox_out_0),.mixed_word(mixcol_out_0)); - inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1)); + inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1)); + // Concatenate mixed words for output assign data_out = {mixcol_out_1,mixcol_out_0}; endmodule - - - diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 4f665f030..e2e7804cd 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,7 +33,8 @@ module aes64es(input logic [63:0] rs1, logic [127:0] shiftRow_out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(data_out[31:0])); aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(data_out[63:32])); diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 51c5474ac..21df77378 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,14 +34,14 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] sbox_out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out[31:0])); - aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32])); + // Apply mix columns operations mixword mw0(.word(sbox_out[31:0]),.mixed_word(data_out[31:0])); mixword mw1(.word(sbox_out[63:32]),.mixed_word(data_out[63:32])); endmodule - - diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index 9a898ef89..80dd4f584 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -28,7 +28,7 @@ module aes64im(input logic [63:0] rs1, output logic [63:0] data_out); - inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0])); - inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32])); + inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0])); + inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/rcon_lut_128.sv b/src/ieu/aes_instructions/rcon_lut_128.sv new file mode 100644 index 000000000..af71e2ef8 --- /dev/null +++ b/src/ieu/aes_instructions/rcon_lut_128.sv @@ -0,0 +1,49 @@ +/////////////////////////////////////////// +// rcon_lut_128.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rcon_lut_128(input logic [3:0] RD, + output logic [7:0] rcon_out); + + always_comb + begin + case(RD) + 4'h0 : rcon_out = 8'h01; + 4'h1 : rcon_out = 8'h02; + 4'h2 : rcon_out = 8'h04; + 4'h3 : rcon_out = 8'h08; + 4'h4 : rcon_out = 8'h10; + 4'h5 : rcon_out = 8'h20; + 4'h6 : rcon_out = 8'h40; + 4'h7 : rcon_out = 8'h80; + 4'h8 : rcon_out = 8'h1b; + 4'h9 : rcon_out = 8'h36; + 4'hA : rcon_out = 8'h00; + default : rcon_out = 8'h00; + endcase + end + +endmodule diff --git a/src/ieu/aes_instructions/rrot8.sv b/src/ieu/aes_instructions/rrot8.sv new file mode 100644 index 000000000..64d451b10 --- /dev/null +++ b/src/ieu/aes_instructions/rrot8.sv @@ -0,0 +1,64 @@ +/////////////////////////////////////////// +// rrot8.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rrot8(input logic[31:0] x, + output logic [31:0] result); + + assign result[0] = x[8]; + assign result[1] = x[9]; + assign result[2] = x[10]; + assign result[3] = x[11]; + assign result[4] = x[12]; + assign result[5] = x[13]; + assign result[6] = x[14]; + assign result[7] = x[15]; + assign result[8] = x[16]; + assign result[9] = x[17]; + assign result[10] = x[18]; + assign result[11] = x[19]; + assign result[12] = x[20]; + assign result[13] = x[21]; + assign result[14] = x[22]; + assign result[15] = x[23]; + assign result[16] = x[24]; + assign result[17] = x[25]; + assign result[18] = x[26]; + assign result[19] = x[27]; + assign result[20] = x[28]; + assign result[21] = x[29]; + assign result[22] = x[30]; + assign result[23] = x[31]; + assign result[24] = x[0]; + assign result[25] = x[1]; + assign result[26] = x[2]; + assign result[27] = x[3]; + assign result[28] = x[4]; + assign result[29] = x[5]; + assign result[30] = x[6]; + assign result[31] = x[7]; + +endmodule From 7cb170c19baaae96498a7de1723e834a92357fd2 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 21 Feb 2024 17:12:50 -0600 Subject: [PATCH 11/47] update on aes_instructions --- src/ieu/aes_instructions/aes32esi.sv | 18 ++++++++++++------ src/ieu/aes_instructions/aes32esmi.sv | 19 +++++++++++++------ 2 files changed, 25 insertions(+), 12 deletions(-) diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index 2281c6f4e..5ef354291 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -39,17 +39,23 @@ module aes32esi(input logic [1:0] bs, logic [31:0] so_rotate; // Shift bs by 3 to get shamt - assign shamt = {bs, 3'b0}; + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input - assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box - assign sbox_in = sbox_in_32[7:0]; + assign sbox_in = sbox_in_32[7:0]; + // Substitute - aes_sbox subbox(.in(sbox_in),.out(sbox_out)); + aes_sbox subbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output - assign so = {24'h000000,sbox_out}; + assign so = {24'h000000,sbox_out}; + // Rotate so left by shamt - rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); assign data_out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 382c1da5d..840a7f756 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -40,19 +40,26 @@ module aes32esmi(input logic [1:0] bs, logic [31:0] mixed_rotate; // Shift bs by 3 to get shamt - assign shamt = {bs, 3'b0}; + assign shamt = {bs, 3'b0}; + // Shift rs2 right by shamt to get sbox input - assign sbox_in_32 = (rs2 >> shamt); + assign sbox_in_32 = (rs2 >> shamt); + // Take the bottom byte as an input to the substitution box - assign sbox_in = sbox_in_32[7:0]; + assign sbox_in = sbox_in_32[7:0]; + // Substitute - aes_sbox sbox(.in(sbox_in),.out(sbox_out)); + aes_sbox sbox(.in(sbox_in),.out(sbox_out)); + // Pad sbox output - assign so = {24'h000000,sbox_out}; + assign so = {24'h000000,sbox_out}; + // Mix Word using aes_mixword component mixword mwd(.word(so),.mixed_word(mixed)); + // Rotate so left by shamt - rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); assign data_out = rs1 ^ mixed_rotate; From 550f50debb8780c5b4686f4dbfe658f3c01abfd0 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Feb 2024 11:55:00 -0600 Subject: [PATCH 12/47] Modify ALU to handle Zkne/K extension --- src/ieu/alu.sv | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 51cf00b97..335eaccac 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -2,8 +2,9 @@ // alu.sv // // Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 9 January 2021 -// Modified: 3 March 2023 +// Modified: 3 March 2023, 22 February 2024 // // Purpose: RISC-V Arithmetic/Logic Unit // @@ -33,9 +34,11 @@ module alu import cvw::*; #(parameter cvw_t P) ( input logic W64, // W64-type instruction input logic SubArith, // Subtraction or arithmetic shift input logic [2:0] ALUSelect, // ALU mux select signal - input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // For BMU decoding + input logic [6:0] Funct7, // For ZKNE and ZKND computation + input logic [4:0] Rs2E, // For ZKNE and ZKND computation input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic BMUActive, // Bit manipulation instruction being executed input logic [1:0] CZero, // {czero.nez, czero.eqz} instructions active @@ -89,10 +92,11 @@ module alu import cvw::*; #(parameter cvw_t P) ( else assign PreALUResult = FullResult; // Bit manipulation muxing - if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu + if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | + P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu bitmanipalu #(P) balu( .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive, - .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, + .Funct3, .Funct7, .Rs2E, .LT, .LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin assign ALUResult = PreALUResult; From 171da97fe324d7369daabfc67472704e2b00290d Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Feb 2024 12:12:56 -0600 Subject: [PATCH 13/47] add config for K extensions (7 so far) --- config/rv32e/config.vh | 9 +++++++++ config/rv32gc/config.vh | 9 +++++++++ config/rv32i/config.vh | 9 +++++++++ config/rv32imc/config.vh | 9 +++++++++ config/rv64gc/config.vh | 9 +++++++++ config/rv64i/config.vh | 9 +++++++++ 6 files changed, 54 insertions(+) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 9f0056fad..5e1f883d4 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -179,6 +179,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 843f55530..29130e766 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 81b25bc2b..490937558 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 931725cc4..357eba840 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -178,6 +178,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 7f038d87e..a483ccbc4 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 4dd540a9f..a289003cc 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; From c8468e99c0f25fefb03bad61e7c342051b27c519 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Feb 2024 12:27:09 -0600 Subject: [PATCH 14/47] slight tweak of names --- src/ieu/aes_instructions/aes32dsi.sv | 9 ++++----- src/ieu/aes_instructions/aes32dsmi.sv | 9 ++++----- src/ieu/aes_instructions/aes32esi.sv | 9 ++++----- src/ieu/aes_instructions/aes32esmi.sv | 11 +++++------ src/ieu/aes_instructions/aes64ds.sv | 9 ++++----- src/ieu/aes_instructions/aes64dsm.sv | 13 ++++++------- src/ieu/aes_instructions/aes64es.sv | 7 +++---- src/ieu/aes_instructions/aes64esm.sv | 11 +++++------ src/ieu/aes_instructions/aes64im.sv | 5 ++--- src/ieu/aes_instructions/aes64ks2.sv | 3 +-- 10 files changed, 38 insertions(+), 48 deletions(-) diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 7ecd5310e..52dc2e8b5 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -46,15 +46,14 @@ module aes32dsi(input logic [1:0] bs, assign sbox_in = sbox_in_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out)); // Pad output of inverse substitution box - assign so = {24'h000000,sbox_out}; + assign so = {24'h0, sbox_out}; // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" - assign data_out = rs1 ^ so_rotate; - + assign data_out = rs1 ^ so_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 1cf033ffc..1fa6560bb 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -47,18 +47,17 @@ module aes32dsmi(input logic [1:0] bs, assign sbox_in = sbox_in_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in),.out(sbox_out)); + aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out)); // Pad output of inverse substitution box - assign so = {24'h000000,sbox_out}; + assign so = {24'h0, sbox_out}; // Run so through the mixword AES function - inv_mixword mix(.word(so),.mixed_word(mixed)); + inv_mixword mix(.word(so), .mixed_word(mixed)); // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign data_out = rs1 ^ mixed_rotate; - endmodule diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index 5ef354291..4d9ff0edd 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -48,15 +48,14 @@ module aes32esi(input logic [1:0] bs, assign sbox_in = sbox_in_32[7:0]; // Substitute - aes_sbox subbox(.in(sbox_in),.out(sbox_out)); + aes_sbox subbox(.in(sbox_in), .out(sbox_out)); // Pad sbox output - assign so = {24'h000000,sbox_out}; + assign so = {24'h0, sbox_out}; // Rotate so left by shamt - rotate_left rol32(.input_data(so),.shamt(shamt),.rot_data(so_rotate)); + rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); - assign data_out = rs1 ^ so_rotate; - + assign data_out = rs1 ^ so_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 840a7f756..a822edc3d 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -49,18 +49,17 @@ module aes32esmi(input logic [1:0] bs, assign sbox_in = sbox_in_32[7:0]; // Substitute - aes_sbox sbox(.in(sbox_in),.out(sbox_out)); + aes_sbox sbox(.in(sbox_in), .out(sbox_out)); // Pad sbox output - assign so = {24'h000000,sbox_out}; + assign so = {24'h0, sbox_out}; // Mix Word using aes_mixword component - mixword mwd(.word(so),.mixed_word(mixed)); + mixword mwd(.word(so), .mixed_word(mixed)); // Rotate so left by shamt - rotate_left rol32(.input_data(mixed),.shamt(shamt),.rot_data(mixed_rotate)); + rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); - assign data_out = rs1 ^ mixed_rotate; - + assign data_out = rs1 ^ mixed_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index 2481413b6..114d6a900 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -35,13 +35,12 @@ module aes64ds(input logic [63:0] rs1, logic [31:0] sbox_out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); - aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1)); // Concatenate the two substitution outputs to get result - assign data_out = {sbox_out_1, sbox_out_0}; - + assign data_out = {sbox_out_1, sbox_out_0}; endmodule diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 247041341..0b417e896 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,17 +37,16 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] mixcol_out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out_0)); - aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out_1)); + aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0)); + aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1)); // Apply inverse mixword to sbox outputs - inv_mixword inv_mw_0(.word(sbox_out_0),.mixed_word(mixcol_out_0)); - inv_mixword inv_mw_1(.word(sbox_out_1),.mixed_word(mixcol_out_1)); + inv_mixword inv_mw_0(.word(sbox_out_0), .mixed_word(mixcol_out_0)); + inv_mixword inv_mw_1(.word(sbox_out_1), .mixed_word(mixcol_out_1)); // Concatenate mixed words for output - assign data_out = {mixcol_out_1,mixcol_out_0}; - + assign data_out = {mixcol_out_1, mixcol_out_0}; endmodule diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index e2e7804cd..a31177823 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,10 +33,9 @@ module aes64es(input logic [63:0] rs1, logic [127:0] shiftRow_out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(data_out[31:0])); - aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(data_out[63:32])); - + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(data_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(data_out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 21df77378..6584525a5 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,14 +34,13 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] sbox_out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}),.dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(shiftRow_out[31:0]),.out(sbox_out[31:0])); - aes_sbox_word sbox_1(.in(shiftRow_out[63:32]),.out(sbox_out[63:32])); + aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out[31:0])); + aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out[63:32])); // Apply mix columns operations - mixword mw0(.word(sbox_out[31:0]),.mixed_word(data_out[31:0])); - mixword mw1(.word(sbox_out[63:32]),.mixed_word(data_out[63:32])); - + mixword mw0(.word(sbox_out[31:0]), .mixed_word(data_out[31:0])); + mixword mw1(.word(sbox_out[63:32]), .mixed_word(data_out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index 80dd4f584..b82ed874b 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -28,7 +28,6 @@ module aes64im(input logic [63:0] rs1, output logic [63:0] data_out); - inv_mixword inv_mw_0(.word(rs1[31:0]),.mixed_word(data_out[31:0])); - inv_mixword inv_mw_1(.word(rs1[63:32]),.mixed_word(data_out[63:32])); - + inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(data_out[31:0])); + inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(data_out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64ks2.sv b/src/ieu/aes_instructions/aes64ks2.sv index c2381bcd5..ce76e17a6 100644 --- a/src/ieu/aes_instructions/aes64ks2.sv +++ b/src/ieu/aes_instructions/aes64ks2.sv @@ -35,6 +35,5 @@ module aes64ks2(input logic [63:0] rs2, assign w0 = rs1[63:32] ^ rs2[31:0]; assign w1 = rs1[63:32] ^ rs2[31:0] ^ rs2[63:32]; - assign rd = {w1, w0}; - + assign rd = {w1, w0}; endmodule From cdd2aa63792c43930f76dec5638cac17a9d93622 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Feb 2024 12:27:40 -0600 Subject: [PATCH 15/47] tweak of names --- src/ieu/aes_instructions/rcon_lut_128.sv | 3 +-- src/ieu/aes_instructions/rrot8.sv | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/ieu/aes_instructions/rcon_lut_128.sv b/src/ieu/aes_instructions/rcon_lut_128.sv index af71e2ef8..89368408d 100644 --- a/src/ieu/aes_instructions/rcon_lut_128.sv +++ b/src/ieu/aes_instructions/rcon_lut_128.sv @@ -44,6 +44,5 @@ module rcon_lut_128(input logic [3:0] RD, 4'hA : rcon_out = 8'h00; default : rcon_out = 8'h00; endcase - end - + end endmodule diff --git a/src/ieu/aes_instructions/rrot8.sv b/src/ieu/aes_instructions/rrot8.sv index 64d451b10..8f36f4317 100644 --- a/src/ieu/aes_instructions/rrot8.sv +++ b/src/ieu/aes_instructions/rrot8.sv @@ -60,5 +60,4 @@ module rrot8(input logic[31:0] x, assign result[29] = x[5]; assign result[30] = x[6]; assign result[31] = x[7]; - endmodule From e06bafe97279ec5965c3e739623ac5651fd1b747 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:21:39 -0600 Subject: [PATCH 16/47] Add alu + controller --- src/ieu/aes_common/aes_inv_mixcols.sv | 16 +++++----- src/ieu/aes_common/aes_inv_mixcolumns.sv | 34 ++++++++++---------- src/ieu/aes_common/aes_inv_sbox.sv | 4 +-- src/ieu/aes_common/aes_inv_sbox_128.sv | 12 +++---- src/ieu/aes_common/aes_inv_sbox_word.sv | 12 +++---- src/ieu/aes_common/aes_inv_shiftrow.sv | 40 ++++++++++++------------ src/ieu/aes_common/aes_mixcolumns.sv | 14 ++++----- src/ieu/aes_common/aes_shiftrow.sv | 40 ++++++++++++------------ src/ieu/aes_common/aes_shiftword.sv | 20 ++++++------ src/ieu/aes_common/gm11.sv | 16 +++++----- src/ieu/aes_common/gm13.sv | 16 +++++----- src/ieu/aes_common/gm14.sv | 20 ++++++------ src/ieu/aes_common/gm2.sv | 8 ++--- src/ieu/aes_common/gm3.sv | 12 +++---- src/ieu/aes_common/gm4.sv | 16 +++++----- src/ieu/aes_common/gm8.sv | 16 +++++----- src/ieu/aes_common/gm9.sv | 12 +++---- src/ieu/aes_common/mixword.sv | 40 ++++++++++++------------ src/ieu/aes_common/rotateleft.sv | 6 ++-- src/ieu/aes_instructions/aes32dsi.sv | 18 +++++------ src/ieu/aes_instructions/aes32dsmi.sv | 18 +++++------ src/ieu/aes_instructions/aes32esi.sv | 18 +++++------ src/ieu/aes_instructions/aes32esmi.sv | 18 +++++------ src/ieu/aes_instructions/aes64ds.sv | 16 +++++----- src/ieu/aes_instructions/aes64dsm.sv | 24 +++++++------- src/ieu/aes_instructions/aes64es.sv | 10 +++--- src/ieu/aes_instructions/aes64esm.sv | 16 +++++----- src/ieu/aes_instructions/aes64im.sv | 6 ++-- src/ieu/aes_instructions/aes64ks1i.sv | 8 ++--- src/ieu/alu.sv | 8 ++--- src/ieu/controller.sv | 25 ++++++++------- 31 files changed, 269 insertions(+), 270 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_mixcols.sv b/src/ieu/aes_common/aes_inv_mixcols.sv index c40ce5a8f..ad581748e 100644 --- a/src/ieu/aes_common/aes_inv_mixcols.sv +++ b/src/ieu/aes_common/aes_inv_mixcols.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_mixcols.sv +// aes_Inv_mixcols.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,17 +25,17 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_col); +module aes_Inv_mixcols (input logic [127:0] Data, output logic [127:0] Mixed_Col); // Declare Internal logic logic [31:0] w0, w1, w2, w3; logic [31:0] ws0, ws1, ws2, ws3; - // Break up input data into word components - assign w0 = data[127:96]; - assign w1 = data[95:64]; - assign w2 = data[63:32]; - assign w3 = data[31:0]; + // Break up input Data into word components + assign w0 = Data[127:96]; + assign w1 = Data[95:64]; + assign w2 = Data[63:32]; + assign w3 = Data[31:0]; // Declare mixword components inv_mixword mw_0(.word(w0), .mixed_word(ws0)); @@ -44,7 +44,7 @@ module aes_inv_mixcols (input logic [127:0] data, output logic [127:0] mixed_co inv_mixword mw_3(.word(w3), .mixed_word(ws3)); // Assign output to mixed word - assign mixed_col = {ws0, ws1, ws2, ws3}; + assign Mixed_Col = {ws0, ws1, ws2, ws3}; endmodule // inv_mixcols diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index 6d4b619c8..e9e910f9c 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_mixcolumns.sv +// aes_Inv_mixcolumns.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -43,28 +43,28 @@ module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word); assign b3 = word[7:0]; // mb0 Galois components - gm9 gm9_0(.gm9_in(b1), .gm9_out(gm9_mb0)); - gm11 gm11_0(.gm11_in(b3), .gm11_out(gm11_mb0)); - gm13 gm13_0(.gm13_in(b2), .gm13_out(gm13_mb0)); - gm14 gm14_0(.gm14_in(b0), .gm14_out(gm14_mb0)); + gm9 gm9_0(.gm9_In(b1), .gm9_Out(gm9_mb0)); + gm11 gm11_0(.gm11_In(b3), .gm11_Out(gm11_mb0)); + gm13 gm13_0(.gm13_In(b2), .gm13_Out(gm13_mb0)); + gm14 gm14_0(.gm14_In(b0), .gm14_Out(gm14_mb0)); // mb1 Galois components - gm9 gm9_1(.gm9_in(b2), .gm9_out(gm9_mb1)); - gm11 gm11_1(.gm11_in(b0), .gm11_out(gm11_mb1)); - gm13 gm13_1(.gm13_in(b3), .gm13_out(gm13_mb1)); - gm14 gm14_1(.gm14_in(b1), .gm14_out(gm14_mb1)); + gm9 gm9_1(.gm9_In(b2), .gm9_Out(gm9_mb1)); + gm11 gm11_1(.gm11_In(b0), .gm11_Out(gm11_mb1)); + gm13 gm13_1(.gm13_In(b3), .gm13_Out(gm13_mb1)); + gm14 gm14_1(.gm14_In(b1), .gm14_Out(gm14_mb1)); // mb2 Galois components - gm9 gm9_2(.gm9_in(b3), .gm9_out(gm9_mb2)); - gm11 gm11_2(.gm11_in(b1), .gm11_out(gm11_mb2)); - gm13 gm13_2(.gm13_in(b0), .gm13_out(gm13_mb2)); - gm14 gm14_2(.gm14_in(b2), .gm14_out(gm14_mb2)); + gm9 gm9_2(.gm9_In(b3), .gm9_Out(gm9_mb2)); + gm11 gm11_2(.gm11_In(b1), .gm11_Out(gm11_mb2)); + gm13 gm13_2(.gm13_In(b0), .gm13_Out(gm13_mb2)); + gm14 gm14_2(.gm14_In(b2), .gm14_Out(gm14_mb2)); // mb3 Galois components - gm9 gm9_3(.gm9_in(b0), .gm9_out(gm9_mb3)); - gm11 gm11_3(.gm11_in(b2), .gm11_out(gm11_mb3)); - gm13 gm13_3(.gm13_in(b1), .gm13_out(gm13_mb3)); - gm14 gm14_3(.gm14_in(b3), .gm14_out(gm14_mb3)); + gm9 gm9_3(.gm9_In(b0), .gm9_Out(gm9_mb3)); + gm11 gm11_3(.gm11_In(b2), .gm11_Out(gm11_mb3)); + gm13 gm13_3(.gm13_In(b1), .gm13_Out(gm13_mb3)); + gm14 gm14_3(.gm14_In(b3), .gm14_Out(gm14_mb3)); // XOR Galois components and assign output assign mb0 = gm9_mb0 ^ gm11_mb0 ^ gm13_mb0 ^ gm14_mb0; diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index a364f75db..3608dac92 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox.sv +// aes_Inv_sbox.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox(input logic [7:0] in, +module aes_Inv_sbox(input logic [7:0] in, output logic [7:0] out); always_comb diff --git a/src/ieu/aes_common/aes_inv_sbox_128.sv b/src/ieu/aes_common/aes_inv_sbox_128.sv index 5c1bc10be..577f37ef7 100644 --- a/src/ieu/aes_common/aes_inv_sbox_128.sv +++ b/src/ieu/aes_common/aes_inv_sbox_128.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox_128.sv +// aes_Inv_sbox_128.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox_128(input logic [127:0] in, +module aes_Inv_sbox_128(input logic [127:0] in, output logic [127:0] out); // Declare the SBOX for (least significant) word 0 of the input - aes_inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0])); + aes_Inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0])); // Declare the SBOX for word 1 of the input - aes_inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32])); + aes_Inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32])); // Declare the SBOX for word 2 of the input - aes_inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64])); + aes_Inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64])); // Declare the SBOX for word 3 of the input - aes_inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96])); + aes_Inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96])); endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index d2b18d7db..42a91c7b6 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox_word.sv +// aes_Inv_sbox_word.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox_word(input logic [31:0] in, +module aes_Inv_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_Inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_Inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_Inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_Inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 1330b0685..5b417f78f 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_shiftrow.sv +// aes_Inv_shiftrow.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,35 +25,35 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_shiftrow(input logic [127:0] dataIn, - output logic [127:0] dataOut); +module aes_Inv_shiftrow(input logic [127:0] DataIn, + output logic [127:0] DataOut); // Separate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = dataIn[7:0]; - logic [7:0] w0_b1 = dataIn[15:8]; - logic [7:0] w0_b2 = dataIn[23:16]; - logic [7:0] w0_b3 = dataIn[31:24]; + logic [7:0] w0_b0 = DataIn[7:0]; + logic [7:0] w0_b1 = DataIn[15:8]; + logic [7:0] w0_b2 = DataIn[23:16]; + logic [7:0] w0_b3 = DataIn[31:24]; // Separate the second word into bytes - logic [7:0] w1_b0 = dataIn[39:32]; - logic [7:0] w1_b1 = dataIn[47:40]; - logic [7:0] w1_b2 = dataIn[55:48]; - logic [7:0] w1_b3 = dataIn[63:56]; + logic [7:0] w1_b0 = DataIn[39:32]; + logic [7:0] w1_b1 = DataIn[47:40]; + logic [7:0] w1_b2 = DataIn[55:48]; + logic [7:0] w1_b3 = DataIn[63:56]; // Separate the third word into bytes - logic [7:0] w2_b0 = dataIn[71:64]; - logic [7:0] w2_b1 = dataIn[79:72]; - logic [7:0] w2_b2 = dataIn[87:80]; - logic [7:0] w2_b3 = dataIn[95:88]; + logic [7:0] w2_b0 = DataIn[71:64]; + logic [7:0] w2_b1 = DataIn[79:72]; + logic [7:0] w2_b2 = DataIn[87:80]; + logic [7:0] w2_b3 = DataIn[95:88]; // Separate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = dataIn[103:96]; - logic [7:0] w3_b1 = dataIn[111:104]; - logic [7:0] w3_b2 = dataIn[119:112]; - logic [7:0] w3_b3 = dataIn[127:120]; + logic [7:0] w3_b0 = DataIn[103:96]; + logic [7:0] w3_b1 = DataIn[111:104]; + logic [7:0] w3_b2 = DataIn[119:112]; + logic [7:0] w3_b3 = DataIn[127:120]; // The output words are composed of sets of the input bytes. logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; - assign dataOut = {out_w0, out_w1, out_w2, out_w3}; + assign DataOut = {out_w0, out_w1, out_w2, out_w3}; endmodule diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index e16c28abb..07ba6cd1b 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -38,21 +38,21 @@ * Reference: secworks repo */ -module aes_mixcolumns(data, mixedcols); +module aes_mixcolumns(Data, mixedcols); // Declare Inputs/Outputs - input logic [127:0] data; + input logic [127:0] Data; output logic [127:0] mixedcols; // Declare internal Logic logic [31:0] w0, w1, w2, w3; logic [31:0] ws0, ws1, ws2, ws3; - // Break up data into individual words - assign w0 = data[127:96]; - assign w1 = data[95:64]; - assign w2 = data[63:32]; - assign w3 = data[31:0]; + // Break up Data into individual words + assign w0 = Data[127:96]; + assign w1 = Data[95:64]; + assign w2 = Data[63:32]; + assign w3 = Data[31:0]; // Instantiate The mix words components for the words mixword mw0(.word(w0), .mixed_word(ws0)); diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 3c5ed4484..4206b7a01 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes_shiftrow for taking in first data line +// Purpose: aes_shiftrow for taking in first Data line // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -25,38 +25,38 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_shiftrow(input logic [127:0] dataIn, - output logic [127:0] dataOut); +module aes_shiftrow(input logic [127:0] DataIn, + output logic [127:0] DataOut); // (This form of writing it may seem like more effort but I feel // like it is more self-explanatory this way without losing efficiency) // Seperate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = dataIn[7:0]; - logic [7:0] w0_b1 = dataIn[79:72]; - logic [7:0] w0_b2 = dataIn[23:16]; - logic [7:0] w0_b3 = dataIn[95:88]; + logic [7:0] w0_b0 = DataIn[7:0]; + logic [7:0] w0_b1 = DataIn[79:72]; + logic [7:0] w0_b2 = DataIn[23:16]; + logic [7:0] w0_b3 = DataIn[95:88]; // Seperate the second word into bytes - logic [7:0] w1_b0 = dataIn[39:32]; - logic [7:0] w1_b1 = dataIn[111:104]; - logic [7:0] w1_b2 = dataIn[55:48]; - logic [7:0] w1_b3 = dataIn[127:120]; + logic [7:0] w1_b0 = DataIn[39:32]; + logic [7:0] w1_b1 = DataIn[111:104]; + logic [7:0] w1_b2 = DataIn[55:48]; + logic [7:0] w1_b3 = DataIn[127:120]; // Seperate the third word into bytes - logic [7:0] w2_b0 = dataIn[71:64]; - logic [7:0] w2_b1 = dataIn[15:8]; - logic [7:0] w2_b2 = dataIn[87:80]; - logic [7:0] w2_b3 = dataIn[31:24]; + logic [7:0] w2_b0 = DataIn[71:64]; + logic [7:0] w2_b1 = DataIn[15:8]; + logic [7:0] w2_b2 = DataIn[87:80]; + logic [7:0] w2_b3 = DataIn[31:24]; // Seperate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = dataIn[103:96]; - logic [7:0] w3_b1 = dataIn[47:40]; - logic [7:0] w3_b2 = dataIn[119:112]; - logic [7:0] w3_b3 = dataIn[63:56]; + logic [7:0] w3_b0 = DataIn[103:96]; + logic [7:0] w3_b1 = DataIn[47:40]; + logic [7:0] w3_b2 = DataIn[119:112]; + logic [7:0] w3_b3 = DataIn[63:56]; // The output words are composed of sets of the input bytes. logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; - assign dataOut = {out_w0, out_w1, out_w2, out_w3}; + assign DataOut = {out_w0, out_w1, out_w2, out_w3}; endmodule diff --git a/src/ieu/aes_common/aes_shiftword.sv b/src/ieu/aes_common/aes_shiftword.sv index 9df834b65..c76e69d1f 100644 --- a/src/ieu/aes_common/aes_shiftword.sv +++ b/src/ieu/aes_common/aes_shiftword.sv @@ -33,26 +33,26 @@ input selection. */ -module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] dataIn, - output logic [31:0] dataOut); +module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] DataIn, + output logic [31:0] DataOut); - logic [7:0] b0 = dataIn[7:0]; - logic [7:0] b1 = dataIn[15:8]; - logic [7:0] b2 = dataIn[23:16]; - logic [7:0] b3 = dataIn[31:24]; + logic [7:0] b0 = DataIn[7:0]; + logic [7:0] b1 = DataIn[15:8]; + logic [7:0] b2 = DataIn[23:16]; + logic [7:0] b3 = DataIn[31:24]; always_comb begin case(shiftAmt) // 00 : Barrel Shift no bytes - 2'b00 : dataOut = {b3, b2, b1, b0}; + 2'b00 : DataOut = {b3, b2, b1, b0}; // 01 : Barrel Shift one byte - 2'b01 : dataOut = {b0, b3, b2, b1}; + 2'b01 : DataOut = {b0, b3, b2, b1}; // 10 : Barrel Shift two bytes - 2'b10 : dataOut = {b1, b0, b3, b2}; + 2'b10 : DataOut = {b1, b0, b3, b2}; // 11 : Barrel Shift three bytes - default : dataOut = {b2, b1, b0, b3}; + default : DataOut = {b2, b1, b0, b3}; endcase end diff --git a/src/ieu/aes_common/gm11.sv b/src/ieu/aes_common/gm11.sv index c4537e269..d5b22914b 100644 --- a/src/ieu/aes_common/gm11.sv +++ b/src/ieu/aes_common/gm11.sv @@ -25,20 +25,20 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm11 (gm11_in, gm11_out); +module gm11 (gm11_In, gm11_Out); - input logic [7:0] gm11_in; - output logic [7:0] gm11_out; + input logic [7:0] gm11_In; + output logic [7:0] gm11_Out; // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm2_0_out; + logic [7:0] gm8_0_Out; + logic [7:0] gm2_0_Out; // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); - gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); + gm8 gm8_0 (.gm8_In(gm11_In), .gm8_Out(gm8_0_Out)); + gm2 gm2_0 (.gm2_In(gm11_In), .gm2_Out(gm2_0_Out)); // Set output to gm8(in) ^ gm2(in) ^ in - assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; + assign gm11_Out = gm8_0_Out ^ gm2_0_Out ^ gm11_In; endmodule diff --git a/src/ieu/aes_common/gm13.sv b/src/ieu/aes_common/gm13.sv index 0dfe3c8dd..3fd7889b3 100644 --- a/src/ieu/aes_common/gm13.sv +++ b/src/ieu/aes_common/gm13.sv @@ -25,20 +25,20 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm13 (gm13_in, gm13_out); +module gm13 (gm13_In, gm13_Out); - input logic [7:0] gm13_in; - output logic [7:0] gm13_out; + input logic [7:0] gm13_In; + output logic [7:0] gm13_Out; // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm4_0_out; + logic [7:0] gm8_0_Out; + logic [7:0] gm4_0_Out; // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); - gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); + gm8 gm8_0 (.gm8_In(gm13_In), .gm8_Out(gm8_0_Out)); + gm4 gm4_0 (.gm4_In(gm13_In), .gm4_Out(gm4_0_Out)); // Set output to gm8(in) ^ gm4(in) ^ in - assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; + assign gm13_Out = gm8_0_Out ^ gm4_0_Out ^ gm13_In; endmodule diff --git a/src/ieu/aes_common/gm14.sv b/src/ieu/aes_common/gm14.sv index 48dd90251..eab5bb8a2 100644 --- a/src/ieu/aes_common/gm14.sv +++ b/src/ieu/aes_common/gm14.sv @@ -25,23 +25,23 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm14 (gm14_in, gm14_out); +module gm14 (gm14_In, gm14_Out); - input logic [7:0] gm14_in; - output logic [7:0] gm14_out; + input logic [7:0] gm14_In; + output logic [7:0] gm14_Out; // Internal Logic - logic [7:0] gm8_0_out; - logic [7:0] gm4_0_out; - logic [7:0] gm2_0_out; + logic [7:0] gm8_0_Out; + logic [7:0] gm4_0_Out; + logic [7:0] gm2_0_Out; // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); - gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); - gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); + gm8 gm8_0 (.gm8_In(gm14_In), .gm8_Out(gm8_0_Out)); + gm4 gm4_0 (.gm4_In(gm14_In), .gm4_Out(gm4_0_Out)); + gm2 gm2_0 (.gm2_In(gm14_In), .gm2_Out(gm2_0_Out)); //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) - assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; + assign gm14_Out = gm8_0_Out ^ gm4_0_Out ^ gm2_0_Out; endmodule diff --git a/src/ieu/aes_common/gm2.sv b/src/ieu/aes_common/gm2.sv index 073d252b6..a9e675be5 100644 --- a/src/ieu/aes_common/gm2.sv +++ b/src/ieu/aes_common/gm2.sv @@ -25,12 +25,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm2 (gm2_in, gm2_out); +module gm2 (gm2_In, gm2_Out); - input logic [7:0] gm2_in; - output logic [7:0] gm2_out; + input logic [7:0] gm2_In; + output logic [7:0] gm2_Out; // Set output to Galois Mult 2 - assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); + assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); endmodule diff --git a/src/ieu/aes_common/gm3.sv b/src/ieu/aes_common/gm3.sv index 602a1778f..886eb7115 100644 --- a/src/ieu/aes_common/gm3.sv +++ b/src/ieu/aes_common/gm3.sv @@ -25,18 +25,18 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm3 (gm3_in, gm3_out); +module gm3 (gm3_In, gm3_Out); - input logic [7:0] gm3_in; - output logic [7:0] gm3_out; + input logic [7:0] gm3_In; + output logic [7:0] gm3_Out; // Internal Logic - logic [7:0] gm2_0_out; + logic [7:0] gm2_0_Out; // Sub-Modules for gm2 multiplication - gm2 gm2_0 (.gm2_in(gm3_in), .gm2_out(gm2_0_out)); + gm2 gm2_0 (.gm2_In(gm3_In), .gm2_Out(gm2_0_Out)); // Assign Output - assign gm3_out = gm2_0_out ^ gm3_in; + assign gm3_Out = gm2_0_Out ^ gm3_In; endmodule diff --git a/src/ieu/aes_common/gm4.sv b/src/ieu/aes_common/gm4.sv index 2371c3aa9..9a74d7189 100644 --- a/src/ieu/aes_common/gm4.sv +++ b/src/ieu/aes_common/gm4.sv @@ -25,20 +25,20 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm4 (gm4_in, gm4_out); +module gm4 (gm4_In, gm4_Out); - input logic [7:0] gm4_in; - output logic [7:0] gm4_out; + input logic [7:0] gm4_In; + output logic [7:0] gm4_Out; // Internal Logic - logic [7:0] gm2_0_out; - logic [7:0] gm2_1_out; + logic [7:0] gm2_0_Out; + logic [7:0] gm2_1_Out; // Sub-Modules for multiple gm2 multiplications - gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out)); - gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out)); + gm2 gm2_0 (.gm2_In(gm4_In), .gm2_Out(gm2_0_Out)); + gm2 gm2_1 (.gm2_In(gm2_0_Out), .gm2_Out(gm2_1_Out)); // Assign output to second gm2 output - assign gm4_out = gm2_1_out; + assign gm4_Out = gm2_1_Out; endmodule diff --git a/src/ieu/aes_common/gm8.sv b/src/ieu/aes_common/gm8.sv index ad66c7958..8fc228e4b 100644 --- a/src/ieu/aes_common/gm8.sv +++ b/src/ieu/aes_common/gm8.sv @@ -25,20 +25,20 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm8 (gm8_in, gm8_out); +module gm8 (gm8_In, gm8_Out); - input logic [7:0] gm8_in; - output logic [7:0] gm8_out; + input logic [7:0] gm8_In; + output logic [7:0] gm8_Out; // Internal Logic - logic [7:0] gm2_0_out; - logic [7:0] gm4_0_out; + logic [7:0] gm2_0_Out; + logic [7:0] gm4_0_Out; // Sub-Modules for sub-Galois operations - gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out)); - gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out)); + gm4 gm4_0 (.gm4_In(gm8_In), .gm4_Out(gm4_0_Out)); + gm2 gm2_0 (.gm2_In(gm4_0_Out), .gm2_Out(gm2_0_Out)); // Assign output to gm2 output - assign gm8_out = gm2_0_out; + assign gm8_Out = gm2_0_Out; endmodule diff --git a/src/ieu/aes_common/gm9.sv b/src/ieu/aes_common/gm9.sv index a26414e2f..1e00d3cf6 100644 --- a/src/ieu/aes_common/gm9.sv +++ b/src/ieu/aes_common/gm9.sv @@ -25,18 +25,18 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm9 (gm9_in, gm9_out); +module gm9 (gm9_In, gm9_Out); - input logic [7:0] gm9_in; - output logic [7:0] gm9_out; + input logic [7:0] gm9_In; + output logic [7:0] gm9_Out; // Internal Logic - logic [7:0] gm8_0_out; + logic [7:0] gm8_0_Out; // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); + gm8 gm8_0 (.gm8_In(gm9_In), .gm8_Out(gm8_0_Out)); // Set output to gm8(in) ^ in - assign gm9_out = gm8_0_out ^ gm9_in; + assign gm9_Out = gm8_0_Out ^ gm9_In; endmodule diff --git a/src/ieu/aes_common/mixword.sv b/src/ieu/aes_common/mixword.sv index 462658c53..fdad29577 100644 --- a/src/ieu/aes_common/mixword.sv +++ b/src/ieu/aes_common/mixword.sv @@ -34,14 +34,14 @@ module mixword (word, mixed_word); // Declare Internal Signals logic [7:0] b0, b1, b2, b3; logic [7:0] mb0, mb1, mb2, mb3; - logic [7:0] gm2_0_out; - logic [7:0] gm3_0_out; - logic [7:0] gm2_1_out; - logic [7:0] gm3_1_out; - logic [7:0] gm2_2_out; - logic [7:0] gm3_2_out; - logic [7:0] gm2_3_out; - logic [7:0] gm3_3_out; + logic [7:0] gm2_0_Out; + logic [7:0] gm3_0_Out; + logic [7:0] gm2_1_Out; + logic [7:0] gm3_1_Out; + logic [7:0] gm2_2_Out; + logic [7:0] gm3_2_Out; + logic [7:0] gm2_3_Out; + logic [7:0] gm3_3_Out; // Break word into bytes assign b0 = word[31:24]; @@ -50,23 +50,23 @@ module mixword (word, mixed_word); assign b3 = word[7:0]; // mb0 Galois components - gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out)); - gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out)); + gm2 gm2_0(.gm2_In(b0), .gm2_Out(gm2_0_Out)); + gm3 gm3_0(.gm3_In(b3), .gm3_Out(gm3_0_Out)); // mb1 Galois components - gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out)); - gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out)); + gm2 gm2_1(.gm2_In(b1), .gm2_Out(gm2_1_Out)); + gm3 gm3_1(.gm3_In(b0), .gm3_Out(gm3_1_Out)); // mb2 Galois components - gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out)); - gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out)); + gm2 gm2_2(.gm2_In(b2), .gm2_Out(gm2_2_Out)); + gm3 gm3_2(.gm3_In(b1), .gm3_Out(gm3_2_Out)); // mb3 Galois components - gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out)); - gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out)); + gm2 gm2_3(.gm2_In(b3), .gm2_Out(gm2_3_Out)); + gm3 gm3_3(.gm3_In(b2), .gm3_Out(gm3_3_Out)); // Combine Componenets into mixed word - assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; - assign mb1 = gm2_1_out ^ gm3_1_out ^ b2 ^ b3; - assign mb2 = gm2_2_out ^ gm3_2_out ^ b0 ^ b3; - assign mb3 = gm2_3_out ^ gm3_3_out ^ b0 ^ b1; + assign mb0 = gm2_0_Out ^ gm3_0_Out ^ b1 ^ b2; + assign mb1 = gm2_1_Out ^ gm3_1_Out ^ b2 ^ b3; + assign mb2 = gm2_2_Out ^ gm3_2_Out ^ b0 ^ b3; + assign mb3 = gm2_3_Out ^ gm3_3_Out ^ b0 ^ b1; assign mixed_word = {mb0, mb1, mb2, mb3}; endmodule diff --git a/src/ieu/aes_common/rotateleft.sv b/src/ieu/aes_common/rotateleft.sv index 363e3526c..74862b47d 100644 --- a/src/ieu/aes_common/rotateleft.sv +++ b/src/ieu/aes_common/rotateleft.sv @@ -25,10 +25,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rotate_left(input logic [31:0] input_data, +module rotate_left(input logic [31:0] Input_Data, input logic [4:0] shamt, - output logic [31:0] rot_data); + output logic [31:0] Rot_Data); - assign rot_data = (input_data << shamt) | (input_data >> (32 - shamt)); + assign Rot_Data = (Input_Data << shamt) | (Input_Data >> (32 - shamt)); endmodule diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 52dc2e8b5..016cce1f1 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -28,13 +28,13 @@ module aes32dsi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] Data_Out); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] sbox_in_32; - logic [7:0] sbox_in; - logic [7:0] sbox_out; + logic [31:0] Sbox_In_32; + logic [7:0] Sbox_In; + logic [7:0] Sbox_Out; logic [31:0] so; logic [31:0] so_rotate; @@ -42,18 +42,18 @@ module aes32dsi(input logic [1:0] bs, assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt and take the lower byte - assign sbox_in_32 = (rs2 >> shamt); - assign sbox_in = sbox_in_32[7:0]; + assign Sbox_In_32 = (rs2 >> shamt); + assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out)); + aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box - assign so = {24'h0, sbox_out}; + assign so = {24'h0, Sbox_Out}; // Rotate the substitution box output left by shamt (bs * 8) rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" - assign data_out = rs1 ^ so_rotate; + assign Data_Out = rs1 ^ so_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 1fa6560bb..7db429c9d 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -28,13 +28,13 @@ module aes32dsmi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] Data_Out); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] sbox_in_32; - logic [7:0] sbox_in; - logic [7:0] sbox_out; + logic [31:0] Sbox_In_32; + logic [7:0] Sbox_In; + logic [7:0] Sbox_Out; logic [31:0] so; logic [31:0] mixed; logic [31:0] mixed_rotate; @@ -43,14 +43,14 @@ module aes32dsmi(input logic [1:0] bs, assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt and take the lower byte - assign sbox_in_32 = (rs2 >> shamt); - assign sbox_in = sbox_in_32[7:0]; + assign Sbox_In_32 = (rs2 >> shamt); + assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(sbox_in), .out(sbox_out)); + aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box - assign so = {24'h0, sbox_out}; + assign so = {24'h0, Sbox_Out}; // Run so through the mixword AES function inv_mixword mix(.word(so), .mixed_word(mixed)); @@ -59,5 +59,5 @@ module aes32dsmi(input logic [1:0] bs, rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" - assign data_out = rs1 ^ mixed_rotate; + assign Data_Out = rs1 ^ mixed_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index 4d9ff0edd..c34caa062 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -28,13 +28,13 @@ module aes32esi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] Data_Out); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] sbox_in_32; - logic [7:0] sbox_in; - logic [7:0] sbox_out; + logic [31:0] Sbox_In_32; + logic [7:0] Sbox_In; + logic [7:0] Sbox_Out; logic [31:0] so; logic [31:0] so_rotate; @@ -42,20 +42,20 @@ module aes32esi(input logic [1:0] bs, assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt to get sbox input - assign sbox_in_32 = (rs2 >> shamt); + assign Sbox_In_32 = (rs2 >> shamt); // Take the bottom byte as an input to the substitution box - assign sbox_in = sbox_in_32[7:0]; + assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_sbox subbox(.in(sbox_in), .out(sbox_out)); + aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output - assign so = {24'h0, sbox_out}; + assign so = {24'h0, Sbox_Out}; // Rotate so left by shamt rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); - assign data_out = rs1 ^ so_rotate; + assign Data_Out = rs1 ^ so_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index a822edc3d..25874b231 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -28,13 +28,13 @@ module aes32esmi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] Data_Out); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] sbox_in_32; - logic [7:0] sbox_in; - logic [7:0] sbox_out; + logic [31:0] Sbox_In_32; + logic [7:0] Sbox_In; + logic [7:0] Sbox_Out; logic [31:0] so; logic [31:0] mixed; logic [31:0] mixed_rotate; @@ -43,16 +43,16 @@ module aes32esmi(input logic [1:0] bs, assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt to get sbox input - assign sbox_in_32 = (rs2 >> shamt); + assign Sbox_In_32 = (rs2 >> shamt); // Take the bottom byte as an input to the substitution box - assign sbox_in = sbox_in_32[7:0]; + assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_sbox sbox(.in(sbox_in), .out(sbox_out)); + aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output - assign so = {24'h0, sbox_out}; + assign so = {24'h0, Sbox_Out}; // Mix Word using aes_mixword component mixword mwd(.word(so), .mixed_word(mixed)); @@ -61,5 +61,5 @@ module aes32esmi(input logic [1:0] bs, rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); - assign data_out = rs1 ^ mixed_rotate; + assign Data_Out = rs1 ^ mixed_rotate; endmodule diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index 114d6a900..cb63fbf65 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -27,20 +27,20 @@ module aes64ds(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] data_out); + output logic [63:0] Data_Out); // Intermediary Logic - logic [127:0] shiftRow_out; - logic [31:0] sbox_out_0; - logic [31:0] sbox_out_1; + logic [127:0] ShiftRow_Out; + logic [31:0] Sbox_Out_0; + logic [31:0] Sbox_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); + aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0)); - aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1)); + aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Concatenate the two substitution outputs to get result - assign data_out = {sbox_out_1, sbox_out_0}; + assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; endmodule diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 0b417e896..7ed85bcf3 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -27,26 +27,26 @@ module aes64dsm(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] data_out); + output logic [63:0] Data_Out); // Intermediary Logic - logic [127:0] shiftRow_out; - logic [31:0] sbox_out_0; - logic [31:0] sbox_out_1; - logic [31:0] mixcol_out_0; - logic [31:0] mixcol_out_1; + logic [127:0] ShiftRow_Out; + logic [31:0] Sbox_Out_0; + logic [31:0] Sbox_Out_1; + logic [31:0] Mixcol_Out_0; + logic [31:0] Mixcol_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); + aes_inv_shiftrow srow(.dataIn({rs2, rs1}), .dataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out_0)); - aes_inv_sbox_word inv_sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out_1)); + aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Apply inverse mixword to sbox outputs - inv_mixword inv_mw_0(.word(sbox_out_0), .mixed_word(mixcol_out_0)); - inv_mixword inv_mw_1(.word(sbox_out_1), .mixed_word(mixcol_out_1)); + inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); + inv_mixword inv_mw_1(.word(Sbox_Out_1), .mixed_word(Mixcol_Out_1)); // Concatenate mixed words for output - assign data_out = {mixcol_out_1, mixcol_out_0}; + assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0}; endmodule diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index a31177823..97db8e443 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -27,15 +27,15 @@ module aes64es(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] data_out); + output logic [63:0] Data_Out); // Intermediary Signals - logic [127:0] shiftRow_out; + logic [127:0] ShiftRow_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(data_out[31:0])); - aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(data_out[63:32])); + aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); + aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 6584525a5..be73d87dc 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -27,20 +27,20 @@ module aes64esm(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] data_out); + output logic [63:0] Data_Out); // Intermediary Signals - logic [127:0] shiftRow_out; - logic [63:0] sbox_out; + logic [127:0] ShiftRow_Out; + logic [63:0] Sbox_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(shiftRow_out)); + aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(shiftRow_out[31:0]), .out(sbox_out[31:0])); - aes_sbox_word sbox_1(.in(shiftRow_out[63:32]), .out(sbox_out[63:32])); + aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); + aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); // Apply mix columns operations - mixword mw0(.word(sbox_out[31:0]), .mixed_word(data_out[31:0])); - mixword mw1(.word(sbox_out[63:32]), .mixed_word(data_out[63:32])); + mixword mw0(.word(Sbox_Out[31:0]), .mixed_word(Data_Out[31:0])); + mixword mw1(.word(Sbox_Out[63:32]), .mixed_word(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index b82ed874b..28aef331c 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -26,8 +26,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aes64im(input logic [63:0] rs1, - output logic [63:0] data_out); + output logic [63:0] Data_Out); - inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(data_out[31:0])); - inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(data_out[63:32])); + inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(Data_Out[31:0])); + inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 6ebfe35eb..4738bb747 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -35,7 +35,7 @@ module aes64ks1i(input logic [3:0] roundnum, logic lastRoundFlag; logic [31:0] rs1_rotate; logic [31:0] tmp2; - logic [31:0] sbox_out; + logic [31:0] Sbox_Out; // Get rcon value from table rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); @@ -48,9 +48,9 @@ module aes64ks1i(input logic [3:0] roundnum, // Assign tmp2 to a mux based on lastRoundFlag assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; // Substitute bytes of value obtained for tmp2 using Rijndael sbox - aes_sbox_word sbox(.in(tmp2),.out(sbox_out)); - assign rd[31:0] = sbox_out ^ rcon; - assign rd[63:32] = sbox_out ^ rcon; + aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out)); + assign rd[31:0] = Sbox_Out ^ rcon; + assign rd[63:32] = Sbox_Out ^ rcon; // There may be some errors with this instruction. // Regression tests are passed successfully, but diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 335eaccac..ae573ca70 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -2,9 +2,8 @@ // alu.sv // // Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu -// kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 9 January 2021 -// Modified: 3 March 2023, 22 February 2024 +// Modified: 3 March 2023 // // Purpose: RISC-V Arithmetic/Logic Unit // @@ -92,11 +91,10 @@ module alu import cvw::*; #(parameter cvw_t P) ( else assign PreALUResult = FullResult; // Bit manipulation muxing - if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | - P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu + if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu bitmanipalu #(P) balu( .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive, - .Funct3, .Funct7, .Rs2E, .LT, .LTU, .BALUControl, .PreALUResult, .FullResult, + .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin assign ALUResult = PreALUResult; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d9c076dbd..9bb40af12 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -43,7 +43,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic StructuralStallD, // Structural stalls detected by controller output logic LoadStallD, // Structural stalls for load, sent to performance counters output logic StoreStallD, // load after store hazard - output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage + output logic [4:0] Rs1D, Rs2D, Rs2E, // Register sources to read in Decode or Execute stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] FlagsE, // Comparison flags ({eq, lt}) @@ -55,6 +55,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field + output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -63,8 +64,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic BranchE, // Branch instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction - output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage + output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [3:0] ZBBSelectE, // ZBB mux select signal in Execute stage output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active @@ -95,7 +96,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [4:0] RdW // Register destinations in Execute, Memory, or Writeback stage ); - logic [4:0] Rs1E, Rs2E; // pipelined register sources + logic [4:0] Rs1E; // pipelined register sources logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage @@ -138,8 +139,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction - logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage - logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [3:0] ZBBSelectD; // ZBB Mux Select Signal logic [1:0] CZeroD; logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions @@ -351,9 +352,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand // tie off unused bit manipulation signals - assign BSelectE = 2'b00; - assign BSelectD = 2'b00; - assign ZBBSelectE = 3'b000; + assign BSelectE = 4'b0000; + assign BSelectD = 4'b0000; + assign ZBBSelectE = 4'b0000; assign BALUControlE = 3'b0; assign BMUActiveE = 1'b0; end @@ -417,9 +418,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(37) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); + flopenrc #(44) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); From 50cbe54d7b172632d5c1f46bf282004e2ecfed85 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:22:19 -0600 Subject: [PATCH 17/47] Add datapath.sv --- src/ieu/datapath.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index eb6fd1d81..49da4e0cb 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -33,11 +33,12 @@ module datapath import cvw::*; #(parameter cvw_t P) ( // Decode stage signals input logic [2:0] ImmSrcD, // Selects type of immediate extension input logic [31:0] InstrD, // Instruction in Decode stage - input logic [4:0] Rs1D, Rs2D, // Source registers + input logic [4:0] Rs1D, Rs2D, Rs2E, // Source registers // Execute stage signals input logic [P.XLEN-1:0] PCE, // PC in Execute stage input logic [P.XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage + input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic W64E, // W64-type instruction @@ -47,8 +48,8 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelectE, // ZBB mux select signal + input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelectE, // ZBB mux select signal input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage input logic BMUActiveE, // Bit manipulation instruction being executed input logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active @@ -109,7 +110,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); + alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); From cd2a9b87128d84e10287cb2b32d0cf98a1195b05 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:26:21 -0600 Subject: [PATCH 18/47] Add mux7 for K ext --- src/generic/mux.sv | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 5a4767c87..f07efeb5c 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -65,6 +65,15 @@ module mux6 #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] y); assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); +endmodule // mux6 + +module mux7 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, + input logic [2:0] s, + output logic [WIDTH-1:0] y); + + assign y = s[2] ? (s[1] ? d6 : (s[0] ? d5 : d4)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); + endmodule /* verilator lint_on DECLFILENAME */ From 71cefdbbb2b47cf42e8aeff37b1be0da846dd3b5 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:35:56 -0600 Subject: [PATCH 19/47] main cvw module --- src/cvw.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/cvw.sv b/src/cvw.sv index 75f83f68b..4defa196a 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -180,6 +180,16 @@ typedef struct packed { logic ZCD_SUPPORTED; logic ZCF_SUPPORTED; +// Cryptography + logic ZBKB_SUPPORTED; + logic ZBKC_SUPPORTED; + logic ZBKX_SUPPORTED; + logic ZKND_SUPPORTED; + logic ZKNE_SUPPORTED; + logic ZKNH_SUPPORTED; + logic ZKSED_SUPPORTED; + logic ZKSH_SUPPORTED; + // Memory synthesis configuration logic USE_SRAM; From ce975a63367a6d97cce45ca03ad873c2211519e9 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:37:04 -0600 Subject: [PATCH 20/47] Add ieu main module for k extension --- src/ieu/ieu.sv | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 438ca7534..38d50e3c3 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -90,13 +90,16 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [3:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage logic SubArithE; // Subtraction or arithmetic shift + logic [6:0] Funct7E; + // Forwarding signals - logic [4:0] Rs1D, Rs2D; // Source registers + logic [4:0] Rs1D, Rs2D; + logic [4:0] Rs2E; // Source registers logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction @@ -108,10 +111,10 @@ module ieu import cvw::*; #(parameter cvw_t P) ( controller #(P) c( .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, - .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, + .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, + .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, @@ -120,8 +123,8 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .RdW, .RdE, .RdM); datapath #(P) dp( - .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, - .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, + .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, + .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From eb1780a66d1450a00cbfc4b9d7caf50abf7ebefb Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:38:21 -0600 Subject: [PATCH 21/47] control for bitmanip --- src/ieu/bmu/bitmanipalu.sv | 76 +++++++++++-- src/ieu/bmu/bmuctrl.sv | 219 ++++++++++++++++++++++++++++--------- 2 files changed, 233 insertions(+), 62 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 3f7d0ae7a..373dbe437 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -31,9 +31,11 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] A, B, // Operands input logic W64, // W64-type instruction - input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform + input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations + input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND input logic LT, // less than flag input logic LTU, // less than unsigned flag input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage @@ -43,7 +45,10 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions output logic [P.XLEN-1:0] ALUResult); // Result - logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result + logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result + logic [P.XLEN-1:0] ZBKBResult, ZBKCResult, ZBKXResult; // ZBKB, ZBKC Result + logic [P.XLEN-1:0] ZKNDResult, ZKNEResult; // ZKND, ZKNE Result + logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result logic [P.XLEN-1:0] MaskB; // BitMask of B logic [P.XLEN-1:0] RevA; // Bit-reversed A logic Rotate; // Indicates if it is Rotate instruction @@ -90,16 +95,69 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZBB Unit if (P.ZBB_SUPPORTED) begin: zbb - zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); + zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult); end else assign ZBBResult = 0; + // ZBKB Unit + if (P.ZBKB_SUPPORTED) begin: zbkb + zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); + end else assign ZBKBResult = 0; + + // ZBKC Unit + if (P.ZBKC_SUPPORTED) begin: zbkc + zbkc #(P.XLEN) ZBKC(.A(ABMU), .B(BBMU), .ZBKCSelect(ZBBSelect[0]), .ZBKCResult); + end else assign ZBKCResult = 0; + + // ZBKX Unit + if (P.ZBKX_SUPPORTED) begin: zbkx + zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult); + end else assign ZBKXResult = 0; + + // ZKND Unit + if (P.ZKND_SUPPORTED) begin: zknd + if (P.XLEN == 32) begin + zknd_32 #(P.XLEN) ZKND32(.A(ABMU), .B(BBMU), .Funct7, .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); + end + else begin + zknd_64 #(P.XLEN) ZKND64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); + end + end else assign ZKNDResult = 0; + + // ZKNE Unit + if (P.ZKNE_SUPPORTED) begin: zkne + if (P.XLEN == 32) begin + zkne_32 #(P.XLEN) ZKNE32(.A(ABMU), .B(BBMU), .Funct7, .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); + end + else begin + zkne_64 #(P.XLEN) ZKNE64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); + end + end else assign ZKNEResult = 0; + + // ZKNH Unit + if (P.ZKNH_SUPPORTED) begin: zknh + if (P.XLEN == 32) begin + zknh_32 ZKNH_32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + end + else begin + zknh_64 ZKNH_64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + end + end else assign ZKNHResult = 0; + // Result Select Mux always_comb case (BSelect) - // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: ALUResult = PreALUResult; - 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: ALUResult = ZBBResult; - 2'b11: ALUResult = ZBCResult; + // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC, 0100: ZBKB, 0101: ZBKC, 0110: ZBKX + // 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH... + 4'b0000: ALUResult = PreALUResult; + 4'b0001: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 4'b0010: ALUResult = ZBBResult; + 4'b0011: ALUResult = ZBCResult; + 4'b0100: ALUResult = ZBKBResult; + 4'b0101: ALUResult = ZBKCResult; + 4'b0110: ALUResult = ZBKXResult; + 4'b0111: ALUResult = ZKNDResult; + 4'b1000: ALUResult = ZKNEResult; + 4'b1001: ALUResult = ZKNHResult; + default: ALUResult = PreALUResult; endcase endmodule diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 5b758f123..19ed746b7 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -34,8 +34,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage input logic ALUOpD, // Regular ALU Operation - output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage - output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [3:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage @@ -44,8 +44,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectD, // ALU select - output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - output logic [2:0] ZBBSelectE, // ZBB mux select signal + output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [3:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE // Bit manipulation instruction being executed @@ -62,7 +62,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage - `define BMUCTRLW 17 + `define BMUCTRLW 20 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -78,92 +78,205 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction; if (P.ZBA_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh3add endcase if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw endcase end if (P.ZBB_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0; // count instruction // // coverage off: This case can't occur in RV64 // 17'b0110011_0000100_100: if (P.XLEN == 32) // BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) // // coverage on - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // minu endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // zexth (rv32) endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_1_0_0_0_0_0; // zexth (rv64) 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction endcase end if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction endcase if (P.ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0; // bset endcase if (P.XLEN==32) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti endcase else if (P.XLEN==64) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti (rv64) endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw endcase + + if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip + casez({OpD,Funct7D, Funct3D}) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // pack + 17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; //packh + 17'b0010011_0110100_101: if (Rs2D == 5'b00111) + BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0; //brev8 + endcase + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0000100_001: if (Rs2D == 5'b01111) + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //zip + 17'b0010011_0000100_101: if (Rs2D == 5'b01111) + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //unzip + endcase + else if (P.XLEN==64) + casez({OpD,Funct7D, Funct3D}) + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw + endcase + end + + if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // ror + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // rev8 + endcase + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv32) + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_1_0_1_0_0_0; // roriw + endcase + end + + if (P.ZBKC_SUPPORTED) begin // ZBKC + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0101_0000_1_0_0_1_0_0_0_0_0; // clmul + 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0101_0001_1_0_0_1_0_0_0_0_0; // clmulh + endcase + end + + if (P.ZBKX_SUPPORTED) begin //ZBKX + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8 + 17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_1_0_0_0_0_0; // xperm4 + endcase + end + + if (P.ZKND_SUPPORTED) begin //ZKND + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes32dsi - final round decrypt + 17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes32dsmi - mid round decrypt + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes64ds - decrypt final round + 17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes64dsm - decrypt mid round + 17'b0010011_0011000_001: if (Rs2D == 5'b00000) + BMUControlsD = `BMUCTRLW'b000_0111_0010_1_1_0_1_0_0_0_0_0; // aes64im - decrypt keyschdule mixcolumns + endcase + end + + if (P.ZKNE_SUPPORTED) begin //ZKNE + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // aes32esi - final round encrypt + 17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // aes32esmi - mid round encrypt + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // aes64es - encrypt final round + 17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // aes64esm - encrypt mid round + endcase + end + + if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin // ZKND and ZKNE shared instructions + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1) + BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 ... Don't know why this works here only ... P.XLEN is not 64 bits? + endcase + if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 + endcase + end + + if (P.ZKNH_SUPPORTED) begin // ZKNH + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0001000_001: + if (Rs2D == 5'b00010) BMUControlsD = `BMUCTRLW'b000_1001_0000_1_0_0_1_0_0_0_0_0; // sha256sig0 + else if (Rs2D == 5'b00011) BMUControlsD = `BMUCTRLW'b000_1001_0001_1_0_0_1_0_0_0_0_0; // sha256sig1 + else if (Rs2D == 5'b00000) BMUControlsD = `BMUCTRLW'b000_1001_0010_1_0_0_1_0_0_0_0_0; // sha256sum0 + else if (Rs2D == 5'b00001) BMUControlsD = `BMUCTRLW'b000_1001_0011_1_0_0_1_0_0_0_0_0; // sha256sum1 + endcase + + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1001_0100_1_0_0_1_0_0_0_0_0; // sha512sig0h + 17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1001_0101_1_0_0_1_0_0_0_0_0; // sha512sig0l + 17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1001_0110_1_0_0_1_0_0_0_0_0; // sha512sig1h + 17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1001_0111_1_0_0_1_0_0_0_0_0; // sha512sig1l + 17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1001_1000_1_0_0_1_0_0_0_0_0; // sha512sum0r + 17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1001_1001_1_0_0_1_0_0_0_0_0; // sha512sum1r + endcase + + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0001000_001: + if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1001_1010_1_0_0_1_0_0_0_0_0; // sha512sig0 + else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1001_1011_1_0_0_1_0_0_0_0_0; // sha512sig1 + else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1001_1100_1_0_0_1_0_0_0_0_0; // sha512sum0 + else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1001_1101_1_0_0_1_0_0_0_0_0; // sha512sum1 + endcase + end end // Unpack Control Signals @@ -176,5 +289,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); // BMU Execute stage pipieline control register - flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); + flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); endmodule From 0d4d996655efaa6410d7a60da724e0833840968b Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 24 Feb 2024 22:43:33 -0600 Subject: [PATCH 22/47] add spike riscof items for K extension test --- tests/riscof/spike/spike_rv32gc_isa.yaml | 3 ++- tests/riscof/spike/spike_rv64gc_isa.yaml | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index c2c95fbf4..d13420bba 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh +# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 4374ad07c..a40b579bd 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,7 +2,8 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb +# ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb + ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From 01c45ab9d7b39d4364c221b54a85649ffca8137f Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Wed, 28 Feb 2024 17:05:08 -0600 Subject: [PATCH 23/47] Fixed K extension changes --- config/rv32gc/config.vh | 14 ++-- config/rv64gc/config.vh | 14 ++-- config/shared/config-shared.vh | 1 + config/shared/parameter-defs.vh | 8 ++ sim/regression-wally | 4 +- src/cvw.sv | 4 +- src/ieu/aes_common/aes_inv_shiftrow.sv | 49 ++++++------ src/ieu/aes_common/aes_shiftrow.sv | 46 +++++++----- src/ieu/aes_instructions/aes32dsi.sv | 5 +- src/ieu/aes_instructions/aes32dsmi.sv | 5 +- src/ieu/aes_instructions/aes32esi.sv | 3 +- src/ieu/aes_instructions/aes32esmi.sv | 3 +- src/ieu/aes_instructions/aes64ds.sv | 6 +- src/ieu/aes_instructions/aes64dsm.sv | 6 +- src/ieu/aes_instructions/aes64es.sv | 2 +- src/ieu/aes_instructions/aes64esm.sv | 2 +- src/ieu/aes_instructions/aes64ks1i.sv | 60 --------------- src/ieu/kmu/packer.sv | 56 ++++++-------- src/ieu/kmu/zknd_32.sv | 4 +- src/ieu/kmu/zknd_64.sv | 6 +- src/ieu/kmu/zkne_32.sv | 4 +- src/ieu/kmu/zkne_64.sv | 4 +- testbench/common/instrNameDecTB.sv | 32 +++++++- testbench/testbench-xcelium.sv | 12 +++ testbench/testbench.sv | 12 +++ testbench/tests.vh | 96 ++++++++++++++++++++++++ tests/riscof/spike/riscof_spike.py | 12 +++ tests/riscof/spike/spike_rv32e_isa.yaml | 2 +- tests/riscof/spike/spike_rv32gc_isa.yaml | 2 +- tests/riscof/spike/spike_rv64gc_isa.yaml | 2 +- 30 files changed, 298 insertions(+), 178 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 29130e766..d6fb995b1 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -181,13 +181,13 @@ localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; // K extension instructions -localparam ZBKB_SUPPORTED = 0; -localparam ZBKC_SUPPORTED = 0; -localparam ZBKX_SUPPORTED = 0; -localparam ZKNE_SUPPORTED = 0; -localparam ZKND_SUPPORTED = 0; -localparam ZK_SUPPORTED = 0; -localparam ZKNH_SUPPORTED = 0; +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index a483ccbc4..1d6c5e9f4 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -182,13 +182,13 @@ localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; // K extension instructions -localparam ZBKB_SUPPORTED = 0; -localparam ZBKC_SUPPORTED = 0; -localparam ZBKX_SUPPORTED = 0; -localparam ZKNE_SUPPORTED = 0; -localparam ZKND_SUPPORTED = 0; -localparam ZK_SUPPORTED = 0; -localparam ZKNH_SUPPORTED = 0; +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index be5543967..954c45d7d 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -29,6 +29,7 @@ localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1); localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1); localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1); localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1); +localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED)); localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1); localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1); localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1); diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 464e3c0f9..5635b286c 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -113,6 +113,13 @@ localparam cvw_t P = '{ ZCB_SUPPORTED : ZCB_SUPPORTED, ZCD_SUPPORTED : ZCD_SUPPORTED, ZCF_SUPPORTED : ZCF_SUPPORTED, + ZBKB_SUPPORTED: ZBKB_SUPPORTED, + ZBKC_SUPPORTED: ZBKC_SUPPORTED, + ZBKX_SUPPORTED: ZBKX_SUPPORTED, + ZKND_SUPPORTED: ZKND_SUPPORTED, + ZKNE_SUPPORTED: ZKNE_SUPPORTED, + ZKNH_SUPPORTED: ZKNH_SUPPORTED, + ZK_SUPPORTED : ZK_SUPPORTED, USE_SRAM : USE_SRAM, M_MODE : M_MODE, S_MODE : S_MODE, @@ -136,6 +143,7 @@ localparam cvw_t P = '{ E_SUPPORTED : E_SUPPORTED, F_SUPPORTED : F_SUPPORTED, I_SUPPORTED : I_SUPPORTED, + K_SUPPORTED : K_SUPPORTED, M_SUPPORTED : M_SUPPORTED, Q_SUPPORTED : Q_SUPPORTED, S_SUPPORTED : S_SUPPORTED, diff --git a/sim/regression-wally b/sim/regression-wally index d06ac0b28..1d12a04ec 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -88,7 +88,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad", +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -127,7 +127,7 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] diff --git a/src/cvw.sv b/src/cvw.sv index 4defa196a..21b55c55e 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -187,8 +187,7 @@ typedef struct packed { logic ZKND_SUPPORTED; logic ZKNE_SUPPORTED; logic ZKNH_SUPPORTED; - logic ZKSED_SUPPORTED; - logic ZKSH_SUPPORTED; + logic ZK_SUPPORTED; // Memory synthesis configuration logic USE_SRAM; @@ -224,6 +223,7 @@ typedef struct packed { logic E_SUPPORTED; logic F_SUPPORTED; logic I_SUPPORTED; + logic K_SUPPORTED; logic M_SUPPORTED; logic Q_SUPPORTED; logic S_SUPPORTED; diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 5b417f78f..be7f106b6 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -27,33 +27,40 @@ module aes_Inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); - + + logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; + logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; + logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; + logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; + logic [31:0] out_w0, out_w1, out_w2, out_w3; + // Separate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = DataIn[7:0]; - logic [7:0] w0_b1 = DataIn[15:8]; - logic [7:0] w0_b2 = DataIn[23:16]; - logic [7:0] w0_b3 = DataIn[31:24]; + assign w0_b0 = DataIn[7:0]; + assign w0_b1 = DataIn[15:8]; + assign w0_b2 = DataIn[23:16]; + assign w0_b3 = DataIn[31:24]; // Separate the second word into bytes - logic [7:0] w1_b0 = DataIn[39:32]; - logic [7:0] w1_b1 = DataIn[47:40]; - logic [7:0] w1_b2 = DataIn[55:48]; - logic [7:0] w1_b3 = DataIn[63:56]; + assign w1_b0 = DataIn[39:32]; + assign w1_b1 = DataIn[47:40]; + assign w1_b2 = DataIn[55:48]; + assign w1_b3 = DataIn[63:56]; // Separate the third word into bytes - logic [7:0] w2_b0 = DataIn[71:64]; - logic [7:0] w2_b1 = DataIn[79:72]; - logic [7:0] w2_b2 = DataIn[87:80]; - logic [7:0] w2_b3 = DataIn[95:88]; + assign w2_b0 = DataIn[71:64]; + assign w2_b1 = DataIn[79:72]; + assign w2_b2 = DataIn[87:80]; + assign w2_b3 = DataIn[95:88]; // Separate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = DataIn[103:96]; - logic [7:0] w3_b1 = DataIn[111:104]; - logic [7:0] w3_b2 = DataIn[119:112]; - logic [7:0] w3_b3 = DataIn[127:120]; + assign w3_b0 = DataIn[103:96]; + assign w3_b1 = DataIn[111:104]; + assign w3_b2 = DataIn[119:112]; + assign w3_b3 = DataIn[127:120]; // The output words are composed of sets of the input bytes. - logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; assign DataOut = {out_w0, out_w1, out_w2, out_w3}; + endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 4206b7a01..0344d7e21 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -31,31 +31,37 @@ module aes_shiftrow(input logic [127:0] DataIn, // (This form of writing it may seem like more effort but I feel // like it is more self-explanatory this way without losing efficiency) + logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; + logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; + logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; + logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; + logic [31:0] out_w0, out_w1, out_w2, out_w3; + // Seperate the first (Least Significant) word into bytes - logic [7:0] w0_b0 = DataIn[7:0]; - logic [7:0] w0_b1 = DataIn[79:72]; - logic [7:0] w0_b2 = DataIn[23:16]; - logic [7:0] w0_b3 = DataIn[95:88]; + assign w0_b0 = DataIn[7:0]; + assign w0_b1 = DataIn[79:72]; + assign w0_b2 = DataIn[23:16]; + assign w0_b3 = DataIn[95:88]; // Seperate the second word into bytes - logic [7:0] w1_b0 = DataIn[39:32]; - logic [7:0] w1_b1 = DataIn[111:104]; - logic [7:0] w1_b2 = DataIn[55:48]; - logic [7:0] w1_b3 = DataIn[127:120]; + assign w1_b0 = DataIn[39:32]; + assign w1_b1 = DataIn[111:104]; + assign w1_b2 = DataIn[55:48]; + assign w1_b3 = DataIn[127:120]; // Seperate the third word into bytes - logic [7:0] w2_b0 = DataIn[71:64]; - logic [7:0] w2_b1 = DataIn[15:8]; - logic [7:0] w2_b2 = DataIn[87:80]; - logic [7:0] w2_b3 = DataIn[31:24]; + assign w2_b0 = DataIn[71:64]; + assign w2_b1 = DataIn[15:8]; + assign w2_b2 = DataIn[87:80]; + assign w2_b3 = DataIn[31:24]; // Seperate the fourth (Most significant) word into bytes - logic [7:0] w3_b0 = DataIn[103:96]; - logic [7:0] w3_b1 = DataIn[47:40]; - logic [7:0] w3_b2 = DataIn[119:112]; - logic [7:0] w3_b3 = DataIn[63:56]; + assign w3_b0 = DataIn[103:96]; + assign w3_b1 = DataIn[47:40]; + assign w3_b2 = DataIn[119:112]; + assign w3_b3 = DataIn[63:56]; // The output words are composed of sets of the input bytes. - logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; + assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; + assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; + assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; + assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; assign DataOut = {out_w0, out_w1, out_w2, out_w3}; diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 016cce1f1..58fc88c51 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -46,13 +46,14 @@ module aes32dsi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign Data_Out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 7db429c9d..df2bad83e 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -47,7 +47,7 @@ module aes32dsmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; @@ -56,7 +56,8 @@ module aes32dsmi(input logic [1:0] bs, inv_mixword mix(.word(so), .mixed_word(mixed)); // Rotate the substitution box output left by shamt (bs * 8) - rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" assign Data_Out = rs1 ^ mixed_rotate; diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index c34caa062..ed47e1d9d 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -54,7 +54,8 @@ module aes32esi(input logic [1:0] bs, assign so = {24'h0, Sbox_Out}; // Rotate so left by shamt - rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); + assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); assign Data_Out = rs1 ^ so_rotate; diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 25874b231..52d45c4de 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -58,7 +58,8 @@ module aes32esmi(input logic [1:0] bs, mixword mwd(.word(so), .mixed_word(mixed)); // Rotate so left by shamt - rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); + assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); assign Data_Out = rs1 ^ mixed_rotate; diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index cb63fbf65..d1892675c 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -35,11 +35,11 @@ module aes64ds(input logic [63:0] rs1, logic [31:0] Sbox_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_Inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Concatenate the two substitution outputs to get result assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 7ed85bcf3..241d718e2 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,11 +37,11 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] Mixcol_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.dataIn({rs2, rs1}), .dataOut(ShiftRow_Out)); + aes_Inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Apply inverse mixword to sbox outputs inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 97db8e443..58e6dfdc0 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,7 +33,7 @@ module aes64es(input logic [63:0] rs1, logic [127:0] ShiftRow_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index be73d87dc..80c8f34d6 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,7 +34,7 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] Sbox_Out; // AES shiftrow unit - aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 4738bb747..5ef76516c 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -58,63 +58,3 @@ module aes64ks1i(input logic [3:0] roundnum, endmodule -module rcon_lut_128(input logic [3:0] RD, - output logic [7:0] rcon_out); - - always_comb - begin - case(RD) - 4'h0 : rcon_out = 8'h01; - 4'h1 : rcon_out = 8'h02; - 4'h2 : rcon_out = 8'h04; - 4'h3 : rcon_out = 8'h08; - 4'h4 : rcon_out = 8'h10; - 4'h5 : rcon_out = 8'h20; - 4'h6 : rcon_out = 8'h40; - 4'h7 : rcon_out = 8'h80; - 4'h8 : rcon_out = 8'h1b; - 4'h9 : rcon_out = 8'h36; - 4'hA : rcon_out = 8'h00; - default : rcon_out = 8'h00; - endcase - end - -endmodule - -module rrot8(input logic[31:0] x, - output logic [31:0] result); - - assign result[0] = x[8]; - assign result[1] = x[9]; - assign result[2] = x[10]; - assign result[3] = x[11]; - assign result[4] = x[12]; - assign result[5] = x[13]; - assign result[6] = x[14]; - assign result[7] = x[15]; - assign result[8] = x[16]; - assign result[9] = x[17]; - assign result[10] = x[18]; - assign result[11] = x[19]; - assign result[12] = x[20]; - assign result[13] = x[21]; - assign result[14] = x[22]; - assign result[15] = x[23]; - assign result[16] = x[24]; - assign result[17] = x[25]; - assign result[18] = x[26]; - assign result[19] = x[27]; - assign result[20] = x[28]; - assign result[21] = x[29]; - assign result[22] = x[30]; - assign result[23] = x[31]; - assign result[24] = x[0]; - assign result[25] = x[1]; - assign result[26] = x[2]; - assign result[27] = x[3]; - assign result[28] = x[4]; - assign result[29] = x[5]; - assign result[30] = x[6]; - assign result[31] = x[7]; - -endmodule diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv index 42702d89c..1e0c3f542 100644 --- a/src/ieu/kmu/packer.sv +++ b/src/ieu/kmu/packer.sv @@ -30,38 +30,30 @@ module packer #(parameter WIDTH=32) ( input logic [2:0] PackSelect, output logic [WIDTH-1:0] PackResult); - logic [WIDTH/2-1:0] low_half, high_half; - logic [7:0] low_halfh, high_halfh; - logic [15:0] low_halfw, high_halfw; + logic [WIDTH/2-1:0] low_half, high_half; + logic [7:0] low_halfh, high_halfh; + logic [15:0] low_halfw, high_halfw; + + logic [WIDTH-1:0] Pack; + logic [WIDTH-1:0] PackH; + logic [WIDTH-1:0] PackW; - logic [WIDTH-1:0] Pack; - logic [WIDTH-1:0] PackH; - logic [WIDTH-1:0] PackW; - logic [1:0] MuxSelect; - - assign low_half = A[WIDTH/2-1:0]; - assign high_half = B[WIDTH/2-1:0]; - assign low_halfh = A[7:0]; - assign high_halfh = B[7:0]; - assign low_halfw = A[15:0]; - assign high_halfw = B[15:0]; - - assign Pack = {high_half, low_half}; - assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; - assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; - - // TODO: FIX THIS ... this is completely incorrect way to use if statements - // Solution for now: - always_comb - begin - if (PackSelect[1:0] == 2'b11) - MuxSelect = 2'b01; - else if (PackSelect[2] == 1'b0) - MuxSelect = 2'b00; - else - MuxSelect = 2'b10; - end - - mux3 #(WIDTH) PackMux(Pack, PackH, PackW, MuxSelect, PackResult); + assign low_half = A[WIDTH/2-1:0]; + assign high_half = B[WIDTH/2-1:0]; + assign low_halfh = A[7:0]; + assign high_halfh = B[7:0]; + assign low_halfw = A[15:0]; + assign high_halfw = B[15:0]; + + assign Pack = {high_half, low_half}; + assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; + assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; + + always_comb + begin + if (PackSelect[1:0] == 2'b11) PackResult = PackH; + else if (PackSelect[2] == 1'b0) PackResult = Pack; + else PackResult = PackW; + end endmodule diff --git a/src/ieu/kmu/zknd_32.sv b/src/ieu/kmu/zknd_32.sv index 6ef6da9a9..2b36fe0df 100644 --- a/src/ieu/kmu/zknd_32.sv +++ b/src/ieu/kmu/zknd_32.sv @@ -36,8 +36,8 @@ module zknd_32 #(parameter WIDTH=32) logic [31:0] aes32dsmiRes; // RV32 - aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsiRes)); - aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsmiRes)); + aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsiRes)); + aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsmiRes)); mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult); diff --git a/src/ieu/kmu/zknd_64.sv b/src/ieu/kmu/zknd_64.sv index 69e190ad3..0bc4cf16a 100644 --- a/src/ieu/kmu/zknd_64.sv +++ b/src/ieu/kmu/zknd_64.sv @@ -40,9 +40,9 @@ module zknd_64 #(parameter WIDTH=32) logic [63:0] aes64ks2Res; // RV64 - aes64ds aes64ds (.rs1(A), .rs2(B), .data_out(aes64dsRes)); - aes64dsm aes64dsm (.rs1(A), .rs2(B), .data_out(aes64dsmRes)); - aes64im aes64im (.rs1(A), .data_out(aes64imRes)); + aes64ds aes64ds (.rs1(A), .rs2(B), .Data_Out(aes64dsRes)); + aes64dsm aes64dsm (.rs1(A), .rs2(B), .Data_Out(aes64dsmRes)); + aes64im aes64im (.rs1(A), .Data_Out(aes64imRes)); aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes)); aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res)); diff --git a/src/ieu/kmu/zkne_32.sv b/src/ieu/kmu/zkne_32.sv index c4ec0b78d..273453184 100644 --- a/src/ieu/kmu/zkne_32.sv +++ b/src/ieu/kmu/zkne_32.sv @@ -36,8 +36,8 @@ module zkne_32 #(parameter WIDTH=32) logic [31:0] aes32esmiRes; // RV32 - aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esiRes)); - aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esmiRes)); + aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esiRes)); + aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esmiRes)); mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult); diff --git a/src/ieu/kmu/zkne_64.sv b/src/ieu/kmu/zkne_64.sv index 84e45852f..1961f025e 100644 --- a/src/ieu/kmu/zkne_64.sv +++ b/src/ieu/kmu/zkne_64.sv @@ -39,8 +39,8 @@ module zkne_64 #(parameter WIDTH=32) logic [63:0] aes64ks2Res; // RV64 - aes64es aes64es (.rs1(A), .rs2(B), .data_out(aes64esRes)); - aes64esm aes64esm (.rs1(A), .rs2(B), .data_out(aes64esmRes)); + aes64es aes64es (.rs1(A), .rs2(B), .Data_Out(aes64esRes)); + aes64esm aes64esm (.rs1(A), .rs2(B), .Data_Out(aes64esmRes)); aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes)); aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res)); diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index ee6cd6900..3c702ffd5 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -58,6 +58,17 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b010010) name = "BCLRI"; else if (funct7[6:1] == 6'b011010) name = "BINVI"; else if (funct7[6:1] == 6'b001010) name = "BSETI"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP"; + else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM"; + else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1"; else if (funct7 == 7'b0110000) begin case (rs2) 5'b00000: name = "CLZ"; @@ -77,6 +88,8 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b011000) name = "RORI"; else if (funct7[6:1] == 6'b010010) name = "BEXTI"; else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B"; + else if (imm == 12'b011010000111) name = "BREV8"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP"; else name = "ILLEGAL"; 10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I"; else if (rd == 0 & rs2 == 1) name = "PREFETCH.R"; @@ -130,6 +143,21 @@ module instrNameDecTB( 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; else if (funct7 == 7'b0000001) name = "MUL"; else if (funct7 == 7'b0100000) name = "SUB"; + else if (funct7[4:0] == 5'b10101) name = "AES32DSI"; + else if (funct7[4:0] == 5'b10111) name = "AES32DSMI"; + else if (funct7 == 7'b0011101) name = "AES64DS"; + else if (funct7 == 7'b0011111) name = "AES64DSM"; + else if (funct7[4:0] == 5'b10001) name = "AES32ESI"; + else if (funct7[4:0] == 5'b10011) name = "AES32ESMI"; + else if (funct7 == 7'b0011001) name = "AES64ES"; + else if (funct7 == 7'b0011011) name = "AES64ESM"; + else if (funct7 == 7'b0111111) name = "AES64KS2"; + else if (funct7 == 7'b0101110) name = "SHA512SIG0H"; + else if (funct7 == 7'b0101010) name = "SHA512SIG0L"; + else if (funct7 == 7'b0101111) name = "SHA512SIG1H"; + else if (funct7 == 7'b0101011) name = "SHA512SIG1L"; + else if (funct7 == 7'b0101000) name = "SHA512SUM0R"; + else if (funct7 == 7'b0101001) name = "SHA512SUM1R"; else name = "ILLEGAL"; 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; else if (funct7 == 7'b0000001) name = "MULH"; @@ -153,7 +181,9 @@ module instrNameDecTB( else if (funct7 == 7'b0010000) name = "SH2ADD"; else if (funct7 == 7'b0000101) name = "MIN"; else if (funct7 == 7'b0100000) name = "ORN"; - else if (funct7 == 7'b0000100) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK"; + else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW"; else name = "ILLEGAL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; else if (funct7 == 7'b0000001) name = "DIVU"; diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index 44afbcd3b..68d0ff3ef 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -129,6 +129,12 @@ module testbench; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; "arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -159,6 +165,12 @@ module testbench; "arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb; "arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0f8194e62..036447341 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -147,6 +147,12 @@ module testbench; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; "buildroot": tests = buildroot; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -189,6 +195,12 @@ module testbench; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 95ebb74b3..fc04e9f7b 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -990,6 +990,53 @@ string imperas32f[] = '{ "rv32i_m/B/src/bseti-01.S" }; + string arch32zbkb[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/brev8_32-01.S", + "rv32i_m/K/src/pack-01.S", + "rv32i_m/K/src/packh-01.S", + "rv32i_m/K/src/unzip-01.S", + "rv32i_m/K/src/zip-01.S" + }; + + string arch32zbkc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S" + }; + + string arch32zbkx[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/xperm8-01.S", + "rv32i_m/K/src/xperm4-01.S" + }; + + string arch32zknd[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32dsi-01.S", + "rv32i_m/K/src/aes32dsmi-01.S" + }; + + string arch32zkne[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32esi-01.S", + "rv32i_m/K/src/aes32esmi-01.S" + }; + + string arch32zknh[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/sha256sig0-01.S", + "rv32i_m/K/src/sha256sig1-01.S", + "rv32i_m/K/src/sha256sum0-01.S", + "rv32i_m/K/src/sha256sum1-01.S", + "rv32i_m/K/src/sha512sig0h-01.S", + "rv32i_m/K/src/sha512sig0l-01.S", + "rv32i_m/K/src/sha512sig1h-01.S", + "rv32i_m/K/src/sha512sig1l-01.S", + "rv32i_m/K/src/sha512sum0r-01.S", + "rv32i_m/K/src/sha512sum1r-01.S" + }; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1748,6 +1795,55 @@ string arch64zbs[] = '{ "rv64i_m/B/src/bseti-01.S" }; +string arch64zbkb[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/brev8-01.S", + "rv64i_m/K/src/pack-01.S", + "rv64i_m/K/src/packh-01.S", + "rv64i_m/K/src/packw-01.S" +}; + +string arch64zbkc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S" +}; + +string arch64zbkx[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/xperm8-01.S", + "rv64i_m/K/src/xperm4-01.S" +}; + +string arch64zknd[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64ds-01.S", + "rv64i_m/K/src/aes64dsm-01.S", + "rv64i_m/K/src/aes64im-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zkne[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64es-01.S", + "rv64i_m/K/src/aes64esm-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zknh[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/sha256sig0-01.S", + "rv64i_m/K/src/sha256sig1-01.S", + "rv64i_m/K/src/sha256sum0-01.S", + "rv64i_m/K/src/sha256sum1-01.S", + "rv64i_m/K/src/sha512sig0-01.S", + "rv64i_m/K/src/sha512sig1-01.S", + "rv64i_m/K/src/sha512sum0-01.S", + "rv64i_m/K/src/sha512sum1-01.S" +}; + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 5450f64df..f5b8ea317 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -131,6 +131,18 @@ class spike(pluginTemplate): self.isa += '_Zbc' if "Zbs" in ispec["ISA"]: self.isa += '_Zbs' + if "Zbkb" in ispec["ISA"]: + self.isa += '_Zbkb' + if "Zbkc" in ispec["ISA"]: + self.isa += '_Zbkc' + if "Zknd" in ispec["ISA"]: + self.isa += '_Zknd' + if "Zkne" in ispec["ISA"]: + self.isa += '_Zkne' + if "Zbkx" in ispec["ISA"]: + self.isa += '_Zbkx' + if "Zknh" in ispec["ISA"]: + self.isa += '_Zknh' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml index 9e9775a9b..ee0aeec11 100644 --- a/tests/riscof/spike/spike_rv32e_isa.yaml +++ b/tests/riscof/spike/spike_rv32e_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32EMCZicsr_Zifencei + ISA: RV32EMCZicsr_Zifencei_Zbkc physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index d13420bba..1879440ed 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh # ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb physical_addr_sz: 32 diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index a40b579bd..6ee45513f 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -3,7 +3,7 @@ hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From 88d93b31b5014fcb6e347423f4c924081c5aa4bb Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Thu, 29 Feb 2024 12:51:42 -0600 Subject: [PATCH 24/47] Combined byteop and revop logic --- src/ieu/bmu/byteop.sv | 20 ++++++++++++++------ src/ieu/bmu/zbb.sv | 2 +- src/ieu/kmu/revop.sv | 44 ------------------------------------------- src/ieu/kmu/zbkb.sv | 6 +++--- 4 files changed, 18 insertions(+), 54 deletions(-) delete mode 100644 src/ieu/kmu/revop.sv diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 191919ecc..980c6d586 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // byteop.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 1 February 2023 -// Modified: 6 March 2023 +// Modified: 29 February 2024 // // Purpose: RISCV bitmanip byte-wise operation unit // @@ -12,7 +12,7 @@ // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -30,16 +30,24 @@ module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands - input logic ByteSelect, // LSB of Immediate + input logic [WIDTH-1:0] RevA, // Reversed A + input logic [1:0] ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result - logic [WIDTH-1:0] OrcBResult, Rev8Result; + logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result; genvar i; for (i=0;i Date: Thu, 29 Feb 2024 14:17:33 -0600 Subject: [PATCH 25/47] Combined ZBC and ZBKC into one unit --- sim/regression-wally | 2 +- src/ieu/bmu/bitmanipalu.sv | 12 +++------ src/ieu/bmu/bmuctrl.sv | 18 +++++++------ src/ieu/kmu/zbkc.sv | 55 -------------------------------------- 4 files changed, 14 insertions(+), 73 deletions(-) delete mode 100644 src/ieu/kmu/zbkc.sv diff --git a/sim/regression-wally b/sim/regression-wally index 1d12a04ec..d4fa2afdb 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -88,7 +88,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad", +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 373dbe437..e52cfcf94 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -88,8 +88,8 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( bitreverse #(P.XLEN) brA(.A(ABMU), .RevA); end - // ZBC Unit - if (P.ZBC_SUPPORTED) begin: zbc + // ZBC and ZBKCUnit + if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); end else assign ZBCResult = 0; @@ -102,11 +102,6 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( if (P.ZBKB_SUPPORTED) begin: zbkb zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); end else assign ZBKBResult = 0; - - // ZBKC Unit - if (P.ZBKC_SUPPORTED) begin: zbkc - zbkc #(P.XLEN) ZBKC(.A(ABMU), .B(BBMU), .ZBKCSelect(ZBBSelect[0]), .ZBKCResult); - end else assign ZBKCResult = 0; // ZBKX Unit if (P.ZBKX_SUPPORTED) begin: zbkx @@ -146,14 +141,13 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // Result Select Mux always_comb case (BSelect) - // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC, 0100: ZBKB, 0101: ZBKC, 0110: ZBKX + // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX // 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH... 4'b0000: ALUResult = PreALUResult; 4'b0001: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. 4'b0010: ALUResult = ZBBResult; 4'b0011: ALUResult = ZBCResult; 4'b0100: ALUResult = ZBKBResult; - 4'b0101: ALUResult = ZBKCResult; 4'b0110: ALUResult = ZBKXResult; 4'b0111: ALUResult = ZKNDResult; 4'b1000: ALUResult = ZKNEResult; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 19ed746b7..d7d6d9a7d 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -91,6 +91,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw endcase end + if (P.ZBB_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) @@ -119,10 +120,19 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction endcase end + if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction endcase + if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin // ZBKC + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul + 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh + endcase + end + if (P.ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr @@ -172,7 +182,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw endcase end - if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions casez({OpD, Funct7D, Funct3D}) 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol @@ -196,13 +205,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( endcase end - if (P.ZBKC_SUPPORTED) begin // ZBKC - casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0101_0000_1_0_0_1_0_0_0_0_0; // clmul - 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0101_0001_1_0_0_1_0_0_0_0_0; // clmulh - endcase - end - if (P.ZBKX_SUPPORTED) begin //ZBKX casez({OpD, Funct7D, Funct3D}) 17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8 diff --git a/src/ieu/kmu/zbkc.sv b/src/ieu/kmu/zbkc.sv deleted file mode 100644 index 66afe0e9a..000000000 --- a/src/ieu/kmu/zbkc.sv +++ /dev/null @@ -1,55 +0,0 @@ -/////////////////////////////////////////// -// zbkc.sv -// -// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu -// Created: 27 November 2023 -// -// Purpose: RISC-V ZBKC top level unit -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module zbkc #(parameter WIDTH=32) - (input logic [WIDTH-1:0] A, B, - input logic ZBKCSelect, - output logic [WIDTH-1:0] ZBKCResult); - - logic [WIDTH-1:0] temp, if_temp; - integer i; - - always_comb begin - temp = 0; - if (ZBKCSelect != 1'b0) begin // clmulh - for (i=1; i> i) & 1; - if(if_temp[0]) temp = temp ^ (A >> (WIDTH-i)); - else temp = temp; - end - end - else begin // clmul - for (i=0; i> i) & 1; - if(if_temp[0]) temp = temp ^ (A << i); - else temp = temp; - end - end - end - assign ZBKCResult = temp; - -endmodule From 9f53c54f57ad0de9ca1432a20b798a41e44263b4 Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Thu, 29 Feb 2024 14:50:15 -0600 Subject: [PATCH 26/47] Optimized Zbkx --- src/ieu/kmu/zbkx.sv | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv index 9d42dd372..7e3ed6ec3 100644 --- a/src/ieu/kmu/zbkx.sv +++ b/src/ieu/kmu/zbkx.sv @@ -30,21 +30,24 @@ module zbkx #(parameter WIDTH=32) input logic [2:0] ZBKXSelect, output logic [WIDTH-1:0] ZBKXResult); - logic [WIDTH-1:0] xperm_lookup[0:WIDTH]; + logic [WIDTH-1:0] xperm_lookup; logic [WIDTH-1:0] XPERM8_Result; logic [WIDTH-1:0] XPERM4_Result; - genvar i; + integer i; - for(i=0; i> {B[i+7:i], 3'b0}; - assign XPERM8_Result[i+7:i] = xperm_lookup[i][7:0]; + always_comb begin + if (ZBKXSelect[0] == 1'b0) begin + for(i=0; i> {B[i+:8], 3'b0}; + ZBKXResult[i+:8] = xperm_lookup[7:0]; + end + end + else begin + for(i=0; i> {B[i+:4], 2'b0}; + ZBKXResult[i+:4] = xperm_lookup[3:0]; + end + end end - for(i=0; i> {B[i+3:i], 2'b0}; - assign XPERM4_Result[i+3:i] = xperm_lookup[i+1][3:0]; - end - - mux2 #(WIDTH) ZbkxMux (XPERM8_Result, XPERM4_Result, ZBKXSelect[0], ZBKXResult); - endmodule From c110d0bb03680c38c5e7e2a3a52650758776ff42 Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Thu, 29 Feb 2024 14:51:02 -0600 Subject: [PATCH 27/47] Optimized Zbkx --- src/ieu/kmu/zbkx.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv index 7e3ed6ec3..cd22dd462 100644 --- a/src/ieu/kmu/zbkx.sv +++ b/src/ieu/kmu/zbkx.sv @@ -31,8 +31,6 @@ module zbkx #(parameter WIDTH=32) output logic [WIDTH-1:0] ZBKXResult); logic [WIDTH-1:0] xperm_lookup; - logic [WIDTH-1:0] XPERM8_Result; - logic [WIDTH-1:0] XPERM4_Result; integer i; always_comb begin From c163069484a4df5f043963bacea18c863faf2b9a Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Mon, 4 Mar 2024 15:23:11 -0600 Subject: [PATCH 28/47] Optimized mixcolumn --- src/ieu/aes_common/aes_inv_mixcols.sv | 51 ------------- src/ieu/aes_common/aes_inv_mixcolumns.sv | 4 +- src/ieu/aes_common/aes_inv_sbox.sv | 4 +- src/ieu/aes_common/aes_inv_sbox_128.sv | 40 ----------- src/ieu/aes_common/aes_inv_sbox_word.sv | 12 ++-- src/ieu/aes_common/aes_inv_shiftrow.sv | 45 +++--------- src/ieu/aes_common/aes_mixcolumns.sv | 61 ++++++---------- src/ieu/aes_common/aes_sbox.sv | 4 +- src/ieu/aes_common/aes_sbox_word.sv | 10 +-- src/ieu/aes_common/aes_shiftrow.sv | 45 ++---------- src/ieu/aes_common/aes_shiftword.sv | 59 --------------- .../{gm2.sv => galoismult_forward.sv} | 17 ++++- src/ieu/aes_common/mixword.sv | 72 ------------------- src/ieu/aes_common/rotateleft.sv | 34 --------- src/ieu/aes_instructions/aes32dsi.sv | 3 +- src/ieu/aes_instructions/aes32dsmi.sv | 5 +- src/ieu/aes_instructions/aes32esi.sv | 3 +- src/ieu/aes_instructions/aes32esmi.sv | 5 +- src/ieu/aes_instructions/aes64ds.sv | 6 +- src/ieu/aes_instructions/aes64dsm.sv | 10 +-- src/ieu/aes_instructions/aes64es.sv | 6 +- src/ieu/aes_instructions/aes64esm.sv | 10 +-- src/ieu/aes_instructions/aes64im.sv | 4 +- src/ieu/aes_instructions/aes64ks1i.sv | 14 ++-- src/ieu/aes_instructions/rcon_lut_128.sv | 2 +- src/ieu/aes_instructions/rrot8.sv | 63 ---------------- 26 files changed, 102 insertions(+), 487 deletions(-) delete mode 100644 src/ieu/aes_common/aes_inv_mixcols.sv delete mode 100644 src/ieu/aes_common/aes_inv_sbox_128.sv delete mode 100644 src/ieu/aes_common/aes_shiftword.sv rename src/ieu/aes_common/{gm2.sv => galoismult_forward.sv} (79%) delete mode 100644 src/ieu/aes_common/mixword.sv delete mode 100644 src/ieu/aes_common/rotateleft.sv delete mode 100644 src/ieu/aes_instructions/rrot8.sv diff --git a/src/ieu/aes_common/aes_inv_mixcols.sv b/src/ieu/aes_common/aes_inv_mixcols.sv deleted file mode 100644 index ad581748e..000000000 --- a/src/ieu/aes_common/aes_inv_mixcols.sv +++ /dev/null @@ -1,51 +0,0 @@ -/////////////////////////////////////////// -// aes_Inv_mixcols.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: AES Inverted Mix Column Function for use with AES -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module aes_Inv_mixcols (input logic [127:0] Data, output logic [127:0] Mixed_Col); - - // Declare Internal logic - logic [31:0] w0, w1, w2, w3; - logic [31:0] ws0, ws1, ws2, ws3; - - // Break up input Data into word components - assign w0 = Data[127:96]; - assign w1 = Data[95:64]; - assign w2 = Data[63:32]; - assign w3 = Data[31:0]; - - // Declare mixword components - inv_mixword mw_0(.word(w0), .mixed_word(ws0)); - inv_mixword mw_1(.word(w1), .mixed_word(ws1)); - inv_mixword mw_2(.word(w2), .mixed_word(ws2)); - inv_mixword mw_3(.word(w3), .mixed_word(ws3)); - - // Assign output to mixed word - assign Mixed_Col = {ws0, ws1, ws2, ws3}; - -endmodule // inv_mixcols - - diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index e9e910f9c..7588454aa 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_Inv_mixcolumns.sv +// aes_inv_mixcolumns.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module inv_mixword (input logic [31:0] word, output logic [31:0] mixed_word); +module aes_Inv_Mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); // Instantiate Internal Logic logic [7:0] b0, b1, b2, b3; diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index 3608dac92..fd24a39c5 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_Inv_sbox.sv +// aes_inv_sbox.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_sbox(input logic [7:0] in, +module aes_Inv_Sbox(input logic [7:0] in, output logic [7:0] out); always_comb diff --git a/src/ieu/aes_common/aes_inv_sbox_128.sv b/src/ieu/aes_common/aes_inv_sbox_128.sv deleted file mode 100644 index 577f37ef7..000000000 --- a/src/ieu/aes_common/aes_inv_sbox_128.sv +++ /dev/null @@ -1,40 +0,0 @@ -/////////////////////////////////////////// -// aes_Inv_sbox_128.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: 128-bit Inverse Substitution box comprised of 4x32-bit inverse s-boxes -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module aes_Inv_sbox_128(input logic [127:0] in, - output logic [127:0] out); - - // Declare the SBOX for (least significant) word 0 of the input - aes_Inv_sbox_word sbox_w0(.in(in[31:0]), .out(out[31:0])); - // Declare the SBOX for word 1 of the input - aes_Inv_sbox_word sbox_w1(.in(in[63:32]), .out(out[63:32])); - // Declare the SBOX for word 2 of the input - aes_Inv_sbox_word sbox_w2(.in(in[95:64]), .out(out[95:64])); - // Declare the SBOX for word 3 of the input - aes_Inv_sbox_word sbox_w3(.in(in[127:96]), .out(out[127:96])); - -endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index 42a91c7b6..a96771a07 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_Inv_sbox_word.sv +// aes_inv_sbox_word.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_sbox_word(input logic [31:0] in, +module aes_Inv_Sbox_Word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_Inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_Inv_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_Inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_Inv_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_Inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_Inv_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_Inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_Inv_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index be7f106b6..1ca9390d1 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_Inv_shiftrow.sv +// aes_inv_shiftrow.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,42 +25,13 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_shiftrow(input logic [127:0] DataIn, - output logic [127:0] DataOut); - - logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; - logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; - logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; - logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; - logic [31:0] out_w0, out_w1, out_w2, out_w3; +module aes_Inv_Shiftrow ( + input logic [127:0] DataIn, + output logic [127:0] DataOut); - // Separate the first (Least Significant) word into bytes - assign w0_b0 = DataIn[7:0]; - assign w0_b1 = DataIn[15:8]; - assign w0_b2 = DataIn[23:16]; - assign w0_b3 = DataIn[31:24]; - // Separate the second word into bytes - assign w1_b0 = DataIn[39:32]; - assign w1_b1 = DataIn[47:40]; - assign w1_b2 = DataIn[55:48]; - assign w1_b3 = DataIn[63:56]; - // Separate the third word into bytes - assign w2_b0 = DataIn[71:64]; - assign w2_b1 = DataIn[79:72]; - assign w2_b2 = DataIn[87:80]; - assign w2_b3 = DataIn[95:88]; - // Separate the fourth (Most significant) word into bytes - assign w3_b0 = DataIn[103:96]; - assign w3_b1 = DataIn[111:104]; - assign w3_b2 = DataIn[119:112]; - assign w3_b3 = DataIn[127:120]; - // The output words are composed of sets of the input bytes. - assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; - - assign DataOut = {out_w0, out_w1, out_w2, out_w3}; - + assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96], + DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64], + DataIn[95:88], DataIn[119:112], DataIn[15:8], DataIn[39:32], + DataIn[63:56], DataIn[87:80], DataIn[111:104], DataIn[7:0]}; endmodule diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index 07ba6cd1b..f1206a7a9 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// // aes_mixcolumns.sv // -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu // Created: 20 February 2024 // -// Purpose: AES "Mix Columns" Operation +// Purpose: Galois field operation to an individual 32-bit word // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -25,42 +25,27 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -/* - * Purpose : The "mix columns" operation is essentially composed of a - * nice little Galois field multiplication (of 1, 2 or 3) in the field - * x^8 + x^4 + x^3 + x + 1. - * The actual matrix you multiply by is - * [2 3 1 1][a_0,j] - * [1 2 3 1][a_1,j] - * [1 1 2 3][a_2,j] - * [3 1 1 2][a_3,j] - * - * Reference: secworks repo - */ -module aes_mixcolumns(Data, mixedcols); +module aes_Mixcolumns ( + input logic [31:0] in, + output logic [31:0] out); - // Declare Inputs/Outputs - input logic [127:0] Data; - output logic [127:0] mixedcols; + logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; + logic [15:0] rrot8_1, rrot8_2; + + assign {in0, in1, in2, in3} = in; + assign temp = in0 ^ in1 ^ in2 ^ in3; + + galoismult_forward gm0 (in0^in1, t0); + galoismult_forward gm1 (in1^in2, t1); + galoismult_forward gm2 (in2^in3, t2); + galoismult_forward gm3 (in3^in0, t3); + + assign out0 = in0 ^ temp ^ t3; + assign out1 = in1 ^ temp ^ t0; + assign out2 = in2 ^ temp ^ t1; + assign out3 = in3 ^ temp ^ t2; - // Declare internal Logic - logic [31:0] w0, w1, w2, w3; - logic [31:0] ws0, ws1, ws2, ws3; - - // Break up Data into individual words - assign w0 = Data[127:96]; - assign w1 = Data[95:64]; - assign w2 = Data[63:32]; - assign w3 = Data[31:0]; - - // Instantiate The mix words components for the words - mixword mw0(.word(w0), .mixed_word(ws0)); - mixword mw1(.word(w1), .mixed_word(ws1)); - mixword mw2(.word(w2), .mixed_word(ws2)); - mixword mw3(.word(w3), .mixed_word(ws3)); - - // Assign Output - assign mixedcols = {ws0, ws1, ws2, ws3}; - -endmodule // mixcolumns + assign out = {out0, out1, out2, out3}; + +endmodule diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv index 2b4491986..12e32dfd6 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aes_sbox.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_mixcolumns.sv +// aes_sbox.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox(input logic [7:0] in, +module aes_Sbox(input logic [7:0] in, output logic [7:0] out); // case statement to lookup the value in the rijndael table diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 17312585b..2111e4eb1 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox_word(input logic [31:0] in, +module aes_Sbox_Word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 0344d7e21..0de15f2ac 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -25,44 +25,13 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_shiftrow(input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_Shiftrow ( + input logic [127:0] DataIn, + output logic [127:0] DataOut); - // (This form of writing it may seem like more effort but I feel - // like it is more self-explanatory this way without losing efficiency) - - logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3; - logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3; - logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3; - logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3; - logic [31:0] out_w0, out_w1, out_w2, out_w3; - - // Seperate the first (Least Significant) word into bytes - assign w0_b0 = DataIn[7:0]; - assign w0_b1 = DataIn[79:72]; - assign w0_b2 = DataIn[23:16]; - assign w0_b3 = DataIn[95:88]; - // Seperate the second word into bytes - assign w1_b0 = DataIn[39:32]; - assign w1_b1 = DataIn[111:104]; - assign w1_b2 = DataIn[55:48]; - assign w1_b3 = DataIn[127:120]; - // Seperate the third word into bytes - assign w2_b0 = DataIn[71:64]; - assign w2_b1 = DataIn[15:8]; - assign w2_b2 = DataIn[87:80]; - assign w2_b3 = DataIn[31:24]; - // Seperate the fourth (Most significant) word into bytes - assign w3_b0 = DataIn[103:96]; - assign w3_b1 = DataIn[47:40]; - assign w3_b2 = DataIn[119:112]; - assign w3_b3 = DataIn[63:56]; - // The output words are composed of sets of the input bytes. - assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; - assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; - assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; - assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0}; - - assign DataOut = {out_w0, out_w1, out_w2, out_w3}; + assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], + DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64], + DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32], + DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]}; endmodule diff --git a/src/ieu/aes_common/aes_shiftword.sv b/src/ieu/aes_common/aes_shiftword.sv deleted file mode 100644 index c76e69d1f..000000000 --- a/src/ieu/aes_common/aes_shiftword.sv +++ /dev/null @@ -1,59 +0,0 @@ -/////////////////////////////////////////// -// aes_shiftword.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: AES Shiftrow shifting values -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -/* - Purpose : This next module provides an alternative way to shift the values. - in which it takes the shift number (essentially row number) as - an input and shifts cyclically to the left by that number of bits. - the complexity here is removed from the module and is more complex in - input selection. - */ - -module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] DataIn, - output logic [31:0] DataOut); - - - logic [7:0] b0 = DataIn[7:0]; - logic [7:0] b1 = DataIn[15:8]; - logic [7:0] b2 = DataIn[23:16]; - logic [7:0] b3 = DataIn[31:24]; - - always_comb - begin - case(shiftAmt) - // 00 : Barrel Shift no bytes - 2'b00 : DataOut = {b3, b2, b1, b0}; - // 01 : Barrel Shift one byte - 2'b01 : DataOut = {b0, b3, b2, b1}; - // 10 : Barrel Shift two bytes - 2'b10 : DataOut = {b1, b0, b3, b2}; - // 11 : Barrel Shift three bytes - default : DataOut = {b2, b1, b0, b3}; - endcase - end - -endmodule diff --git a/src/ieu/aes_common/gm2.sv b/src/ieu/aes_common/galoismult_forward.sv similarity index 79% rename from src/ieu/aes_common/gm2.sv rename to src/ieu/aes_common/galoismult_forward.sv index a9e675be5..3594aaedd 100644 --- a/src/ieu/aes_common/gm2.sv +++ b/src/ieu/aes_common/galoismult_forward.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// -// gm2.sv +// galoismult_forward.sv // -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu // Created: 20 February 2024 // // Purpose: Galois field operations for mix columns operation @@ -25,6 +25,17 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// +module galoismult_forward ( + input logic [7:0] in, + output logic [7:0] out); + + logic [7:0] leftshift; + + assign leftshift = {in[6:0], 1'b0}; + assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift; + +endmodule + module gm2 (gm2_In, gm2_Out); input logic [7:0] gm2_In; @@ -33,4 +44,4 @@ module gm2 (gm2_In, gm2_Out); // Set output to Galois Mult 2 assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); -endmodule +endmodule \ No newline at end of file diff --git a/src/ieu/aes_common/mixword.sv b/src/ieu/aes_common/mixword.sv deleted file mode 100644 index fdad29577..000000000 --- a/src/ieu/aes_common/mixword.sv +++ /dev/null @@ -1,72 +0,0 @@ -/////////////////////////////////////////// -// mixword.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operation to an individual 32-bit word -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module mixword (word, mixed_word); - - // Declare Inputs/Outputs - input logic [31:0] word; - output logic [31:0] mixed_word; - - // Declare Internal Signals - logic [7:0] b0, b1, b2, b3; - logic [7:0] mb0, mb1, mb2, mb3; - logic [7:0] gm2_0_Out; - logic [7:0] gm3_0_Out; - logic [7:0] gm2_1_Out; - logic [7:0] gm3_1_Out; - logic [7:0] gm2_2_Out; - logic [7:0] gm3_2_Out; - logic [7:0] gm2_3_Out; - logic [7:0] gm3_3_Out; - - // Break word into bytes - assign b0 = word[31:24]; - assign b1 = word[23:16]; - assign b2 = word[15:8]; - assign b3 = word[7:0]; - - // mb0 Galois components - gm2 gm2_0(.gm2_In(b0), .gm2_Out(gm2_0_Out)); - gm3 gm3_0(.gm3_In(b3), .gm3_Out(gm3_0_Out)); - // mb1 Galois components - gm2 gm2_1(.gm2_In(b1), .gm2_Out(gm2_1_Out)); - gm3 gm3_1(.gm3_In(b0), .gm3_Out(gm3_1_Out)); - // mb2 Galois components - gm2 gm2_2(.gm2_In(b2), .gm2_Out(gm2_2_Out)); - gm3 gm3_2(.gm3_In(b1), .gm3_Out(gm3_2_Out)); - // mb3 Galois components - gm2 gm2_3(.gm2_In(b3), .gm2_Out(gm2_3_Out)); - gm3 gm3_3(.gm3_In(b2), .gm3_Out(gm3_3_Out)); - - // Combine Componenets into mixed word - assign mb0 = gm2_0_Out ^ gm3_0_Out ^ b1 ^ b2; - assign mb1 = gm2_1_Out ^ gm3_1_Out ^ b2 ^ b3; - assign mb2 = gm2_2_Out ^ gm3_2_Out ^ b0 ^ b3; - assign mb3 = gm2_3_Out ^ gm3_3_Out ^ b0 ^ b1; - assign mixed_word = {mb0, mb1, mb2, mb3}; - -endmodule diff --git a/src/ieu/aes_common/rotateleft.sv b/src/ieu/aes_common/rotateleft.sv deleted file mode 100644 index 74862b47d..000000000 --- a/src/ieu/aes_common/rotateleft.sv +++ /dev/null @@ -1,34 +0,0 @@ -/////////////////////////////////////////// -// rotateleft.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: 32-bit left rotate for AES -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module rotate_left(input logic [31:0] Input_Data, - input logic [4:0] shamt, - output logic [31:0] Rot_Data); - - assign Rot_Data = (Input_Data << shamt) | (Input_Data >> (32 - shamt)); - -endmodule diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index 58fc88c51..ab52d1d96 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -46,13 +46,12 @@ module aes32dsi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_Sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; // Rotate the substitution box output left by shamt (bs * 8) - // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index df2bad83e..6374cab8c 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -47,16 +47,15 @@ module aes32dsmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Inv_Sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; // Run so through the mixword AES function - inv_mixword mix(.word(so), .mixed_word(mixed)); + aes_Inv_Mixcolumns mix(.word(so), .mixed_word(mixed)); // Rotate the substitution box output left by shamt (bs * 8) - // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index ed47e1d9d..c1adb4e93 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -48,13 +48,12 @@ module aes32esi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Sbox subbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output assign so = {24'h0, Sbox_Out}; // Rotate so left by shamt - // rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate)); assign so_rotate = (so << shamt) | (so >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 52d45c4de..53550c921 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -49,16 +49,15 @@ module aes32esmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_Sbox sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output assign so = {24'h0, Sbox_Out}; // Mix Word using aes_mixword component - mixword mwd(.word(so), .mixed_word(mixed)); + aes_Mixcolumns mwd(.in(so), .out(mixed)); // Rotate so left by shamt - // rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate)); assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index d1892675c..44f6717b8 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -35,11 +35,11 @@ module aes64ds(input logic [63:0] rs1, logic [31:0] Sbox_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_Inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_Inv_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_Sbox_Word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_Sbox_Word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Concatenate the two substitution outputs to get result assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 241d718e2..c9f538358 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,15 +37,15 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] Mixcol_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_Inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); + aes_Inv_Shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_Inv_Sbox_Word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_Inv_Sbox_Word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Apply inverse mixword to sbox outputs - inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); - inv_mixword inv_mw_1(.word(Sbox_Out_1), .mixed_word(Mixcol_Out_1)); + aes_Inv_Mixcolumns inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); + aes_Inv_Mixcolumns inv_mw_1(.word(Sbox_Out_1), .mixed_word(Mixcol_Out_1)); // Concatenate mixed words for output assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0}; diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 58e6dfdc0..363a1ab2c 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,9 +33,9 @@ module aes64es(input logic [63:0] rs1, logic [127:0] ShiftRow_Out; // AES shiftrow unit - aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); - aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); + aes_Sbox_Word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); + aes_Sbox_Word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 80c8f34d6..3b10df582 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,13 +34,13 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] Sbox_Out; // AES shiftrow unit - aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); - aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); + aes_Sbox_Word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); + aes_Sbox_Word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); // Apply mix columns operations - mixword mw0(.word(Sbox_Out[31:0]), .mixed_word(Data_Out[31:0])); - mixword mw1(.word(Sbox_Out[63:32]), .mixed_word(Data_Out[63:32])); + aes_Mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0])); + aes_Mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index 28aef331c..06c8c8ebf 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -28,6 +28,6 @@ module aes64im(input logic [63:0] rs1, output logic [63:0] Data_Out); - inv_mixword inv_mw_0(.word(rs1[31:0]), .mixed_word(Data_Out[31:0])); - inv_mixword inv_mw_1(.word(rs1[63:32]), .mixed_word(Data_Out[63:32])); + aes_Inv_Mixcolumns inv_mw_0(.word(rs1[31:0]), .mixed_word(Data_Out[31:0])); + aes_Inv_Mixcolumns inv_mw_1(.word(rs1[63:32]), .mixed_word(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 5ef76516c..0e5a08df6 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -38,23 +38,25 @@ module aes64ks1i(input logic [3:0] roundnum, logic [31:0] Sbox_Out; // Get rcon value from table - rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + rcon_Lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + // Shift RCON value assign rcon = {24'b0, rcon_preshift}; + // Flag will be set if roundnum = 0xA = 0b1010 assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0]; + // Get rotated value fo ruse in tmp2 - rrot8 rr(.x(rs1[63:32]), .result(rs1_rotate)); + assign rs1_rotate = {rs1[39:32], rs1[63:40]}; + // Assign tmp2 to a mux based on lastRoundFlag assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; + // Substitute bytes of value obtained for tmp2 using Rijndael sbox - aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out)); + aes_Sbox_Word sbox(.in(tmp2),.out(Sbox_Out)); assign rd[31:0] = Sbox_Out ^ rcon; assign rd[63:32] = Sbox_Out ^ rcon; - // There may be some errors with this instruction. - // Regression tests are passed successfully, but - // the algorithm seems wrong. Check later. endmodule diff --git a/src/ieu/aes_instructions/rcon_lut_128.sv b/src/ieu/aes_instructions/rcon_lut_128.sv index 89368408d..6103ea374 100644 --- a/src/ieu/aes_instructions/rcon_lut_128.sv +++ b/src/ieu/aes_instructions/rcon_lut_128.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rcon_lut_128(input logic [3:0] RD, +module rcon_Lut_128(input logic [3:0] RD, output logic [7:0] rcon_out); always_comb diff --git a/src/ieu/aes_instructions/rrot8.sv b/src/ieu/aes_instructions/rrot8.sv deleted file mode 100644 index 8f36f4317..000000000 --- a/src/ieu/aes_instructions/rrot8.sv +++ /dev/null @@ -1,63 +0,0 @@ -/////////////////////////////////////////// -// rrot8.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: aes64ks1i instruction -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module rrot8(input logic[31:0] x, - output logic [31:0] result); - - assign result[0] = x[8]; - assign result[1] = x[9]; - assign result[2] = x[10]; - assign result[3] = x[11]; - assign result[4] = x[12]; - assign result[5] = x[13]; - assign result[6] = x[14]; - assign result[7] = x[15]; - assign result[8] = x[16]; - assign result[9] = x[17]; - assign result[10] = x[18]; - assign result[11] = x[19]; - assign result[12] = x[20]; - assign result[13] = x[21]; - assign result[14] = x[22]; - assign result[15] = x[23]; - assign result[16] = x[24]; - assign result[17] = x[25]; - assign result[18] = x[26]; - assign result[19] = x[27]; - assign result[20] = x[28]; - assign result[21] = x[29]; - assign result[22] = x[30]; - assign result[23] = x[31]; - assign result[24] = x[0]; - assign result[25] = x[1]; - assign result[26] = x[2]; - assign result[27] = x[3]; - assign result[28] = x[4]; - assign result[29] = x[5]; - assign result[30] = x[6]; - assign result[31] = x[7]; -endmodule From e6ffde61bd9dfcc3d079fbf57c148d2d06b7fb28 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 08:54:50 -0600 Subject: [PATCH 29/47] fix module name to lc --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 2 +- src/ieu/aes_common/aes_inv_sbox.sv | 2 +- src/ieu/aes_common/aes_inv_sbox_word.sv | 10 +++++----- src/ieu/aes_common/aes_inv_shiftrow.sv | 5 ++--- src/ieu/aes_common/aes_mixcolumns.sv | 5 ++--- src/ieu/aes_common/aes_sbox.sv | 2 +- src/ieu/aes_common/aes_sbox_word.sv | 10 +++++----- src/ieu/aes_common/aes_shiftrow.sv | 6 +++--- 8 files changed, 20 insertions(+), 22 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index 7588454aa..670765349 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); +module aes_inv_mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); // Instantiate Internal Logic logic [7:0] b0, b1, b2, b3; diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index fd24a39c5..a364f75db 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Sbox(input logic [7:0] in, +module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out); always_comb diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index a96771a07..d2b18d7db 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Sbox_Word(input logic [31:0] in, +module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_Inv_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_Inv_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_Inv_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_Inv_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 1ca9390d1..3f04fa225 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -25,9 +25,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Shiftrow ( - input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_inv_shiftrow(input logic [127:0] DataIn, + output logic [127:0] DataOut); assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96], DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64], diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index f1206a7a9..72a610833 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -26,9 +26,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Mixcolumns ( - input logic [31:0] in, - output logic [31:0] out); +module aes_mixcolumns (input logic [31:0] in, + output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; logic [15:0] rrot8_1, rrot8_2; diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv index 12e32dfd6..29521b90e 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aes_sbox.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Sbox(input logic [7:0] in, +module aes_sbox(input logic [7:0] in, output logic [7:0] out); // case statement to lookup the value in the rijndael table diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 2111e4eb1..17312585b 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Sbox_Word(input logic [31:0] in, +module aes_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 0de15f2ac..991b49559 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -25,9 +25,9 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Shiftrow ( - input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_shiftrow + (input logic [127:0] DataIn, + output logic [127:0] DataOut); assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64], From 0d7ea36883698b7731e66c3248c491997e2b9a4e Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 08:56:24 -0600 Subject: [PATCH 30/47] fix module name to lc in aes_instructions --- src/ieu/aes_instructions/aes64ks1i.sv | 2 +- src/ieu/aes_instructions/rcon_lut_128.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 0e5a08df6..7336fcd10 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -38,7 +38,7 @@ module aes64ks1i(input logic [3:0] roundnum, logic [31:0] Sbox_Out; // Get rcon value from table - rcon_Lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); // Shift RCON value assign rcon = {24'b0, rcon_preshift}; diff --git a/src/ieu/aes_instructions/rcon_lut_128.sv b/src/ieu/aes_instructions/rcon_lut_128.sv index 6103ea374..89368408d 100644 --- a/src/ieu/aes_instructions/rcon_lut_128.sv +++ b/src/ieu/aes_instructions/rcon_lut_128.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rcon_Lut_128(input logic [3:0] RD, +module rcon_lut_128(input logic [3:0] RD, output logic [7:0] rcon_out); always_comb From 7bbc6413fbbd4dbb012e43696ad8d2ffaa68f80b Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 08:59:45 -0600 Subject: [PATCH 31/47] fix spacing in sha_instructions for style --- src/ieu/sha_instructions/sha256sig0.sv | 6 +++--- src/ieu/sha_instructions/sha512sig0.sv | 2 +- src/ieu/sha_instructions/sha512sig1.sv | 2 +- src/ieu/sha_instructions/sha512sum0.sv | 2 +- src/ieu/sha_instructions/sha512sum1.sv | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/ieu/sha_instructions/sha256sig0.sv b/src/ieu/sha_instructions/sha256sig0.sv index 069e99a29..58e476c53 100644 --- a/src/ieu/sha_instructions/sha256sig0.sv +++ b/src/ieu/sha_instructions/sha256sig0.sv @@ -25,9 +25,9 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha256sig0 #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] rs1, - output logic [WIDTH-1:0] result); +module sha256sig0 #(parameter WIDTH=32) + (input logic [WIDTH-1:0] rs1, + output logic [WIDTH-1:0] result); logic [31:0] ror7; logic [31:0] ror18; diff --git a/src/ieu/sha_instructions/sha512sig0.sv b/src/ieu/sha_instructions/sha512sig0.sv index 9f2cec04a..7f1df95da 100644 --- a/src/ieu/sha_instructions/sha512sig0.sv +++ b/src/ieu/sha_instructions/sha512sig0.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig0 (input logic [63:0] rs1, output logic [63:0] result); +module sha512sig0(input logic [63:0] rs1, output logic [63:0] result); logic [63:0] ror1; logic [63:0] ror8; diff --git a/src/ieu/sha_instructions/sha512sig1.sv b/src/ieu/sha_instructions/sha512sig1.sv index 1299df813..cc22b3fed 100644 --- a/src/ieu/sha_instructions/sha512sig1.sv +++ b/src/ieu/sha_instructions/sha512sig1.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig1 (input logic [63:0] rs1, output logic [63:0] result); +module sha512sig1(input logic [63:0] rs1, output logic [63:0] result); logic [63:0] ror19; logic [63:0] ror61; diff --git a/src/ieu/sha_instructions/sha512sum0.sv b/src/ieu/sha_instructions/sha512sum0.sv index dcd8c97d4..28edad516 100644 --- a/src/ieu/sha_instructions/sha512sum0.sv +++ b/src/ieu/sha_instructions/sha512sum0.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sum0 (input logic [63:0] rs1, output logic [63:0] result); +module sha512sum0(input logic [63:0] rs1, output logic [63:0] result); logic [63:0] ror28; logic [63:0] ror34; diff --git a/src/ieu/sha_instructions/sha512sum1.sv b/src/ieu/sha_instructions/sha512sum1.sv index 91c60ef7b..982d1dbdd 100644 --- a/src/ieu/sha_instructions/sha512sum1.sv +++ b/src/ieu/sha_instructions/sha512sum1.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sum1 (input logic [63:0] rs1, output logic [63:0] result); +module sha512sum1(input logic [63:0] rs1, output logic [63:0] result); logic [63:0] ror14; logic [63:0] ror18; From 5e247b9bf32386c4e5e45af800348d635e37206b Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 09:02:22 -0600 Subject: [PATCH 32/47] fix some spacing in aes_common --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 2 +- src/ieu/aes_common/aes_mixcolumns.sv | 4 ++-- src/ieu/aes_common/gm11.sv | 2 +- src/ieu/aes_common/gm13.sv | 2 +- src/ieu/aes_common/gm14.sv | 2 +- src/ieu/aes_common/gm3.sv | 2 +- src/ieu/aes_common/gm4.sv | 2 +- src/ieu/aes_common/gm8.sv | 2 +- src/ieu/aes_common/gm9.sv | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index 670765349..acb910637 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); +module aes_inv_mixcolumns(input logic [31:0] word, output logic [31:0] mixed_word); // Instantiate Internal Logic logic [7:0] b0, b1, b2, b3; diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index 72a610833..8a73e6253 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -26,8 +26,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_mixcolumns (input logic [31:0] in, - output logic [31:0] out); +module aes_mixcolumns(input logic [31:0] in, + output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; logic [15:0] rrot8_1, rrot8_2; diff --git a/src/ieu/aes_common/gm11.sv b/src/ieu/aes_common/gm11.sv index d5b22914b..aa9f96754 100644 --- a/src/ieu/aes_common/gm11.sv +++ b/src/ieu/aes_common/gm11.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm11 (gm11_In, gm11_Out); +module gm11(gm11_In, gm11_Out); input logic [7:0] gm11_In; output logic [7:0] gm11_Out; diff --git a/src/ieu/aes_common/gm13.sv b/src/ieu/aes_common/gm13.sv index 3fd7889b3..de4cf3911 100644 --- a/src/ieu/aes_common/gm13.sv +++ b/src/ieu/aes_common/gm13.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm13 (gm13_In, gm13_Out); +module gm13(gm13_In, gm13_Out); input logic [7:0] gm13_In; output logic [7:0] gm13_Out; diff --git a/src/ieu/aes_common/gm14.sv b/src/ieu/aes_common/gm14.sv index eab5bb8a2..1a8b77d93 100644 --- a/src/ieu/aes_common/gm14.sv +++ b/src/ieu/aes_common/gm14.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm14 (gm14_In, gm14_Out); +module gm14(gm14_In, gm14_Out); input logic [7:0] gm14_In; output logic [7:0] gm14_Out; diff --git a/src/ieu/aes_common/gm3.sv b/src/ieu/aes_common/gm3.sv index 886eb7115..009519f99 100644 --- a/src/ieu/aes_common/gm3.sv +++ b/src/ieu/aes_common/gm3.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm3 (gm3_In, gm3_Out); +module gm3(gm3_In, gm3_Out); input logic [7:0] gm3_In; output logic [7:0] gm3_Out; diff --git a/src/ieu/aes_common/gm4.sv b/src/ieu/aes_common/gm4.sv index 9a74d7189..f2e5a41e4 100644 --- a/src/ieu/aes_common/gm4.sv +++ b/src/ieu/aes_common/gm4.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm4 (gm4_In, gm4_Out); +module gm4(gm4_In, gm4_Out); input logic [7:0] gm4_In; output logic [7:0] gm4_Out; diff --git a/src/ieu/aes_common/gm8.sv b/src/ieu/aes_common/gm8.sv index 8fc228e4b..159022854 100644 --- a/src/ieu/aes_common/gm8.sv +++ b/src/ieu/aes_common/gm8.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm8 (gm8_In, gm8_Out); +module gm8(gm8_In, gm8_Out); input logic [7:0] gm8_In; output logic [7:0] gm8_Out; diff --git a/src/ieu/aes_common/gm9.sv b/src/ieu/aes_common/gm9.sv index 1e00d3cf6..c53f23e6f 100644 --- a/src/ieu/aes_common/gm9.sv +++ b/src/ieu/aes_common/gm9.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm9 (gm9_In, gm9_Out); +module gm9(gm9_In, gm9_Out); input logic [7:0] gm9_In; output logic [7:0] gm9_Out; From 5aab40a35fa583d0d939ebc7fe613a7bace57bab Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 09:06:48 -0600 Subject: [PATCH 33/47] Missed some style module declarations --- src/ieu/aes_common/aes_inv_sbox.sv | 3 +-- src/ieu/aes_common/aes_inv_sbox_word.sv | 3 +-- src/ieu/aes_common/aes_inv_shiftrow.sv | 3 +-- src/ieu/aes_common/aes_mixcolumns.sv | 3 +-- src/ieu/aes_common/aes_sbox.sv | 3 +-- src/ieu/aes_common/aes_sbox_word.sv | 3 +-- src/ieu/aes_common/aes_shiftrow.sv | 4 +--- src/ieu/aes_common/galoismult_forward.sv | 6 ++---- 8 files changed, 9 insertions(+), 19 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index a364f75db..a25fbf475 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox(input logic [7:0] in, - output logic [7:0] out); +module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out); always_comb begin diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index d2b18d7db..090b0b5b9 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox_word(input logic [31:0] in, - output logic [31:0] out); +module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 3f04fa225..67e92adf8 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_shiftrow(input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96], DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64], diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index 8a73e6253..f33a16880 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -26,8 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_mixcolumns(input logic [31:0] in, - output logic [31:0] out); +module aes_mixcolumns(input logic [31:0] in, output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; logic [15:0] rrot8_1, rrot8_2; diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv index 29521b90e..53f8bafe4 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aes_sbox.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox(input logic [7:0] in, - output logic [7:0] out); +module aes_sbox(input logic [7:0] in, output logic [7:0] out); // case statement to lookup the value in the rijndael table always_comb diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 17312585b..15fa9dec5 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox_word(input logic [31:0] in, - output logic [31:0] out); +module aes_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 991b49559..8c3e2b3c0 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -25,9 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_shiftrow - (input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64], diff --git a/src/ieu/aes_common/galoismult_forward.sv b/src/ieu/aes_common/galoismult_forward.sv index 3594aaedd..0779b0833 100644 --- a/src/ieu/aes_common/galoismult_forward.sv +++ b/src/ieu/aes_common/galoismult_forward.sv @@ -25,9 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module galoismult_forward ( - input logic [7:0] in, - output logic [7:0] out); +module galoismult_forward(input logic [7:0] in, output logic [7:0] out); logic [7:0] leftshift; @@ -44,4 +42,4 @@ module gm2 (gm2_In, gm2_Out); // Set output to Galois Mult 2 assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); -endmodule \ No newline at end of file +endmodule From 6894ee45884e8020f183385c1431059f58418f88 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 09:10:41 -0600 Subject: [PATCH 34/47] Separate gm2.sv to be separate module --- src/ieu/aes_common/galoismult_forward.sv | 10 ------- src/ieu/aes_common/gm2.sv | 36 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 10 deletions(-) create mode 100644 src/ieu/aes_common/gm2.sv diff --git a/src/ieu/aes_common/galoismult_forward.sv b/src/ieu/aes_common/galoismult_forward.sv index 0779b0833..ea6d8d011 100644 --- a/src/ieu/aes_common/galoismult_forward.sv +++ b/src/ieu/aes_common/galoismult_forward.sv @@ -33,13 +33,3 @@ module galoismult_forward(input logic [7:0] in, output logic [7:0] out); assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift; endmodule - -module gm2 (gm2_In, gm2_Out); - - input logic [7:0] gm2_In; - output logic [7:0] gm2_Out; - - // Set output to Galois Mult 2 - assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); - -endmodule diff --git a/src/ieu/aes_common/gm2.sv b/src/ieu/aes_common/gm2.sv new file mode 100644 index 000000000..527340337 --- /dev/null +++ b/src/ieu/aes_common/gm2.sv @@ -0,0 +1,36 @@ +/////////////////////////////////////////// +// gm2.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module gm2 (gm2_In, gm2_Out); + + input logic [7:0] gm2_In; + output logic [7:0] gm2_Out; + + // Set output to Galois Mult 2 + assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); + +endmodule From 5b445946b152cfd567cbe5fb0a457cd2aabd6131 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 09:14:22 -0600 Subject: [PATCH 35/47] style file slight mods for sha_instructions --- src/ieu/sha_instructions/sha512sig0h.sv | 3 +-- src/ieu/sha_instructions/sha512sig0l.sv | 3 +-- src/ieu/sha_instructions/sha512sig1h.sv | 3 +-- src/ieu/sha_instructions/sha512sig1l.sv | 3 +-- src/ieu/sha_instructions/sha512sum0r.sv | 3 +-- src/ieu/sha_instructions/sha512sum1r.sv | 3 +-- 6 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/ieu/sha_instructions/sha512sig0h.sv b/src/ieu/sha_instructions/sha512sig0h.sv index fb23c135a..a26ae0ef7 100644 --- a/src/ieu/sha_instructions/sha512sig0h.sv +++ b/src/ieu/sha_instructions/sha512sig0h.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig0h(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // RS1 Shifts diff --git a/src/ieu/sha_instructions/sha512sig0l.sv b/src/ieu/sha_instructions/sha512sig0l.sv index 3702b18bb..a12568fb5 100644 --- a/src/ieu/sha_instructions/sha512sig0l.sv +++ b/src/ieu/sha_instructions/sha512sig0l.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig0l(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // rs1 operations diff --git a/src/ieu/sha_instructions/sha512sig1h.sv b/src/ieu/sha_instructions/sha512sig1h.sv index 05fd66cd1..cce4b593b 100644 --- a/src/ieu/sha_instructions/sha512sig1h.sv +++ b/src/ieu/sha_instructions/sha512sig1h.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig1h(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // rs1 shifts diff --git a/src/ieu/sha_instructions/sha512sig1l.sv b/src/ieu/sha_instructions/sha512sig1l.sv index 570664a26..dae623091 100644 --- a/src/ieu/sha_instructions/sha512sig1l.sv +++ b/src/ieu/sha_instructions/sha512sig1l.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sig1l(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // rs1 shift logic diff --git a/src/ieu/sha_instructions/sha512sum0r.sv b/src/ieu/sha_instructions/sha512sum0r.sv index bee3b7551..e7ccf4e6e 100644 --- a/src/ieu/sha_instructions/sha512sum0r.sv +++ b/src/ieu/sha_instructions/sha512sum0r.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sum0r(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // RS1 shifts diff --git a/src/ieu/sha_instructions/sha512sum1r.sv b/src/ieu/sha_instructions/sha512sum1r.sv index 48428a69f..36ccbc1be 100644 --- a/src/ieu/sha_instructions/sha512sum1r.sv +++ b/src/ieu/sha_instructions/sha512sum1r.sv @@ -25,8 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module sha512sum1r(input logic [31:0] rs1, - input logic [31:0] rs2, +module sha512sum1r(input logic [31:0] rs1, input logic [31:0] rs2, output logic [31:0] data_out); // Declare logic for rs1 shifts From 00b61390d9c49565de7338cc25c4e1a9072a9b5b Mon Sep 17 00:00:00 2001 From: KelvinTr Date: Tue, 5 Mar 2024 14:56:24 -0600 Subject: [PATCH 36/47] Optimized Inverse Mixcolumn --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 62 +++++-------------- src/ieu/aes_common/aes_mixcolumns.sv | 1 - src/ieu/aes_common/galoismult_forward.sv | 2 +- .../{gm2.sv => galoismult_inverse.sv} | 22 +++---- src/ieu/aes_common/gm11.sv | 44 ------------- src/ieu/aes_common/gm13.sv | 44 ------------- src/ieu/aes_common/gm14.sv | 47 -------------- src/ieu/aes_common/gm3.sv | 42 ------------- src/ieu/aes_common/gm4.sv | 44 ------------- src/ieu/aes_common/gm8.sv | 44 ------------- src/ieu/aes_common/gm9.sv | 42 ------------- src/ieu/aes_instructions/aes32dsi.sv | 2 +- src/ieu/aes_instructions/aes32dsmi.sv | 4 +- src/ieu/aes_instructions/aes32esi.sv | 2 +- src/ieu/aes_instructions/aes32esmi.sv | 4 +- src/ieu/aes_instructions/aes64ds.sv | 6 +- src/ieu/aes_instructions/aes64dsm.sv | 10 +-- src/ieu/aes_instructions/aes64es.sv | 6 +- src/ieu/aes_instructions/aes64esm.sv | 10 +-- src/ieu/aes_instructions/aes64im.sv | 4 +- src/ieu/aes_instructions/aes64ks1i.sv | 2 +- 21 files changed, 53 insertions(+), 391 deletions(-) rename src/ieu/aes_common/{gm2.sv => galoismult_inverse.sv} (74%) delete mode 100644 src/ieu/aes_common/gm11.sv delete mode 100644 src/ieu/aes_common/gm13.sv delete mode 100644 src/ieu/aes_common/gm14.sv delete mode 100644 src/ieu/aes_common/gm3.sv delete mode 100644 src/ieu/aes_common/gm4.sv delete mode 100644 src/ieu/aes_common/gm8.sv delete mode 100644 src/ieu/aes_common/gm9.sv diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index acb910637..4338e3c32 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // aes_inv_mixcolumns.sv // -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 05 March 2024 // // Purpose: AES Inverted Mix Column Function for use with AES // @@ -25,52 +25,22 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_mixcolumns(input logic [31:0] word, output logic [31:0] mixed_word); +module aes_inv_mixcolumns(input logic [31:0] in, output logic [31:0] out); - // Instantiate Internal Logic - logic [7:0] b0, b1, b2, b3; - logic [7:0] mb0, mb1, mb2, mb3; + logic [7:0] in0, in1, in2, in3, temp; + logic [10:0] xor0, xor1, xor2, xor3; - logic [7:0] gm9_mb0, gm11_mb0, gm13_mb0, gm14_mb0; - logic [7:0] gm9_mb1, gm11_mb1, gm13_mb1, gm14_mb1; - logic [7:0] gm9_mb2, gm11_mb2, gm13_mb2, gm14_mb2; - logic [7:0] gm9_mb3, gm11_mb3, gm13_mb3, gm14_mb3; + assign {in0, in1, in2, in3} = in; + assign temp = in0 ^ in1 ^ in2 ^ in3; - // Break up word into 1 byte slices - assign b0 = word[31:24]; - assign b1 = word[23:16]; - assign b2 = word[15:8]; - assign b3 = word[7:0]; - - // mb0 Galois components - gm9 gm9_0(.gm9_In(b1), .gm9_Out(gm9_mb0)); - gm11 gm11_0(.gm11_In(b3), .gm11_Out(gm11_mb0)); - gm13 gm13_0(.gm13_In(b2), .gm13_Out(gm13_mb0)); - gm14 gm14_0(.gm14_In(b0), .gm14_Out(gm14_mb0)); + assign xor0 = {temp, 3'b0} ^ {1'b0, in3^in1, 2'b0} ^ {2'b0, in3^in2, 1'b0} ^ {3'b0, temp} ^ {3'b0, in3}; + assign xor1 = {temp, 3'b0} ^ {1'b0, in2^in0, 2'b0} ^ {2'b0, in2^in1, 1'b0} ^ {3'b0, temp} ^ {3'b0, in2}; + assign xor2 = {temp, 3'b0} ^ {1'b0, in1^in3, 2'b0} ^ {2'b0, in1^in0, 1'b0} ^ {3'b0, temp} ^ {3'b0, in1}; + assign xor3 = {temp, 3'b0} ^ {1'b0, in0^in2, 2'b0} ^ {2'b0, in0^in3, 1'b0} ^ {3'b0, temp} ^ {3'b0, in0}; - // mb1 Galois components - gm9 gm9_1(.gm9_In(b2), .gm9_Out(gm9_mb1)); - gm11 gm11_1(.gm11_In(b0), .gm11_Out(gm11_mb1)); - gm13 gm13_1(.gm13_In(b3), .gm13_Out(gm13_mb1)); - gm14 gm14_1(.gm14_In(b1), .gm14_Out(gm14_mb1)); - - // mb2 Galois components - gm9 gm9_2(.gm9_In(b3), .gm9_Out(gm9_mb2)); - gm11 gm11_2(.gm11_In(b1), .gm11_Out(gm11_mb2)); - gm13 gm13_2(.gm13_In(b0), .gm13_Out(gm13_mb2)); - gm14 gm14_2(.gm14_In(b2), .gm14_Out(gm14_mb2)); - - // mb3 Galois components - gm9 gm9_3(.gm9_In(b0), .gm9_Out(gm9_mb3)); - gm11 gm11_3(.gm11_In(b2), .gm11_Out(gm11_mb3)); - gm13 gm13_3(.gm13_In(b1), .gm13_Out(gm13_mb3)); - gm14 gm14_3(.gm14_In(b3), .gm14_Out(gm14_mb3)); + galoismult_inverse gm0 (xor0, out[7:0]); + galoismult_inverse gm1 (xor1, out[15:8]); + galoismult_inverse gm2 (xor2, out[23:16]); + galoismult_inverse gm3 (xor3, out[31:24]); - // XOR Galois components and assign output - assign mb0 = gm9_mb0 ^ gm11_mb0 ^ gm13_mb0 ^ gm14_mb0; - assign mb1 = gm9_mb1 ^ gm11_mb1 ^ gm13_mb1 ^ gm14_mb1; - assign mb2 = gm9_mb2 ^ gm11_mb2 ^ gm13_mb2 ^ gm14_mb2; - assign mb3 = gm9_mb3 ^ gm11_mb3 ^ gm13_mb3 ^ gm14_mb3; - assign mixed_word = {mb0, mb1, mb2, mb3}; - -endmodule // inv_mixword +endmodule \ No newline at end of file diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index f33a16880..54f0c4d14 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -29,7 +29,6 @@ module aes_mixcolumns(input logic [31:0] in, output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; - logic [15:0] rrot8_1, rrot8_2; assign {in0, in1, in2, in3} = in; assign temp = in0 ^ in1 ^ in2 ^ in3; diff --git a/src/ieu/aes_common/galoismult_forward.sv b/src/ieu/aes_common/galoismult_forward.sv index ea6d8d011..b7c855188 100644 --- a/src/ieu/aes_common/galoismult_forward.sv +++ b/src/ieu/aes_common/galoismult_forward.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module galoismult_forward(input logic [7:0] in, output logic [7:0] out); +module galoismult_forward(input logic [7:0] in, output logic [7:0] out); logic [7:0] leftshift; diff --git a/src/ieu/aes_common/gm2.sv b/src/ieu/aes_common/galoismult_inverse.sv similarity index 74% rename from src/ieu/aes_common/gm2.sv rename to src/ieu/aes_common/galoismult_inverse.sv index 527340337..fda3bbcb9 100644 --- a/src/ieu/aes_common/gm2.sv +++ b/src/ieu/aes_common/galoismult_inverse.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// -// gm2.sv +// galoismult_inverse.sv // -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // // Purpose: Galois field operations for mix columns operation @@ -25,12 +25,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gm2 (gm2_In, gm2_Out); - - input logic [7:0] gm2_In; - output logic [7:0] gm2_Out; - - // Set output to Galois Mult 2 - assign gm2_Out = {gm2_In[6:0], 1'b0} ^ (8'h1b & {8{gm2_In[7]}}); - -endmodule +module galoismult_inverse(input logic [10:0] in, output logic [7:0] out); + + logic [7:0] temp0, temp1; + + assign temp0 = in[8] ? (in[7:0] ^ 8'b00011011) : in[7:0]; + assign temp1 = in[9] ? (temp0 ^ 8'b00110110) : temp0; + assign out = in[10] ? (temp1 ^ 8'b01101100) : temp1; + +endmodule diff --git a/src/ieu/aes_common/gm11.sv b/src/ieu/aes_common/gm11.sv deleted file mode 100644 index aa9f96754..000000000 --- a/src/ieu/aes_common/gm11.sv +++ /dev/null @@ -1,44 +0,0 @@ -/////////////////////////////////////////// -// gm11.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm11(gm11_In, gm11_Out); - - input logic [7:0] gm11_In; - output logic [7:0] gm11_Out; - - // Internal Logic - logic [7:0] gm8_0_Out; - logic [7:0] gm2_0_Out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_In(gm11_In), .gm8_Out(gm8_0_Out)); - gm2 gm2_0 (.gm2_In(gm11_In), .gm2_Out(gm2_0_Out)); - - // Set output to gm8(in) ^ gm2(in) ^ in - assign gm11_Out = gm8_0_Out ^ gm2_0_Out ^ gm11_In; - -endmodule diff --git a/src/ieu/aes_common/gm13.sv b/src/ieu/aes_common/gm13.sv deleted file mode 100644 index de4cf3911..000000000 --- a/src/ieu/aes_common/gm13.sv +++ /dev/null @@ -1,44 +0,0 @@ -/////////////////////////////////////////// -// gm13.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm13(gm13_In, gm13_Out); - - input logic [7:0] gm13_In; - output logic [7:0] gm13_Out; - - // Internal Logic - logic [7:0] gm8_0_Out; - logic [7:0] gm4_0_Out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_In(gm13_In), .gm8_Out(gm8_0_Out)); - gm4 gm4_0 (.gm4_In(gm13_In), .gm4_Out(gm4_0_Out)); - - // Set output to gm8(in) ^ gm4(in) ^ in - assign gm13_Out = gm8_0_Out ^ gm4_0_Out ^ gm13_In; - -endmodule diff --git a/src/ieu/aes_common/gm14.sv b/src/ieu/aes_common/gm14.sv deleted file mode 100644 index 1a8b77d93..000000000 --- a/src/ieu/aes_common/gm14.sv +++ /dev/null @@ -1,47 +0,0 @@ -/////////////////////////////////////////// -// gm14.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm14(gm14_In, gm14_Out); - - input logic [7:0] gm14_In; - output logic [7:0] gm14_Out; - - // Internal Logic - logic [7:0] gm8_0_Out; - logic [7:0] gm4_0_Out; - logic [7:0] gm2_0_Out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_In(gm14_In), .gm8_Out(gm8_0_Out)); - gm4 gm4_0 (.gm4_In(gm14_In), .gm4_Out(gm4_0_Out)); - gm2 gm2_0 (.gm2_In(gm14_In), .gm2_Out(gm2_0_Out)); - - //Assign output to gm8(in) ^ gm4(in) ^ gm2(in) - assign gm14_Out = gm8_0_Out ^ gm4_0_Out ^ gm2_0_Out; - -endmodule - diff --git a/src/ieu/aes_common/gm3.sv b/src/ieu/aes_common/gm3.sv deleted file mode 100644 index 009519f99..000000000 --- a/src/ieu/aes_common/gm3.sv +++ /dev/null @@ -1,42 +0,0 @@ -/////////////////////////////////////////// -// gm3.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm3(gm3_In, gm3_Out); - - input logic [7:0] gm3_In; - output logic [7:0] gm3_Out; - - // Internal Logic - logic [7:0] gm2_0_Out; - - // Sub-Modules for gm2 multiplication - gm2 gm2_0 (.gm2_In(gm3_In), .gm2_Out(gm2_0_Out)); - - // Assign Output - assign gm3_Out = gm2_0_Out ^ gm3_In; - -endmodule diff --git a/src/ieu/aes_common/gm4.sv b/src/ieu/aes_common/gm4.sv deleted file mode 100644 index f2e5a41e4..000000000 --- a/src/ieu/aes_common/gm4.sv +++ /dev/null @@ -1,44 +0,0 @@ -/////////////////////////////////////////// -// gm4.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm4(gm4_In, gm4_Out); - - input logic [7:0] gm4_In; - output logic [7:0] gm4_Out; - - // Internal Logic - logic [7:0] gm2_0_Out; - logic [7:0] gm2_1_Out; - - // Sub-Modules for multiple gm2 multiplications - gm2 gm2_0 (.gm2_In(gm4_In), .gm2_Out(gm2_0_Out)); - gm2 gm2_1 (.gm2_In(gm2_0_Out), .gm2_Out(gm2_1_Out)); - - // Assign output to second gm2 output - assign gm4_Out = gm2_1_Out; - -endmodule diff --git a/src/ieu/aes_common/gm8.sv b/src/ieu/aes_common/gm8.sv deleted file mode 100644 index 159022854..000000000 --- a/src/ieu/aes_common/gm8.sv +++ /dev/null @@ -1,44 +0,0 @@ -/////////////////////////////////////////// -// gm8.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm8(gm8_In, gm8_Out); - - input logic [7:0] gm8_In; - output logic [7:0] gm8_Out; - - // Internal Logic - logic [7:0] gm2_0_Out; - logic [7:0] gm4_0_Out; - - // Sub-Modules for sub-Galois operations - gm4 gm4_0 (.gm4_In(gm8_In), .gm4_Out(gm4_0_Out)); - gm2 gm2_0 (.gm2_In(gm4_0_Out), .gm2_Out(gm2_0_Out)); - - // Assign output to gm2 output - assign gm8_Out = gm2_0_Out; - -endmodule diff --git a/src/ieu/aes_common/gm9.sv b/src/ieu/aes_common/gm9.sv deleted file mode 100644 index c53f23e6f..000000000 --- a/src/ieu/aes_common/gm9.sv +++ /dev/null @@ -1,42 +0,0 @@ -/////////////////////////////////////////// -// gm9.sv -// -// Written: ryan.swann@okstate.edu, james.stine@okstate.edu -// Created: 20 February 2024 -// -// Purpose: Galois field operations for mix columns operation -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module gm9(gm9_In, gm9_Out); - - input logic [7:0] gm9_In; - output logic [7:0] gm9_Out; - - // Internal Logic - logic [7:0] gm8_0_Out; - - // Sub-Modules for sub-Galois operations - gm8 gm8_0 (.gm8_In(gm9_In), .gm8_Out(gm8_0_Out)); - - // Set output to gm8(in) ^ in - assign gm9_Out = gm8_0_Out ^ gm9_In; - -endmodule diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index ab52d1d96..b54a68d27 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -46,7 +46,7 @@ module aes32dsi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_Inv_Sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index 6374cab8c..dcb8d327b 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -47,13 +47,13 @@ module aes32dsmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Apply inverse sbox to si - aes_Inv_Sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad output of inverse substitution box assign so = {24'h0, Sbox_Out}; // Run so through the mixword AES function - aes_Inv_Mixcolumns mix(.word(so), .mixed_word(mixed)); + aes_inv_mixcolumns mix(.in(so), .out(mixed)); // Rotate the substitution box output left by shamt (bs * 8) assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index c1adb4e93..1d54de585 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -48,7 +48,7 @@ module aes32esi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_Sbox subbox(.in(Sbox_In), .out(Sbox_Out)); + aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output assign so = {24'h0, Sbox_Out}; diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 53550c921..88277a37d 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -49,13 +49,13 @@ module aes32esmi(input logic [1:0] bs, assign Sbox_In = Sbox_In_32[7:0]; // Substitute - aes_Sbox sbox(.in(Sbox_In), .out(Sbox_Out)); + aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out)); // Pad sbox output assign so = {24'h0, Sbox_Out}; // Mix Word using aes_mixword component - aes_Mixcolumns mwd(.in(so), .out(mixed)); + aes_mixcolumns mwd(.in(so), .out(mixed)); // Rotate so left by shamt assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index 44f6717b8..275d5b43c 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -35,11 +35,11 @@ module aes64ds(input logic [63:0] rs1, logic [31:0] Sbox_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_Inv_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_Inv_Sbox_Word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_Inv_Sbox_Word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Concatenate the two substitution outputs to get result assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index c9f538358..4695d42cc 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -37,15 +37,15 @@ module aes64dsm(input logic [63:0] rs1, logic [31:0] Mixcol_Out_1; // Apply inverse shiftrows to rs2 and rs1 - aes_Inv_Shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); + aes_inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_Inv_Sbox_Word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_Inv_Sbox_Word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); + aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); // Apply inverse mixword to sbox outputs - aes_Inv_Mixcolumns inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0)); - aes_Inv_Mixcolumns inv_mw_1(.word(Sbox_Out_1), .mixed_word(Mixcol_Out_1)); + aes_inv_mixcolumns inv_mw_0(.in(Sbox_Out_0), .out(Mixcol_Out_0)); + aes_inv_mixcolumns inv_mw_1(.in(Sbox_Out_1), .out(Mixcol_Out_1)); // Concatenate mixed words for output assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0}; diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 363a1ab2c..58e6dfdc0 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -33,9 +33,9 @@ module aes64es(input logic [63:0] rs1, logic [127:0] ShiftRow_Out; // AES shiftrow unit - aes_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_Sbox_Word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); - aes_Sbox_Word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); + aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); + aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 3b10df582..0e3fd0d56 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -34,13 +34,13 @@ module aes64esm(input logic [63:0] rs1, logic [63:0] Sbox_Out; // AES shiftrow unit - aes_Shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); // Apply substitution box to 2 lower words - aes_Sbox_Word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); - aes_Sbox_Word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); + aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); + aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); // Apply mix columns operations - aes_Mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0])); - aes_Mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32])); + aes_mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0])); + aes_mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index 06c8c8ebf..d4b7f12bb 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -28,6 +28,6 @@ module aes64im(input logic [63:0] rs1, output logic [63:0] Data_Out); - aes_Inv_Mixcolumns inv_mw_0(.word(rs1[31:0]), .mixed_word(Data_Out[31:0])); - aes_Inv_Mixcolumns inv_mw_1(.word(rs1[63:32]), .mixed_word(Data_Out[63:32])); + aes_inv_mixcolumns inv_mw_0(.in(rs1[31:0]), .out(Data_Out[31:0])); + aes_inv_mixcolumns inv_mw_1(.in(rs1[63:32]), .out(Data_Out[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index 7336fcd10..a8b44c3e5 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -53,7 +53,7 @@ module aes64ks1i(input logic [3:0] roundnum, assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; // Substitute bytes of value obtained for tmp2 using Rijndael sbox - aes_Sbox_Word sbox(.in(tmp2),.out(Sbox_Out)); + aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out)); assign rd[31:0] = Sbox_Out ^ rcon; assign rd[63:32] = Sbox_Out ^ rcon; From 8821386fe5b8b0d32a60f95694ef2d6aa9476a9e Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 13:06:36 -0600 Subject: [PATCH 37/47] update removal of underscores from aes_common --- .../{aes_inv_mixcolumns.sv => aesinvmixcolumns.sv} | 14 +++++++------- .../aes_common/{aes_inv_sbox.sv => aesinvsbox.sv} | 4 ++-- .../{aes_inv_sbox_word.sv => aesinvsboxword.sv} | 12 ++++++------ .../{aes_inv_shiftrow.sv => aesinvshiftrow.sv} | 4 ++-- .../{aes_mixcolumns.sv => aesmixcolumns.sv} | 12 ++++++------ src/ieu/aes_common/{aes_sbox.sv => aessbox.sv} | 4 ++-- .../{aes_sbox_word.sv => aessboxword.sv} | 12 ++++++------ .../aes_common/{aes_shiftrow.sv => aesshiftrow.sv} | 4 ++-- ...{galoismult_forward.sv => galoismultforward.sv} | 4 ++-- ...{galoismult_inverse.sv => galoismultinverse.sv} | 4 ++-- 10 files changed, 37 insertions(+), 37 deletions(-) rename src/ieu/aes_common/{aes_inv_mixcolumns.sv => aesinvmixcolumns.sv} (85%) rename src/ieu/aes_common/{aes_inv_sbox.sv => aesinvsbox.sv} (98%) rename src/ieu/aes_common/{aes_inv_sbox_word.sv => aesinvsboxword.sv} (80%) rename src/ieu/aes_common/{aes_inv_shiftrow.sv => aesinvshiftrow.sv} (93%) rename src/ieu/aes_common/{aes_mixcolumns.sv => aesmixcolumns.sv} (85%) rename src/ieu/aes_common/{aes_sbox.sv => aessbox.sv} (98%) rename src/ieu/aes_common/{aes_sbox_word.sv => aessboxword.sv} (81%) rename src/ieu/aes_common/{aes_shiftrow.sv => aesshiftrow.sv} (93%) rename src/ieu/aes_common/{galoismult_forward.sv => galoismultforward.sv} (93%) rename src/ieu/aes_common/{galoismult_inverse.sv => galoismultinverse.sv} (93%) diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aesinvmixcolumns.sv similarity index 85% rename from src/ieu/aes_common/aes_inv_mixcolumns.sv rename to src/ieu/aes_common/aesinvmixcolumns.sv index 4338e3c32..52ac6beb9 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aesinvmixcolumns.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_mixcolumns.sv +// aesinvmixcolumns.sv // // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 05 March 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_mixcolumns(input logic [31:0] in, output logic [31:0] out); +module aesinvmixcolumns(input logic [31:0] in, output logic [31:0] out); logic [7:0] in0, in1, in2, in3, temp; logic [10:0] xor0, xor1, xor2, xor3; @@ -38,9 +38,9 @@ module aes_inv_mixcolumns(input logic [31:0] in, output logic [31:0] out); assign xor2 = {temp, 3'b0} ^ {1'b0, in1^in3, 2'b0} ^ {2'b0, in1^in0, 1'b0} ^ {3'b0, temp} ^ {3'b0, in1}; assign xor3 = {temp, 3'b0} ^ {1'b0, in0^in2, 2'b0} ^ {2'b0, in0^in3, 1'b0} ^ {3'b0, temp} ^ {3'b0, in0}; - galoismult_inverse gm0 (xor0, out[7:0]); - galoismult_inverse gm1 (xor1, out[15:8]); - galoismult_inverse gm2 (xor2, out[23:16]); - galoismult_inverse gm3 (xor3, out[31:24]); + galoismultinverse gm0 (xor0, out[7:0]); + galoismultinverse gm1 (xor1, out[15:8]); + galoismultinverse gm2 (xor2, out[23:16]); + galoismultinverse gm3 (xor3, out[31:24]); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aesinvsbox.sv similarity index 98% rename from src/ieu/aes_common/aes_inv_sbox.sv rename to src/ieu/aes_common/aesinvsbox.sv index a25fbf475..0c8b4c200 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aesinvsbox.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox.sv +// aesinvsbox.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out); +module aesinvsbox(input logic [7:0] in, output logic [7:0] out); always_comb begin diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aesinvsboxword.sv similarity index 80% rename from src/ieu/aes_common/aes_inv_sbox_word.sv rename to src/ieu/aes_common/aesinvsboxword.sv index 090b0b5b9..7baa03d21 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aesinvsboxword.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_sbox_word.sv +// aesinvsboxword.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,15 +25,15 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out); +module aesinvsboxword(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aesinvsbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aesinvsbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aesinvsbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aesinvsbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aesinvshiftrow.sv similarity index 93% rename from src/ieu/aes_common/aes_inv_shiftrow.sv rename to src/ieu/aes_common/aesinvshiftrow.sv index 67e92adf8..495ad8c71 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aesinvshiftrow.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_inv_shiftrow.sv +// aesinvshiftrow.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); +module aesinvshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96], DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64], diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aesmixcolumns.sv similarity index 85% rename from src/ieu/aes_common/aes_mixcolumns.sv rename to src/ieu/aes_common/aesmixcolumns.sv index 54f0c4d14..6a5c076fa 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aesmixcolumns.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_mixcolumns.sv +// aesmixcolumns.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu // Created: 20 February 2024 @@ -26,17 +26,17 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_mixcolumns(input logic [31:0] in, output logic [31:0] out); +module aesmixcolumns(input logic [31:0] in, output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; assign {in0, in1, in2, in3} = in; assign temp = in0 ^ in1 ^ in2 ^ in3; - galoismult_forward gm0 (in0^in1, t0); - galoismult_forward gm1 (in1^in2, t1); - galoismult_forward gm2 (in2^in3, t2); - galoismult_forward gm3 (in3^in0, t3); + galoismultforward gm0 (in0^in1, t0); + galoismultforward gm1 (in1^in2, t1); + galoismultforward gm2 (in2^in3, t2); + galoismultforward gm3 (in3^in0, t3); assign out0 = in0 ^ temp ^ t3; assign out1 = in1 ^ temp ^ t0; diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aessbox.sv similarity index 98% rename from src/ieu/aes_common/aes_sbox.sv rename to src/ieu/aes_common/aessbox.sv index 53f8bafe4..6b6e04918 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aessbox.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_sbox.sv +// aessbox.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox(input logic [7:0] in, output logic [7:0] out); +module aessbox(input logic [7:0] in, output logic [7:0] out); // case statement to lookup the value in the rijndael table always_comb diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aessboxword.sv similarity index 81% rename from src/ieu/aes_common/aes_sbox_word.sv rename to src/ieu/aes_common/aessboxword.sv index 15fa9dec5..2a72b19b1 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aessboxword.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_sbox_word.sv +// aessboxword.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,15 +25,15 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_sbox_word(input logic [31:0] in, output logic [31:0] out); +module aessboxword(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aessbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aessbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aessbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aessbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aesshiftrow.sv similarity index 93% rename from src/ieu/aes_common/aes_shiftrow.sv rename to src/ieu/aes_common/aesshiftrow.sv index 8c3e2b3c0..57ed86670 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aesshiftrow.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// aes_shiftrow.sv +// aesshiftrow.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); +module aesshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64], diff --git a/src/ieu/aes_common/galoismult_forward.sv b/src/ieu/aes_common/galoismultforward.sv similarity index 93% rename from src/ieu/aes_common/galoismult_forward.sv rename to src/ieu/aes_common/galoismultforward.sv index b7c855188..1dcfcd56f 100644 --- a/src/ieu/aes_common/galoismult_forward.sv +++ b/src/ieu/aes_common/galoismultforward.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// galoismult_forward.sv +// galoismultforward.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module galoismult_forward(input logic [7:0] in, output logic [7:0] out); +module galoismultforward(input logic [7:0] in, output logic [7:0] out); logic [7:0] leftshift; diff --git a/src/ieu/aes_common/galoismult_inverse.sv b/src/ieu/aes_common/galoismultinverse.sv similarity index 93% rename from src/ieu/aes_common/galoismult_inverse.sv rename to src/ieu/aes_common/galoismultinverse.sv index fda3bbcb9..08be6588a 100644 --- a/src/ieu/aes_common/galoismult_inverse.sv +++ b/src/ieu/aes_common/galoismultinverse.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// galoismult_inverse.sv +// galoismultinverse.sv // // Written: kelvin.tran@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module galoismult_inverse(input logic [10:0] in, output logic [7:0] out); +module galoismultinverse(input logic [10:0] in, output logic [7:0] out); logic [7:0] temp0, temp1; From 08c7ddd61d6ebd7334801e781e1032efacf44175 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 13:28:47 -0600 Subject: [PATCH 38/47] update removal of underscores from aes_instructions --- src/ieu/aes_instructions/aes32dsi.sv | 22 +++++++------- src/ieu/aes_instructions/aes32dsmi.sv | 24 +++++++-------- src/ieu/aes_instructions/aes32esi.sv | 22 +++++++------- src/ieu/aes_instructions/aes32esmi.sv | 26 ++++++++-------- src/ieu/aes_instructions/aes64ds.sv | 16 +++++----- src/ieu/aes_instructions/aes64dsm.sv | 24 +++++++-------- src/ieu/aes_instructions/aes64es.sv | 10 +++---- src/ieu/aes_instructions/aes64esm.sv | 16 +++++----- src/ieu/aes_instructions/aes64im.sv | 6 ++-- src/ieu/aes_instructions/aes64ks1i.sv | 22 +++++++------- .../{rcon_lut_128.sv => rconlut128.sv} | 30 +++++++++---------- 11 files changed, 108 insertions(+), 110 deletions(-) rename src/ieu/aes_instructions/{rcon_lut_128.sv => rconlut128.sv} (73%) diff --git a/src/ieu/aes_instructions/aes32dsi.sv b/src/ieu/aes_instructions/aes32dsi.sv index b54a68d27..edb83c0ee 100644 --- a/src/ieu/aes_instructions/aes32dsi.sv +++ b/src/ieu/aes_instructions/aes32dsi.sv @@ -28,32 +28,32 @@ module aes32dsi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] Data_Out); + output logic [31:0] DataOut); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] Sbox_In_32; - logic [7:0] Sbox_In; - logic [7:0] Sbox_Out; + logic [31:0] SboxIn32; + logic [7:0] SboxIn; + logic [7:0] SboxOut; logic [31:0] so; - logic [31:0] so_rotate; + logic [31:0] sorotate; // shamt = bs * 8 assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt and take the lower byte - assign Sbox_In_32 = (rs2 >> shamt); - assign Sbox_In = Sbox_In_32[7:0]; + assign SboxIn32 = (rs2 >> shamt); + assign SboxIn = SboxIn32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut)); // Pad output of inverse substitution box - assign so = {24'h0, Sbox_Out}; + assign so = {24'h0, SboxOut}; // Rotate the substitution box output left by shamt (bs * 8) - assign so_rotate = (so << shamt) | (so >> (32 - shamt)); + assign sorotate = (so << shamt) | (so >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" - assign Data_Out = rs1 ^ so_rotate; + assign DataOut = rs1 ^ sorotate; endmodule diff --git a/src/ieu/aes_instructions/aes32dsmi.sv b/src/ieu/aes_instructions/aes32dsmi.sv index dcb8d327b..c3798658a 100644 --- a/src/ieu/aes_instructions/aes32dsmi.sv +++ b/src/ieu/aes_instructions/aes32dsmi.sv @@ -28,36 +28,36 @@ module aes32dsmi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] Data_Out); + output logic [31:0] DataOut); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] Sbox_In_32; - logic [7:0] Sbox_In; - logic [7:0] Sbox_Out; + logic [31:0] SboxIn32; + logic [7:0] SboxIn; + logic [7:0] SboxOut; logic [31:0] so; logic [31:0] mixed; - logic [31:0] mixed_rotate; + logic [31:0] mixedrotate; // shamt = bs * 8 assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt and take the lower byte - assign Sbox_In_32 = (rs2 >> shamt); - assign Sbox_In = Sbox_In_32[7:0]; + assign SboxIn32 = (rs2 >> shamt); + assign SboxIn = SboxIn32[7:0]; // Apply inverse sbox to si - aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out)); + aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut)); // Pad output of inverse substitution box - assign so = {24'h0, Sbox_Out}; + assign so = {24'h0, SboxOut}; // Run so through the mixword AES function - aes_inv_mixcolumns mix(.in(so), .out(mixed)); + aesinvmixcolumns mix(.in(so), .out(mixed)); // Rotate the substitution box output left by shamt (bs * 8) - assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); + assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));" - assign Data_Out = rs1 ^ mixed_rotate; + assign DataOut = rs1 ^ mixedrotate; endmodule diff --git a/src/ieu/aes_instructions/aes32esi.sv b/src/ieu/aes_instructions/aes32esi.sv index 1d54de585..83791f4c3 100644 --- a/src/ieu/aes_instructions/aes32esi.sv +++ b/src/ieu/aes_instructions/aes32esi.sv @@ -28,34 +28,34 @@ module aes32esi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] Data_Out); + output logic [31:0] DataOut); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] Sbox_In_32; - logic [7:0] Sbox_In; - logic [7:0] Sbox_Out; + logic [31:0] SboxIn32; + logic [7:0] SboxIn; + logic [7:0] SboxOut; logic [31:0] so; - logic [31:0] so_rotate; + logic [31:0] sorotate; // Shift bs by 3 to get shamt assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt to get sbox input - assign Sbox_In_32 = (rs2 >> shamt); + assign SboxIn32 = (rs2 >> shamt); // Take the bottom byte as an input to the substitution box - assign Sbox_In = Sbox_In_32[7:0]; + assign SboxIn = SboxIn32[7:0]; // Substitute - aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out)); + aessbox subbox(.in(SboxIn), .out(SboxOut)); // Pad sbox output - assign so = {24'h0, Sbox_Out}; + assign so = {24'h0, SboxOut}; // Rotate so left by shamt - assign so_rotate = (so << shamt) | (so >> (32 - shamt)); + assign sorotate = (so << shamt) | (so >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); - assign Data_Out = rs1 ^ so_rotate; + assign DataOut = rs1 ^ sorotate; endmodule diff --git a/src/ieu/aes_instructions/aes32esmi.sv b/src/ieu/aes_instructions/aes32esmi.sv index 88277a37d..b3839c93a 100644 --- a/src/ieu/aes_instructions/aes32esmi.sv +++ b/src/ieu/aes_instructions/aes32esmi.sv @@ -28,38 +28,38 @@ module aes32esmi(input logic [1:0] bs, input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] Data_Out); + output logic [31:0] DataOut); // Declare Intermediary logic logic [4:0] shamt; - logic [31:0] Sbox_In_32; - logic [7:0] Sbox_In; - logic [7:0] Sbox_Out; + logic [31:0] SboxIn32; + logic [7:0] SboxIn; + logic [7:0] SboxOut; logic [31:0] so; logic [31:0] mixed; - logic [31:0] mixed_rotate; + logic [31:0] mixedrotate; // Shift bs by 3 to get shamt assign shamt = {bs, 3'b0}; // Shift rs2 right by shamt to get sbox input - assign Sbox_In_32 = (rs2 >> shamt); + assign SboxIn32 = (rs2 >> shamt); // Take the bottom byte as an input to the substitution box - assign Sbox_In = Sbox_In_32[7:0]; + assign SboxIn = SboxIn32[7:0]; // Substitute - aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out)); + aessbox sbox(.in(SboxIn), .out(SboxOut)); // Pad sbox output - assign so = {24'h0, Sbox_Out}; + assign so = {24'h0, SboxOut}; - // Mix Word using aes_mixword component - aes_mixcolumns mwd(.in(so), .out(mixed)); + // Mix Word using aesmixword component + aesmixcolumns mwd(.in(so), .out(mixed)); // Rotate so left by shamt - assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt)); + assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt)); // Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); - assign Data_Out = rs1 ^ mixed_rotate; + assign DataOut = rs1 ^ mixedrotate; endmodule diff --git a/src/ieu/aes_instructions/aes64ds.sv b/src/ieu/aes_instructions/aes64ds.sv index 275d5b43c..d5289ab03 100644 --- a/src/ieu/aes_instructions/aes64ds.sv +++ b/src/ieu/aes_instructions/aes64ds.sv @@ -27,20 +27,20 @@ module aes64ds(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] Data_Out); + output logic [63:0] DataOut); // Intermediary Logic - logic [127:0] ShiftRow_Out; - logic [31:0] Sbox_Out_0; - logic [31:0] Sbox_Out_1; + logic [127:0] ShiftRowOut; + logic [31:0] SboxOut0; + logic [31:0] SboxOut1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aesinvshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aesinvsboxword inv_sbox_0(.in(ShiftRowOut[31:0]), .out(SboxOut0)); + aesinvsboxword inv_sbox_1(.in(ShiftRowOut[63:32]), .out(SboxOut1)); // Concatenate the two substitution outputs to get result - assign Data_Out = {Sbox_Out_1, Sbox_Out_0}; + assign DataOut = {SboxOut1, SboxOut0}; endmodule diff --git a/src/ieu/aes_instructions/aes64dsm.sv b/src/ieu/aes_instructions/aes64dsm.sv index 4695d42cc..194485642 100644 --- a/src/ieu/aes_instructions/aes64dsm.sv +++ b/src/ieu/aes_instructions/aes64dsm.sv @@ -27,26 +27,26 @@ module aes64dsm(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] Data_Out); + output logic [63:0] DataOut); // Intermediary Logic - logic [127:0] ShiftRow_Out; - logic [31:0] Sbox_Out_0; - logic [31:0] Sbox_Out_1; - logic [31:0] Mixcol_Out_0; - logic [31:0] Mixcol_Out_1; + logic [127:0] ShiftRowOut; + logic [31:0] SboxOut0; + logic [31:0] SboxOut1; + logic [31:0] MixcolOut0; + logic [31:0] MixcolOut1; // Apply inverse shiftrows to rs2 and rs1 - aes_inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out)); + aesinvshiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRowOut)); // Apply full word inverse substitution to lower 2 words of shiftrow out - aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0)); - aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1)); + aesinvsboxword invsbox0(.in(ShiftRowOut[31:0]), .out(SboxOut0)); + aesinvsboxword invsbox1(.in(ShiftRowOut[63:32]), .out(SboxOut1)); // Apply inverse mixword to sbox outputs - aes_inv_mixcolumns inv_mw_0(.in(Sbox_Out_0), .out(Mixcol_Out_0)); - aes_inv_mixcolumns inv_mw_1(.in(Sbox_Out_1), .out(Mixcol_Out_1)); + aesinvmixcolumns invmw0(.in(SboxOut0), .out(MixcolOut0)); + aesinvmixcolumns invmw1(.in(SboxOut1), .out(MixcolOut1)); // Concatenate mixed words for output - assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0}; + assign DataOut = {MixcolOut1, MixcolOut0}; endmodule diff --git a/src/ieu/aes_instructions/aes64es.sv b/src/ieu/aes_instructions/aes64es.sv index 58e6dfdc0..39521af76 100644 --- a/src/ieu/aes_instructions/aes64es.sv +++ b/src/ieu/aes_instructions/aes64es.sv @@ -27,15 +27,15 @@ module aes64es(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] Data_Out); + output logic [63:0] DataOut); // Intermediary Signals - logic [127:0] ShiftRow_Out; + logic [127:0] ShiftRowOut; // AES shiftrow unit - aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0])); - aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32])); + aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(DataOut[31:0])); + aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(DataOut[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64esm.sv b/src/ieu/aes_instructions/aes64esm.sv index 0e3fd0d56..0b0bab3a0 100644 --- a/src/ieu/aes_instructions/aes64esm.sv +++ b/src/ieu/aes_instructions/aes64esm.sv @@ -27,20 +27,20 @@ module aes64esm(input logic [63:0] rs1, input logic [63:0] rs2, - output logic [63:0] Data_Out); + output logic [63:0] DataOut); // Intermediary Signals - logic [127:0] ShiftRow_Out; - logic [63:0] Sbox_Out; + logic [127:0] ShiftRowOut; + logic [63:0] SboxOut; // AES shiftrow unit - aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out)); + aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut)); // Apply substitution box to 2 lower words - aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0])); - aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32])); + aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(SboxOut[31:0])); + aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(SboxOut[63:32])); // Apply mix columns operations - aes_mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0])); - aes_mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32])); + aesmixcolumns mw0(.in(SboxOut[31:0]), .out(DataOut[31:0])); + aesmixcolumns mw1(.in(SboxOut[63:32]), .out(DataOut[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64im.sv b/src/ieu/aes_instructions/aes64im.sv index d4b7f12bb..7e812587f 100644 --- a/src/ieu/aes_instructions/aes64im.sv +++ b/src/ieu/aes_instructions/aes64im.sv @@ -26,8 +26,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module aes64im(input logic [63:0] rs1, - output logic [63:0] Data_Out); + output logic [63:0] DataOut); - aes_inv_mixcolumns inv_mw_0(.in(rs1[31:0]), .out(Data_Out[31:0])); - aes_inv_mixcolumns inv_mw_1(.in(rs1[63:32]), .out(Data_Out[63:32])); + aesinvmixcolumns inv_mw_0(.in(rs1[31:0]), .out(DataOut[31:0])); + aesinvmixcolumns inv_mw_1(.in(rs1[63:32]), .out(DataOut[63:32])); endmodule diff --git a/src/ieu/aes_instructions/aes64ks1i.sv b/src/ieu/aes_instructions/aes64ks1i.sv index a8b44c3e5..bd7188ea0 100644 --- a/src/ieu/aes_instructions/aes64ks1i.sv +++ b/src/ieu/aes_instructions/aes64ks1i.sv @@ -30,33 +30,31 @@ module aes64ks1i(input logic [3:0] roundnum, output logic [63:0] rd); // Instantiate intermediary logic signals - logic [7:0] rcon_preshift; + logic [7:0] rconPreShift; logic [31:0] rcon; logic lastRoundFlag; - logic [31:0] rs1_rotate; + logic [31:0] rs1Rotate; logic [31:0] tmp2; - logic [31:0] Sbox_Out; + logic [31:0] SboxOut; // Get rcon value from table - rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift)); + rconlut128 rc(.RD(roundnum), .rconOut(rconPreShift)); // Shift RCON value - assign rcon = {24'b0, rcon_preshift}; + assign rcon = {24'b0, rconPreShift}; // Flag will be set if roundnum = 0xA = 0b1010 assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0]; // Get rotated value fo ruse in tmp2 - assign rs1_rotate = {rs1[39:32], rs1[63:40]}; + assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Assign tmp2 to a mux based on lastRoundFlag - assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate; + assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1Rotate; // Substitute bytes of value obtained for tmp2 using Rijndael sbox - aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out)); - assign rd[31:0] = Sbox_Out ^ rcon; - assign rd[63:32] = Sbox_Out ^ rcon; - - + aessboxword sbox(.in(tmp2),.out(SboxOut)); + assign rd[31:0] = SboxOut ^ rcon; + assign rd[63:32] = SboxOut ^ rcon; endmodule diff --git a/src/ieu/aes_instructions/rcon_lut_128.sv b/src/ieu/aes_instructions/rconlut128.sv similarity index 73% rename from src/ieu/aes_instructions/rcon_lut_128.sv rename to src/ieu/aes_instructions/rconlut128.sv index 89368408d..c95807778 100644 --- a/src/ieu/aes_instructions/rcon_lut_128.sv +++ b/src/ieu/aes_instructions/rconlut128.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// rcon_lut_128.sv +// rconlut128.sv // // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 @@ -25,24 +25,24 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rcon_lut_128(input logic [3:0] RD, - output logic [7:0] rcon_out); +module rconlut128(input logic [3:0] RD, + output logic [7:0] rconOut); always_comb begin case(RD) - 4'h0 : rcon_out = 8'h01; - 4'h1 : rcon_out = 8'h02; - 4'h2 : rcon_out = 8'h04; - 4'h3 : rcon_out = 8'h08; - 4'h4 : rcon_out = 8'h10; - 4'h5 : rcon_out = 8'h20; - 4'h6 : rcon_out = 8'h40; - 4'h7 : rcon_out = 8'h80; - 4'h8 : rcon_out = 8'h1b; - 4'h9 : rcon_out = 8'h36; - 4'hA : rcon_out = 8'h00; - default : rcon_out = 8'h00; + 4'h0 : rconOut = 8'h01; + 4'h1 : rconOut = 8'h02; + 4'h2 : rconOut = 8'h04; + 4'h3 : rconOut = 8'h08; + 4'h4 : rconOut = 8'h10; + 4'h5 : rconOut = 8'h20; + 4'h6 : rconOut = 8'h40; + 4'h7 : rconOut = 8'h80; + 4'h8 : rconOut = 8'h1b; + 4'h9 : rconOut = 8'h36; + 4'hA : rconOut = 8'h00; + default : rconOut = 8'h00; endcase end endmodule From 3b16238a37a04aec62ce769b3de0c11f333513f3 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 18:51:01 -0600 Subject: [PATCH 39/47] update removal of underscores from sha_instructions --- src/ieu/sha_instructions/sha512sig0h.sv | 4 ++-- src/ieu/sha_instructions/sha512sig0l.sv | 4 ++-- src/ieu/sha_instructions/sha512sig1h.sv | 4 ++-- src/ieu/sha_instructions/sha512sig1l.sv | 4 ++-- src/ieu/sha_instructions/sha512sum0r.sv | 4 ++-- src/ieu/sha_instructions/sha512sum1r.sv | 28 ++++++++++++------------- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/ieu/sha_instructions/sha512sig0h.sv b/src/ieu/sha_instructions/sha512sig0h.sv index a26ae0ef7..8074dc9a3 100644 --- a/src/ieu/sha_instructions/sha512sig0h.sv +++ b/src/ieu/sha_instructions/sha512sig0h.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // RS1 Shifts logic [31:0] shift1; @@ -47,6 +47,6 @@ module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2, assign shift24 = rs2 << 24; // XOR to get result - assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24; + assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24; endmodule diff --git a/src/ieu/sha_instructions/sha512sig0l.sv b/src/ieu/sha_instructions/sha512sig0l.sv index a12568fb5..0f0df38e9 100644 --- a/src/ieu/sha_instructions/sha512sig0l.sv +++ b/src/ieu/sha_instructions/sha512sig0l.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // rs1 operations logic [31:0] shift1; @@ -48,6 +48,6 @@ module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2, assign shift25 = rs2 << 25; assign shift24 = rs2 << 24; - assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24; + assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24; endmodule diff --git a/src/ieu/sha_instructions/sha512sig1h.sv b/src/ieu/sha_instructions/sha512sig1h.sv index cce4b593b..7929852d0 100644 --- a/src/ieu/sha_instructions/sha512sig1h.sv +++ b/src/ieu/sha_instructions/sha512sig1h.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // rs1 shifts logic [31:0] shift3; @@ -45,7 +45,7 @@ module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2, assign shift13 = rs2 << 13; // XOR Shifted registers for output - assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13; + assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13; endmodule diff --git a/src/ieu/sha_instructions/sha512sig1l.sv b/src/ieu/sha_instructions/sha512sig1l.sv index dae623091..f8ba1d9f4 100644 --- a/src/ieu/sha_instructions/sha512sig1l.sv +++ b/src/ieu/sha_instructions/sha512sig1l.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // rs1 shift logic logic [31:0] shift3; @@ -48,6 +48,6 @@ module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2, assign shift26 = rs2 << 26; assign shift13 = rs2 << 13; - assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13; + assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13; endmodule diff --git a/src/ieu/sha_instructions/sha512sum0r.sv b/src/ieu/sha_instructions/sha512sum0r.sv index e7ccf4e6e..1f92e6fdc 100644 --- a/src/ieu/sha_instructions/sha512sum0r.sv +++ b/src/ieu/sha_instructions/sha512sum0r.sv @@ -26,7 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // RS1 shifts logic [31:0] shift25; @@ -49,6 +49,6 @@ module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2, assign shift4 = rs2 << 4; // Set output to XOR of shifted values - assign data_out = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4; + assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4; endmodule diff --git a/src/ieu/sha_instructions/sha512sum1r.sv b/src/ieu/sha_instructions/sha512sum1r.sv index 36ccbc1be..0cf46e82c 100644 --- a/src/ieu/sha_instructions/sha512sum1r.sv +++ b/src/ieu/sha_instructions/sha512sum1r.sv @@ -26,29 +26,29 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module sha512sum1r(input logic [31:0] rs1, input logic [31:0] rs2, - output logic [31:0] data_out); + output logic [31:0] DataOut); // Declare logic for rs1 shifts - logic [31:0] shift1_23; - logic [31:0] shift1_14; - logic [31:0] shift1_18; + logic [31:0] shift1by23; + logic [31:0] shift1by14; + logic [31:0] shift1by18; // Declare logic for rs2 shifts - logic [31:0] shift2_9; - logic [31:0] shift2_18; - logic [31:0] shift2_14; + logic [31:0] shift2by9; + logic [31:0] shift2by18; + logic [31:0] shift2by14; // Shift RS1 - assign shift1_23 = rs1 << 23; - assign shift1_14 = rs1 >> 14; - assign shift1_18 = rs1 >> 18; + assign shift1by23 = rs1 << 23; + assign shift1by14 = rs1 >> 14; + assign shift1by18 = rs1 >> 18; // Shift RS2 - assign shift2_9 = rs2 >> 9; - assign shift2_18 = rs2 << 18; - assign shift2_14 = rs2 << 14; + assign shift2by9 = rs2 >> 9; + assign shift2by18 = rs2 << 18; + assign shift2by14 = rs2 << 14; // Assign output to xor of shifts - assign data_out = shift1_23 ^ shift1_14 ^ shift1_18 ^ shift2_9 ^ shift2_18 ^ shift2_14; + assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14; endmodule From 55e019c9ddfe50ed2fc5adf30cf6b89454323f41 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 19:00:31 -0600 Subject: [PATCH 40/47] update removal of underscores from kmu --- src/ieu/kmu/packer.sv | 49 +++++++++--------- src/ieu/kmu/zbkb.sv | 3 +- src/ieu/kmu/zbkx.sv | 15 +++--- src/ieu/kmu/zipper.sv | 6 +-- src/ieu/kmu/{zknd_32.sv => zknd32.sv} | 9 ++-- src/ieu/kmu/{zknd_64.sv => zknd64.sv} | 11 ++-- src/ieu/kmu/{zkne_32.sv => zkne32.sv} | 9 ++-- src/ieu/kmu/{zkne_64.sv => zkne64.sv} | 11 ++-- src/ieu/kmu/zknh32.sv | 71 ++++++++++++++++++++++++++ src/ieu/kmu/{zknh_64.sv => zknh64.sv} | 55 ++++++++++---------- src/ieu/kmu/zknh_32.sv | 72 --------------------------- 11 files changed, 150 insertions(+), 161 deletions(-) rename src/ieu/kmu/{zknd_32.sv => zknd32.sv} (90%) rename src/ieu/kmu/{zknd_64.sv => zknd64.sv} (88%) rename src/ieu/kmu/{zkne_32.sv => zkne32.sv} (90%) rename src/ieu/kmu/{zkne_64.sv => zkne64.sv} (88%) create mode 100644 src/ieu/kmu/zknh32.sv rename src/ieu/kmu/{zknh_64.sv => zknh64.sv} (53%) delete mode 100644 src/ieu/kmu/zknh_32.sv diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv index 1e0c3f542..3f17b16d0 100644 --- a/src/ieu/kmu/packer.sv +++ b/src/ieu/kmu/packer.sv @@ -30,30 +30,29 @@ module packer #(parameter WIDTH=32) ( input logic [2:0] PackSelect, output logic [WIDTH-1:0] PackResult); - logic [WIDTH/2-1:0] low_half, high_half; - logic [7:0] low_halfh, high_halfh; - logic [15:0] low_halfw, high_halfw; - - logic [WIDTH-1:0] Pack; - logic [WIDTH-1:0] PackH; - logic [WIDTH-1:0] PackW; + logic [WIDTH/2-1:0] lowhalf, highhalf; + logic [7:0] lowhalfh, highhalfh; + logic [15:0] lowhalfw, highhalfw; - assign low_half = A[WIDTH/2-1:0]; - assign high_half = B[WIDTH/2-1:0]; - assign low_halfh = A[7:0]; - assign high_halfh = B[7:0]; - assign low_halfw = A[15:0]; - assign high_halfw = B[15:0]; - - assign Pack = {high_half, low_half}; - assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; - assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; - - always_comb - begin - if (PackSelect[1:0] == 2'b11) PackResult = PackH; - else if (PackSelect[2] == 1'b0) PackResult = Pack; - else PackResult = PackW; - end - + logic [WIDTH-1:0] Pack; + logic [WIDTH-1:0] PackH; + logic [WIDTH-1:0] PackW; + + assign lowhalf = A[WIDTH/2-1:0]; + assign highhalf = B[WIDTH/2-1:0]; + assign lowhalfh = A[7:0]; + assign highhalfh = B[7:0]; + assign lowhalfw = A[15:0]; + assign highhalfw = B[15:0]; + + assign Pack = {highhalf, lowhalf}; + assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh}; + assign PackW = {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw}; + + always_comb + begin + if (PackSelect[1:0] == 2'b11) PackResult = PackH; + else if (PackSelect[2] == 1'b0) PackResult = Pack; + else PackResult = PackW; + end endmodule diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv index 33efb4b43..e6e667f17 100644 --- a/src/ieu/kmu/zbkb.sv +++ b/src/ieu/kmu/zbkb.sv @@ -41,6 +41,5 @@ module zbkb #(parameter WIDTH=32) zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult); // ZBKB Result Select Mux - mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult); - + mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult); endmodule diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv index cd22dd462..9e3d2c200 100644 --- a/src/ieu/kmu/zbkx.sv +++ b/src/ieu/kmu/zbkx.sv @@ -30,22 +30,21 @@ module zbkx #(parameter WIDTH=32) input logic [2:0] ZBKXSelect, output logic [WIDTH-1:0] ZBKXResult); - logic [WIDTH-1:0] xperm_lookup; - integer i; + logic [WIDTH-1:0] xpermlookup; + integer i; always_comb begin if (ZBKXSelect[0] == 1'b0) begin for(i=0; i> {B[i+:8], 3'b0}; - ZBKXResult[i+:8] = xperm_lookup[7:0]; + xpermlookup = A >> {B[i+:8], 3'b0}; + ZBKXResult[i+:8] = xpermlookup[7:0]; end end else begin for(i=0; i> {B[i+:4], 2'b0}; - ZBKXResult[i+:4] = xperm_lookup[3:0]; + xpermlookup = A >> {B[i+:4], 2'b0}; + ZBKXResult[i+:4] = xpermlookup[3:0]; end end - end - + end endmodule diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv index acbd36355..1799c5a89 100644 --- a/src/ieu/kmu/zipper.sv +++ b/src/ieu/kmu/zipper.sv @@ -36,12 +36,10 @@ module zipper #(parameter WIDTH=64) for (i=0; i Date: Sat, 9 Mar 2024 19:10:43 -0600 Subject: [PATCH 41/47] fix space at beginning of file in bmu --- src/ieu/bmu/bitreverse.sv | 1 - src/ieu/bmu/cnt.sv | 1 - src/ieu/bmu/ext.sv | 1 - src/ieu/bmu/popcnt.sv | 1 - src/ieu/bmu/zbb.sv | 1 - 5 files changed, 5 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 3876c31e4..083033d53 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // bitreverse.sv // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index eb54d6e3c..dff468257 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // cnt.sv // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 5ce1139fb..66d69fb21 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // ext.sv // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 903b67eeb..8f5759873 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // popccnt.sv // Written: Kevin Kim diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 5eba50440..e96ed7acd 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // zbb.sv // From ad12def935c711632cb2f8fdadd096df90879d2c Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 19:38:10 -0600 Subject: [PATCH 42/47] fix underscore in instantiation --- src/ieu/aes_common/aesinvsboxword.sv | 9 ++++----- src/ieu/aes_common/aessboxword.sv | 9 ++++----- src/ieu/aes_common/aesshiftrow.sv | 5 ++--- src/ieu/aes_common/galoismultforward.sv | 1 - 4 files changed, 10 insertions(+), 14 deletions(-) diff --git a/src/ieu/aes_common/aesinvsboxword.sv b/src/ieu/aes_common/aesinvsboxword.sv index 7baa03d21..ec0930d0c 100644 --- a/src/ieu/aes_common/aesinvsboxword.sv +++ b/src/ieu/aes_common/aesinvsboxword.sv @@ -28,12 +28,11 @@ module aesinvsboxword(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aesinvsbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aesinvsbox sboxb0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aesinvsbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aesinvsbox sboxb1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aesinvsbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aesinvsbox sboxb2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aesinvsbox sbox_b3(.in(in[31:24]), .out(out[31:24])); - + aesinvsbox sboxb3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aessboxword.sv b/src/ieu/aes_common/aessboxword.sv index 2a72b19b1..fd4e49af0 100644 --- a/src/ieu/aes_common/aessboxword.sv +++ b/src/ieu/aes_common/aessboxword.sv @@ -28,12 +28,11 @@ module aessboxword(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aessbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aessbox sboxb0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aessbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aessbox sboxb1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aessbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aessbox sboxb2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aessbox sbox_b3(.in(in[31:24]), .out(out[31:24])); - + aessbox sboxb3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aesshiftrow.sv b/src/ieu/aes_common/aesshiftrow.sv index 57ed86670..96e4b4e0d 100644 --- a/src/ieu/aes_common/aesshiftrow.sv +++ b/src/ieu/aes_common/aesshiftrow.sv @@ -4,7 +4,7 @@ // Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Created: 20 February 2024 // -// Purpose: aes_shiftrow for taking in first Data line +// Purpose: aesshiftrow for taking in first Data line // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -30,6 +30,5 @@ module aesshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut); assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64], DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32], - DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]}; - + DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]}; endmodule diff --git a/src/ieu/aes_common/galoismultforward.sv b/src/ieu/aes_common/galoismultforward.sv index 1dcfcd56f..86eed1a39 100644 --- a/src/ieu/aes_common/galoismultforward.sv +++ b/src/ieu/aes_common/galoismultforward.sv @@ -31,5 +31,4 @@ module galoismultforward(input logic [7:0] in, output logic [7:0] out); assign leftshift = {in[6:0], 1'b0}; assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift; - endmodule From 1aa1608a18248827884d93d010d659b149f4f57d Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 19:41:29 -0600 Subject: [PATCH 43/47] fix space in kmu --- src/ieu/kmu/zbkb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv index e6e667f17..21e92dad7 100644 --- a/src/ieu/kmu/zbkb.sv +++ b/src/ieu/kmu/zbkb.sv @@ -32,7 +32,7 @@ module zbkb #(parameter WIDTH=32) input logic [2:0] ZBKBSelect, output logic [WIDTH-1:0] ZBKBResult); - logic [WIDTH-1:0] ByteResult; // rev8, brev8 + logic [WIDTH-1:0] ByteResult; // rev8, brev8 logic [WIDTH-1:0] PackResult; // pack, packh, packw (RB64 only) logic [WIDTH-1:0] ZipResult; // zip, unzip From ac3aa823e7b1c12c8a262310955a136af3fc1930 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 20:19:46 -0600 Subject: [PATCH 44/47] fix underscore in bmu directory --- src/ieu/bmu/bitmanipalu.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index e52cfcf94..b4c07b182 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -111,30 +111,30 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // ZKND Unit if (P.ZKND_SUPPORTED) begin: zknd if (P.XLEN == 32) begin - zknd_32 #(P.XLEN) ZKND32(.A(ABMU), .B(BBMU), .Funct7, .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); + zknd32 #(P.XLEN) ZKND32(.A(ABMU), .B(BBMU), .Funct7, .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); end else begin - zknd_64 #(P.XLEN) ZKND64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); + zknd64 #(P.XLEN) ZKND64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult); end end else assign ZKNDResult = 0; // ZKNE Unit if (P.ZKNE_SUPPORTED) begin: zkne if (P.XLEN == 32) begin - zkne_32 #(P.XLEN) ZKNE32(.A(ABMU), .B(BBMU), .Funct7, .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); + zkne32 #(P.XLEN) ZKNE32(.A(ABMU), .B(BBMU), .Funct7, .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); end else begin - zkne_64 #(P.XLEN) ZKNE64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); + zkne64 #(P.XLEN) ZKNE64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult); end end else assign ZKNEResult = 0; // ZKNH Unit if (P.ZKNH_SUPPORTED) begin: zknh if (P.XLEN == 32) begin - zknh_32 ZKNH_32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); end else begin - zknh_64 ZKNH_64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); end end else assign ZKNHResult = 0; From 1573c890d0c3966f885aad78c7bd0e96fc8f4eca Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 22:01:20 -0600 Subject: [PATCH 45/47] Update bitmanipalu.sv for K extension --- src/ieu/bmu/bitmanipalu.sv | 63 ++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index b4c07b182..36700e066 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -1,18 +1,18 @@ /////////////////////////////////////////// // bitmanipalu.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 23 March 2023 -// Modified: 23 March 2023 +// Modified: 9 March 2024 // -// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension +// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension // // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -29,34 +29,39 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module bitmanipalu import cvw::*; #(parameter cvw_t P) ( - input logic [P.XLEN-1:0] A, B, // Operands - input logic W64, // W64-type instruction - input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [3:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform - input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations - input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND - input logic LT, // less than flag - input logic LTU, // less than unsigned flag - input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - input logic BMUActive, // Bit manipulation instruction being executed - input logic [P.XLEN-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals + input logic [P.XLEN-1:0] A, B, // Operands + input logic W64, // W64-type instruction + input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform + input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations + input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND + input logic LT, // less than flag + input logic LTU, // less than unsigned flag + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + input logic BMUActive, // Bit manipulation instruction being executed + input logic [P.XLEN-1:0] PreALUResult, // PreALUResult signals + input logic [P.XLEN-1:0] FullResult, // FullResult signals output logic [P.XLEN-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [P.XLEN-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions output logic [P.XLEN-1:0] ALUResult); // Result - logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result - logic [P.XLEN-1:0] ZBKBResult, ZBKCResult, ZBKXResult; // ZBKB, ZBKC Result - logic [P.XLEN-1:0] ZKNDResult, ZKNEResult; // ZKND, ZKNE Result - logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result - logic [P.XLEN-1:0] MaskB; // BitMask of B - logic [P.XLEN-1:0] RevA; // Bit-reversed A - logic Rotate; // Indicates if it is Rotate instruction - logic Mask; // Indicates if it is ZBS instruction - logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction - logic [1:0] PreShiftAmt; // Amount to Pre-Shift A - logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal - logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity + logic [P.XLEN-1:0] ZBBResult; // ZBB Result + logic [P.XLEN-1:0] ZBCResult; // ZBC Result + logic [P.XLEN-1:0] ZBKBResult // ZBKB Result + logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result + logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result + logic [P.XLEN-1:0] ZKNDResult; // ZKND Result + logic [P.XLEN-1:0] ZKNEResult; // ZKNE Result + logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result + logic [P.XLEN-1:0] MaskB; // BitMask of B + logic [P.XLEN-1:0] RevA; // Bit-reversed A + logic Rotate; // Indicates if it is Rotate instruction + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A + logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal + logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity // gate data inputs to BMU to only operate when BMU is active assign ABMU = A & {P.XLEN{BMUActive}}; @@ -144,7 +149,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX // 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH... 4'b0000: ALUResult = PreALUResult; - 4'b0001: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 4'b0001: ALUResult = FullResult; // NOTE: don't use ALUResult since ZBA/ZBS doesnt sext the MSB of RH word 4'b0010: ALUResult = ZBBResult; 4'b0011: ALUResult = ZBCResult; 4'b0100: ALUResult = ZBKBResult; From 54fec7c31fdf2c3905cbd3fa2d2fcf8751d29730 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 22:07:40 -0600 Subject: [PATCH 46/47] fix bitmanipalu.sv typo on missing semicolon --- src/ieu/bmu/bitmanipalu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 36700e066..f5e88b8b1 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -48,7 +48,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] ZBBResult; // ZBB Result logic [P.XLEN-1:0] ZBCResult; // ZBC Result - logic [P.XLEN-1:0] ZBKBResult // ZBKB Result + logic [P.XLEN-1:0] ZBKBResult; // ZBKB Result logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result logic [P.XLEN-1:0] ZKNDResult; // ZKND Result From 047291ef4983967a2e724b0fbbc4043b92b31d37 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 9 Mar 2024 22:09:31 -0600 Subject: [PATCH 47/47] add header for bmuctrl.sv --- src/ieu/bmu/bmuctrl.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d7d6d9a7d..63021864f 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // bmuctrl.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 16 February 2023 -// Modified: 6 March 2023 +// Modified: 6 March 2023, 9 March 2024 // // Purpose: Top level bit manipulation instruction decoder // @@ -12,7 +12,7 @@ // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 //