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mmu cleanup

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This commit is contained in:
David Harris 2023-01-14 18:27:53 -08:00
parent 9d51abc2e1
commit 93b0286934
3 changed files with 50 additions and 55 deletions
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59
pipelined/src/mmu/tlbcontrol.sv
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@ -29,39 +29,32 @@
`include "wally-config.vh" `include "wally-config.vh"
module tlbcontrol #(parameter ITLB = 0) ( module tlbcontrol #(parameter ITLB = 0) (
input logic [`SVMODE_BITS-1:0] SATP_MODE,
// Current value of satp CSR (from privileged unit) input logic [`XLEN-1:0] VAdr,
input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [`XLEN-1:0] VAdr, input logic [1:0] STATUS_MPP,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic [1:0] STATUS_MPP, input logic ReadAccess, WriteAccess,
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic DisableTranslation,
input logic TLBFlush, // Invalidate all TLB entries
// 00 - TLB is not being accessed input logic [7:0] PTEAccessBits,
// 1x - TLB is accessed for a read (or an instruction) input logic CAMHit,
// x1 - TLB is accessed for a write input logic Misaligned,
// 11 - TLB is accessed for both read and write output logic TLBMiss,
input logic ReadAccess, WriteAccess, output logic TLBHit,
input logic DisableTranslation, output logic TLBPageFault,
input logic TLBFlush, // Invalidate all TLB entries output logic DAPageFault,
input logic [7:0] PTEAccessBits, output logic SV39Mode,
input logic CAMHit, output logic Translate
input logic Misaligned,
output logic TLBMiss,
output logic TLBHit,
output logic TLBPageFault,
output logic DAPageFault,
output logic SV39Mode,
output logic Translate
); );
// Sections of the page table entry // Sections of the page table entry
logic [1:0] EffectivePrivilegeMode; logic [1:0] EffectivePrivilegeMode;
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
logic UpperBitsUnequalPageFault; logic UpperBitsUnequalPageFault;
logic TLBAccess; logic TLBAccess;
logic ImproperPrivilege; logic ImproperPrivilege;
// Grab the sv mode from SATP and determine whether translation should occur // Grab the sv mode from SATP and determine whether translation should occur
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
@ -70,8 +63,12 @@ module tlbcontrol #(parameter ITLB = 0) (
// Determine whether TLB is being used // Determine whether TLB is being used
assign TLBAccess = ReadAccess | WriteAccess; assign TLBAccess = ReadAccess | WriteAccess;
// Check whether upper bits of virtual addresss are all equal if (`XLEN==64) // Check whether upper bits of 64-bit virtual addressses are all equal
vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault); vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
else begin
assign SV39Mode = 0;
assign UpperBitsUnequalPageFault = 0;
end
// unswizzle useful PTE bits // unswizzle useful PTE bits
assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; assign {PTE_D, PTE_A} = PTEAccessBits[7:6];

20
pipelined/src/mmu/tlblru.sv
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@ -28,18 +28,18 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module tlblru #(parameter TLB_ENTRIES = 8) ( module tlblru #(parameter TLB_ENTRIES = 8) (
input logic clk, reset, input logic clk, reset,
input logic TLBWrite, input logic TLBWrite,
input logic TLBFlush, input logic TLBFlush,
input logic [TLB_ENTRIES-1:0] Matches, input logic [TLB_ENTRIES-1:0] Matches,
input logic CAMHit, input logic CAMHit,
output logic [TLB_ENTRIES-1:0] WriteEnables output logic [TLB_ENTRIES-1:0] WriteEnables
); );
logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
logic [TLB_ENTRIES-1:0] WriteLines; logic [TLB_ENTRIES-1:0] WriteLines;
logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
logic AllUsed; // High if the next access causes all RU bits to be 1 logic AllUsed; // High if the next access causes all RU bits to be 1
// Find the first line not recently used // Find the first line not recently used
priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines)); priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));

26
pipelined/src/mmu/vm64check.sv
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@ -29,20 +29,18 @@
`include "wally-config.vh" `include "wally-config.vh"
module vm64check ( module vm64check (
input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic [`SVMODE_BITS-1:0] SATP_MODE,
input logic [`XLEN-1:0] VAdr, input logic [`XLEN-1:0] VAdr,
output logic SV39Mode, UpperBitsUnequalPageFault output logic SV39Mode,
output logic UpperBitsUnequalPageFault
); );
if (`XLEN==64) begin:rv64 logic eq_63_47, eq_46_38;
assign SV39Mode = (SATP_MODE == `SV39);
// page fault if upper bits aren't all the same assign SV39Mode = (SATP_MODE == `SV39);
logic UpperEqual39, UpperEqual48;
assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]); // page fault if upper bits aren't all the same
assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48; assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
end else begin assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
assign SV39Mode = 0;
assign UpperBitsUnequalPageFault = 0;
end
endmodule endmodule