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https://github.com/openhwgroup/cvw
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testbench now compiles with basic infrastructure to do int64rem test on drsu
This commit is contained in:
Kevin Kim
parent
23bb96f857
commit
9343c2296e
@ -56,7 +56,8 @@ module testbenchfp;
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logic WriteIntVal; // value of the current WriteInt
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logic [P.FLEN-1:0] X, Y, Z; // inputs read from TestFloat
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logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat
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logic [P.XLEN-1:0] SrcA; // integer input
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logic [P.XLEN-1:0] SrcA, SrcB; // integer input
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logic W64; // is W64 instruction
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logic [P.FLEN-1:0] Ans; // correct answer from TestFloat
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logic [P.FLEN-1:0] Res; // result from other units
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logic [4:0] AnsFlg; // correct flags read from testfloat
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@ -84,6 +85,7 @@ module testbenchfp;
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logic [P.DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart;
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logic IDivStart;
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logic FDivBusyE;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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@ -118,11 +120,13 @@ module testbenchfp;
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logic [P.NE+1:0] QeM;
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logic [P.DIVb:0] QmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic IntDivE;
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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logic FMAop; // Is this a FMA operation?
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flop #(3) funct3reg(.clk, .d(Funct3E), .q(Funct3M));
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///////////////////////////////////////////////////////////////////////////////////////////////
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// ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| |||
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@ -660,12 +664,12 @@ module testbenchfp;
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end
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end
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if (TEST === "divremsqrttest") begin // if unified div sqrt is being tested
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Tests = {Tests, f128sqrt};
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Tests = {Tests, f64sqrt};
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OpCtrl = {OpCtrl, `SQRT_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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for(int i = 0; i<5; i++) begin
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Unit = {Unit, `DIVUNIT};
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Fmt = {Fmt, 2'b11};
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Fmt = {Fmt, 2'b01};
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end
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end
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if (TEST === "customdiv") begin // if unified div sqrt is being tested
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@ -682,7 +686,15 @@ module testbenchfp;
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Unit = {Unit, `DIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intdiv") begin // if unified div sqrt is being tested
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Tests = {Tests, intdiv};
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OpCtrl = {OpCtrl, `INTREM_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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end
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// check if nothing is being tested
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if (Tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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@ -732,10 +744,10 @@ module testbenchfp;
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// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
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readvectors #(P) readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
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.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
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.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .SrcB,
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.Xs, .Ys, .Zs, .Unit(UnitVal),
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.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
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.Xm, .Ym, .Zm, .DivStart,
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.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), .Funct3E,
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.Xm, .Ym, .Zm, .DivStart, .IDivStart, .IntDivE,
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.XNaN, .YNaN, .ZNaN,
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.XSNaN, .YSNaN, .ZSNaN,
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.XSubnorm, .ZSubnorm,
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@ -799,7 +811,7 @@ module testbenchfp;
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.Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
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.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
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end
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if (TEST === "divremsqrt" | TEST === "divremsqrttest" | TEST === "customdiv") begin: divremsqrt
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if (TEST === "divremsqrt" | TEST === "divremsqrttest" | TEST === "customdiv" | TEST === "intdiv") begin: divremsqrt
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drsu #(P) drsu(.clk, .reset, .XsE(Xs), .YsE(Ys), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
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.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
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@ -808,10 +820,10 @@ module testbenchfp;
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.OpCtrl(OpCtrlVal),
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.XSNaNE(XSNaN), .YSNaNE(YSNaN),
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.Frm(FrmVal),
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.FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
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.FDivStartE(DivStart), .IDivStartE(IDivStart), .W64E(1'b0),
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.StallM(1'b0), .FDivBusyE,
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.FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
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.Funct3E(Funct3E), .IntDivE(1'b0),
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.FlushE(1'b0), .ForwardedSrcAE(SrcA), .ForwardedSrcBE(SrcB), .Funct3M(Funct3M),
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.Funct3E(Funct3E), .IntDivE(IntDivE),
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.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE), .FResM(FpRes), .FIntDivResultM(IntRes), .FlgM(Flg));
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end
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else begin: postprocess
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@ -912,6 +924,7 @@ module testbenchfp;
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`CMPUNIT: Res = CmpRes;
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`CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes;
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`CVTFPUNIT: Res = FpRes;
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`INTDIVUNIT: Res = IntRes;
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endcase
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// select the flag to check
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@ -921,6 +934,7 @@ module testbenchfp;
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`CMPUNIT: ResFlg = CmpFlg;
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`CVTINTUNIT: ResFlg = Flg;
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`CVTFPUNIT: ResFlg = Flg;
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`INTDIVUNIT: ResFlg = Flg;
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endcase
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end
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@ -1030,7 +1044,7 @@ module testbenchfp;
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// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
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assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
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assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
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assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL) | (OpCtrlVal == `INTREM_OPCTRL);
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assign FMAop = (OpCtrlVal == `FMAUNIT);
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assign DivDone = OldFDivBusyE & ~FDivBusyE;
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@ -1044,7 +1058,7 @@ module testbenchfp;
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$display("inputs: %h %h %h\nSrcA: %h\n SrcB: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, SrcB, Res, ResFlg, Ans, AnsFlg);
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end
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// TestFloat sets the result to all 1's when there is an invalid result, however in
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@ -1100,6 +1114,7 @@ module readvectors (
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input logic [2:0] OpCtrl,
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output logic [P.FLEN-1:0] Ans,
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output logic [P.XLEN-1:0] SrcA,
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output logic [P.XLEN-1:0] SrcB,
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output logic [4:0] AnsFlg,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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@ -1111,6 +1126,9 @@ module readvectors (
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax,
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output logic DivStart,
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output logic IDivStart,
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output logic IntDivE,
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output logic [2:0] Funct3E,
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output logic [P.FLEN-1:0] X, Y, Z, XPostBox
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);
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@ -1265,6 +1283,21 @@ module readvectors (
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DivStart = 1'b0;
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end
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endcase
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`INTDIVUNIT: begin
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#20;
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X = {P.FLEN{1'bx}};
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SrcA = TestVector[2*(P.Q_LEN)+P.D_LEN-1:2*(P.Q_LEN)];
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SrcB = TestVector[(P.Q_LEN)+P.D_LEN-1:P.Q_LEN];
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Ans = TestVector[P.D_LEN-1:0];
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if (~clk) #5;
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IDivStart = 1'b1;
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IntDivE = 1'b1;
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Funct3E = 3'b110;
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#10 // one clk cycle
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IDivStart = 1'b0;
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IntDivE = 1'b0;
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end
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`CMPUNIT:
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case (Fmt)
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2'b11: begin // quad
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@ -42,6 +42,10 @@
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`define FROM_I_OPCTRL 3'b101
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`define FROM_UL_OPCTRL 3'b110
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`define FROM_L_OPCTRL 3'b111
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`define INTREMU_OPCTRL 3'b000
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`define INTREM_OPCTRL 3'b110
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`define INTDIV_OPCTRL 3'b010
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`define INTDIVU_OPCTRL 3'b011
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`define RNE 3'b000
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`define RZ 3'b001
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`define RU 3'b011
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@ -53,6 +57,7 @@
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`define CVTFPUNIT 4
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`define CMPUNIT 3
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`define DIVREMSQRTUNIT 5
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`define INTDIVUNIT 6
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string f16rv32cvtint[] = '{
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"ui32_to_f16_rne.tv",
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@ -589,5 +594,8 @@ string customdivcorrect[] = '{
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"f16_custom.tv"
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};
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string intdiv[] = '{
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"f16_kevin.tv"
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};
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@ -272,22 +272,22 @@ def create_vectors(my_config):
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src_file2.close()
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config_list = [
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Config(32, "M", "div", "div-", 0),
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Config(32, "M", "div", "div-", 4),
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Config(32, "F", "fdiv", "fdiv", 1),
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Config(32, "F", "fsqrt", "fsqrt", 2),
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Config(32, "M", "rem", "rem-", 3),
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Config(32, "M", "divu", "divu-", 4),
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Config(32, "M", "remu", "remu-", 5),
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Config(64, "M", "div", "div-", 0),
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Config(32, "M", "rem", "rem-", 6),
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Config(32, "M", "divu", "divu-", 5),
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Config(32, "M", "remu", "remu-", 7),
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Config(64, "M", "div", "div-", 4),
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Config(64, "F", "fdiv", "fdiv", 1),
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Config(64, "F", "fsqrt", "fsqrt", 2),
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Config(64, "M", "rem", "rem-", 3),
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Config(64, "M", "divu", "divu-", 4),
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Config(64, "M", "remu", "remu-", 5),
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Config(64, "M", "divw", "divw-", 6),
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Config(64, "M", "divuw", "divuw-", 7),
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Config(64, "M", "remw", "remw-", 8),
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Config(64, "M", "remuw", "remuw-", 9)
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Config(64, "M", "rem", "rem-", 6),
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Config(64, "M", "divu", "divu-", 5),
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Config(64, "M", "remu", "remu-", 7),
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Config(64, "M", "divw", "divw-", 4),
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Config(64, "M", "divuw", "divuw-", 5),
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Config(64, "M", "remw", "remw-", 6),
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Config(64, "M", "remuw", "remuw-", 7)
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]
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for c in config_list:
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294
tests/fp/combined_IF_vectors/extract_arch_vectors_v2.py
Executable file
294
tests/fp/combined_IF_vectors/extract_arch_vectors_v2.py
Executable file
@ -0,0 +1,294 @@
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#! /usr/bin/python3
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# author: Alessandro Maiuolo, Kevin Kim
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# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
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# date created: 3-29-2023
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# extract all arch test vectors
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import os
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wally = os.popen('echo $WALLY').read().strip()
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def ext_bits(my_string):
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target_len = 32 # we want 128 bits, div by 4 bc hex notation
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zeroes_to_add = target_len - len(my_string)
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return zeroes_to_add*"0" + my_string
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def twos_comp(b, x):
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if b == 32:
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return hex(0x100000000 - int(x,16))[2:]
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elif b == 64:
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return hex(0x10000000000000000 - int(x,16))[2:]
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else:
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return "UNEXPECTED_BITSIZE"
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def unpack_rf(packed):
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bin_u = bin(int(packed, 16))[2:].zfill(8) # translate to binary
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flags = hex(int(bin_u[3:],2))[2:].zfill(2)
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rounding_mode = hex(int(bin_u[:3],2))[2:]
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return flags, rounding_mode
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# rounding mode dictionary
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round_dict = {
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"rne":"0",
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"rnm":"4",
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"ru":"3",
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"rz":"1",
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"rd":"2",
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"dyn":"7"
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}
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# fcsr dictionary
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fcsr_dict = {
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"0":"rne",
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"128":"rnm",
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"96":"ru",
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"32":"rz",
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"64":"rd",
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"224":"dyn"
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}
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print("creating arch test vectors")
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class Config:
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def __init__(self, bits, letter, op, filt, op_code):
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self.bits = bits
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self.letter = letter
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self.op = op
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self.filt = filt
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self.op_code = op_code
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def create_vectors(my_config):
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suite_folder_num = my_config.bits
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if my_config.bits == 64 and my_config.letter == "F": suite_folder_num = 32
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source_dir1 = "{}/addins/riscv-arch-test/riscv-test-suite/rv{}i_m/{}/src/".format(wally, suite_folder_num, my_config.letter)
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source_dir2 = "{}/tests/riscof/work/riscv-arch-test/rv{}i_m/{}/src/".format(wally, my_config.bits, my_config.letter)
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dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
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all_vectors1 = os.listdir(source_dir1)
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filt_vectors1 = [v for v in all_vectors1 if my_config.filt in v]
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# print(filt_vectors1)
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filt_vectors2 = [v + "/ref/Reference-sail_c_simulator.signature" for v in all_vectors1 if my_config.filt in v]
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# iterate through all vectors
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for i in range(len(filt_vectors1)):
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vector1 = filt_vectors1[i]
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vector2 = filt_vectors2[i]
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operation = my_config.op_code
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rounding_mode = "X"
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flags = "XX"
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# use name to create our new tv
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dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w')
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# open vectors
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src_file1 = open(source_dir1 + vector1,'r')
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src_file2 = open(source_dir2 + vector2,'r')
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# for each test in the vector
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reading = True
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src_file2.readline() #skip first bc junk
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# print(my_config.bits, my_config.letter)
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if my_config.letter == "F" and my_config.bits == 64:
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reading = True
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# print("trigger 64F")
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#skip first 2 lines bc junk
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src_file2.readline()
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while reading:
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# get answer and flags from Ref...signature
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# answers are before deadbeef (first line of 4)
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# flags are after deadbeef (third line of 4)
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answer = src_file2.readline().strip()
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deadbeef = src_file2.readline().strip()
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# print(answer)
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if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
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# get flags
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packed = src_file2.readline().strip()[6:]
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flags, rounding_mode = unpack_rf(packed)
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# skip 00000000 buffer
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src_file2.readline()
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# parse through .S file
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detected = False
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done = False
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op1val = "0"
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op2val = "0"
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while not (detected or done):
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# print("det1")
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line = src_file1.readline()
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# print(line)
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if "op1val" in line:
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# print("det2")
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# parse line
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals
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op2val = line.split("op2val")[1].split("x")[1].strip()
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if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
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else:
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op2val = 32*"X"
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# go to next test in vector
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detected = True
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elif "RVTEST_CODE_END" in line:
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done = True
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# put it all together
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if not done:
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translation = "{}_{}_{}".format(ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()))
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dest_file.write(translation + "\n")
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else:
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# print("read false")
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reading = False
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elif my_config.letter == "M" and my_config.bits == 64:
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reading = True
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#skip first 2 lines bc junk
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src_file2.readline()
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while reading:
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# print("trigger 64M")
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# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer2 = src_file2.readline().strip()
|
||||
answer1 = src_file2.readline().strip()
|
||||
answer = answer1 + answer2
|
||||
#print(answer1,answer2)
|
||||
if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}".format(ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()))
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
elif my_config.letter == "M" and my_config.bits == 32:
|
||||
reading = True
|
||||
while reading:
|
||||
# print("trigger 64M")
|
||||
# get answer from Ref...signature
|
||||
# answers span two lines and are reversed
|
||||
answer = src_file2.readline().strip()
|
||||
print(f"Answer: {answer}")
|
||||
#print(answer1,answer2)
|
||||
if not (answer == "6f5ca309"): # if there is still stuff to read
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# ints don't have flags
|
||||
flags = "XX"
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}".format(ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()))
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
else:
|
||||
while reading:
|
||||
# get answer and flags from Ref...signature
|
||||
answer = src_file2.readline()
|
||||
print(answer)
|
||||
packed = src_file2.readline()[6:]
|
||||
print("Packed: ", packed)
|
||||
if len(packed.strip())>0: # if there is still stuff to read
|
||||
# print("packed")
|
||||
# parse through .S file
|
||||
detected = False
|
||||
done = False
|
||||
op1val = "0"
|
||||
op2val = "0"
|
||||
while not (detected or done):
|
||||
# print("det1")
|
||||
line = src_file1.readline()
|
||||
# print(line)
|
||||
if "op1val" in line:
|
||||
# print("det2")
|
||||
# parse line
|
||||
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||
op1val = twos_comp(my_config.bits, op1val)
|
||||
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||
op2val = twos_comp(my_config.bits, op2val)
|
||||
# go to next test in vector
|
||||
detected = True
|
||||
elif "RVTEST_CODE_END" in line:
|
||||
done = True
|
||||
# rounding mode for float
|
||||
if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
|
||||
flags, rounding_mode = unpack_rf(packed)
|
||||
|
||||
# put it all together
|
||||
if not done:
|
||||
translation = "{}_{}_{}".format(ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()))
|
||||
dest_file.write(translation + "\n")
|
||||
else:
|
||||
# print("read false")
|
||||
reading = False
|
||||
# print("out")
|
||||
dest_file.close()
|
||||
src_file1.close()
|
||||
src_file2.close()
|
||||
|
||||
config_list = [
|
||||
Config(32, "M", "div", "div-", 4),
|
||||
Config(32, "F", "fdiv", "fdiv", 1),
|
||||
Config(32, "F", "fsqrt", "fsqrt", 2),
|
||||
Config(32, "M", "rem", "rem-", 6),
|
||||
Config(32, "M", "divu", "divu-", 5),
|
||||
Config(32, "M", "remu", "remu-", 7),
|
||||
Config(64, "M", "div", "div-", 4),
|
||||
Config(64, "F", "fdiv", "fdiv", 1),
|
||||
Config(64, "F", "fsqrt", "fsqrt", 2),
|
||||
Config(64, "M", "rem", "rem-", 6),
|
||||
Config(64, "M", "divu", "divu-", 5),
|
||||
Config(64, "M", "remu", "remu-", 7),
|
||||
Config(64, "M", "divw", "divw-", 4),
|
||||
Config(64, "M", "divuw", "divuw-", 5),
|
||||
Config(64, "M", "remw", "remw-", 6),
|
||||
Config(64, "M", "remuw", "remuw-", 7)
|
||||
]
|
||||
|
||||
for c in config_list:
|
||||
create_vectors(c)
|
||||
Loading…
Reference in New Issue
Block a user