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https://github.com/openhwgroup/cvw
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///////////////////////////////////////////
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///////////////////////////////////////////
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// controller input stage
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// controller input stage
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//
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//
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// Written: Ross Thompson August 31, 2022
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// Written: Ross Thompson ross1728@gmail.com
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// ross1728@gmail.com
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// Created: August 31, 2022
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// Modified:
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// Modified: 18 January 2023
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//
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//
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// Purpose: AHB multi controller interface to merge LSU and IFU controls.
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// Purpose: AHB multi controller interface to merge LSU and IFU controls.
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
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//
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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//
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@ -32,25 +33,29 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module controllerinputstage #(parameter SAVE_ENABLED = 1) (
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module controllerinputstage #(
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parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs
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)(
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input logic HCLK,
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input logic HCLK,
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input logic HRESETn,
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input logic HRESETn,
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input logic Save, Restore, Disable,
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input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
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output logic Request,
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input logic Restore, // Restore a saved manager inputs when it is finally granted
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input logic Disable, // Supress HREADY to the non-granted manager
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output logic Request, // This manager is making a request
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// controller input
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// controller input
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input logic HWRITEIn,
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input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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input logic [2:0] HSIZEIn,
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input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation
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input logic [2:0] HBURSTIn,
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input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
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input logic [1:0] HTRANSIn,
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input logic [2:0] HBURSTIn, // Manager input. AHB burst length
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input logic [`PA_BITS-1:0] HADDRIn,
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input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
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output logic HREADYOut,
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output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority
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// controller output
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// controller output
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output logic HWRITEOut,
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output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
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output logic [2:0] HSIZEOut,
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output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation
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output logic [2:0] HBURSTOut,
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output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width
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output logic [1:0] HTRANSOut,
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output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length
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output logic [`PA_BITS-1:0] HADDROut,
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output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address
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input logic HREADYIn
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input logic HREADYIn // Peripherial ready
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);
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);
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logic HWRITESave;
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logic HWRITESave;
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