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Added clock gater and divider to generate the SDCCLK.

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This commit is contained in:
Ross Thompson 2021-09-23 17:58:50 -05:00
parent 3cbbd15763
commit 92ea88c57b
1 changed files with 21 additions and 6 deletions
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27
wally-pipelined/src/sdc/SDC.sv
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@ -59,7 +59,7 @@ module SDC
// Register outputs
logic [31:0] CLKDiv;
logic [7:0] CLKDiv;
logic [2:0] Command;
logic [`XLEN-1:9] Address;
@ -125,7 +125,7 @@ module SDC
assign StartCLKDivUpdate = HADDRDelay == '0 & RegWrite;
flopenl #(32) CLKDivReg(HCLK, ~HRESETn, CLKDivUpdateEn, HWDATA[31:0], `SDCCLKDIV, CLKDiv);
flopenl #(8) CLKDivReg(HCLK, ~HRESETn, CLKDivUpdateEn, HWDATA[31:0], `SDCCLKDIV, CLKDiv);
// Control reg
flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (SDCDone),
@ -141,7 +141,7 @@ module SDC
if(`XLEN == 64) begin
always_comb
case(HADDRDelay[4:2])
'h0: HREADSDC = {32'b0, CLKDiv};
'h0: HREADSDC = {`XLEN-8'b0, CLKDiv};
'h4: HREADSDC = {`XLEN-6'b0, ErrorCode, InvalidCommand, Done, Busy};
'h8: HREADSDC = {`XLEN-3'b0, Command};
'hC: HREADSDC = 'h200;
@ -183,9 +183,9 @@ module SDC
statetype CurrState, NextState;
always_ff @(posedge HCLK, posedge ~HRESETn)
if (~HRESETn) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
always_ff @(posedge HCLK, negedge HRESETn)
if (~HRESETn) CurrState <= STATE_READY;
else CurrState <= NextState;
always_comb begin
CLKDivUpdateEn = 1'b0;
@ -225,6 +225,21 @@ module SDC
endcase
end
// clock generation divider
clockgater clockgater(.E(SDCLKEN),
.SE(1'b0),
.CLK(HCLK),
.ECLK(CLKGate));
clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
.i_EN(CLKDiv != 'b1),
.i_CLK(CLKGate),
.i_RST(~HRESETn),
.o_CLK(CLKSDC));
endmodule