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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added clock gater and divider to generate the SDCCLK.
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@ -59,7 +59,7 @@ module SDC
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// Register outputs
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// Register outputs
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logic [31:0] CLKDiv;
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logic [7:0] CLKDiv;
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logic [2:0] Command;
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logic [2:0] Command;
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logic [`XLEN-1:9] Address;
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logic [`XLEN-1:9] Address;
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@ -125,7 +125,7 @@ module SDC
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assign StartCLKDivUpdate = HADDRDelay == '0 & RegWrite;
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assign StartCLKDivUpdate = HADDRDelay == '0 & RegWrite;
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flopenl #(32) CLKDivReg(HCLK, ~HRESETn, CLKDivUpdateEn, HWDATA[31:0], `SDCCLKDIV, CLKDiv);
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flopenl #(8) CLKDivReg(HCLK, ~HRESETn, CLKDivUpdateEn, HWDATA[31:0], `SDCCLKDIV, CLKDiv);
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// Control reg
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// Control reg
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flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (SDCDone),
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flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (SDCDone),
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@ -141,7 +141,7 @@ module SDC
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if(`XLEN == 64) begin
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if(`XLEN == 64) begin
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always_comb
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always_comb
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case(HADDRDelay[4:2])
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case(HADDRDelay[4:2])
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'h0: HREADSDC = {32'b0, CLKDiv};
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'h0: HREADSDC = {`XLEN-8'b0, CLKDiv};
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'h4: HREADSDC = {`XLEN-6'b0, ErrorCode, InvalidCommand, Done, Busy};
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'h4: HREADSDC = {`XLEN-6'b0, ErrorCode, InvalidCommand, Done, Busy};
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'h8: HREADSDC = {`XLEN-3'b0, Command};
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'h8: HREADSDC = {`XLEN-3'b0, Command};
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'hC: HREADSDC = 'h200;
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'hC: HREADSDC = 'h200;
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@ -183,9 +183,9 @@ module SDC
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statetype CurrState, NextState;
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statetype CurrState, NextState;
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always_ff @(posedge HCLK, posedge ~HRESETn)
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) CurrState <= #1 STATE_READY;
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if (~HRESETn) CurrState <= STATE_READY;
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else CurrState <= #1 NextState;
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else CurrState <= NextState;
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always_comb begin
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always_comb begin
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CLKDivUpdateEn = 1'b0;
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CLKDivUpdateEn = 1'b0;
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@ -224,6 +224,21 @@ module SDC
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end
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end
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endcase
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endcase
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end
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end
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// clock generation divider
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clockgater clockgater(.E(SDCLKEN),
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.SE(1'b0),
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.CLK(HCLK),
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.ECLK(CLKGate));
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clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
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.i_EN(CLKDiv != 'b1),
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.i_CLK(CLKGate),
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.i_RST(~HRESETn),
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.o_CLK(CLKSDC));
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endmodule
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endmodule
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