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https://github.com/openhwgroup/cvw
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same but do that right this time
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parent
280cd94280
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@ -169,8 +169,8 @@ module testbench();
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initial begin
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initial begin
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$readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
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$readmemh({`BUSYBEAR_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
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$readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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$readmemh({`BUSYBEAR_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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end
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end
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integer warningCount = 0;
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integer warningCount = 0;
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@ -532,7 +532,7 @@ module testbench();
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instrs += 1;
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instrs += 1;
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// are we at a branch/jump?
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// are we at a branch/jump?
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if (`BPRED_ENABLED) begin
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if (`BPRED_ENABLED) begin
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speculative = dut.hart.ifu.bpred.BPPredWrongE;
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speculative = dut.hart.ifu.bpred.bpred.BPPredWrongE;
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end else begin
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end else begin
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casex (lastCheckInstrD[31:0])
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casex (lastCheckInstrD[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00000000001000000000000001110011, // URET
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