Merge pull request #136 from davidharrishmc/dev

Bug fix in wally-regression

.editorconfig

@@ -0,0 +1,5 @@
+root = true
+
+[src/**.sv]
+indent_style = space
+indent_size = 2

setup.sh

@@ -48,8 +48,9 @@ if [ -e "$IDV" ]; then
     export IMPERAS_HOME=$IDV/Imperas
     export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
     export ROOTDIR=~/
-    source ${IDV}/Imperas/bin/setup.sh
+    source ${IMPERAS_HOME}/bin/setup.sh
-    setupImperas ${IDV}/Imperas
+    setupImperas ${IMPERAS_HOME}
+    export PATH=$IDV/scripts/cvw:$PATH
 fi
 
 

sim/regression-wally

@@ -27,6 +27,8 @@ from collections import namedtuple
 regressionDir = os.path.dirname(os.path.abspath(__file__))
 os.chdir(regressionDir)
 
+coverage = '-coverage' in sys.argv
+
 TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
 # name:     the name of this test configuration (used in printing human-readable
 #           output and picking logfile names)
@@ -66,14 +68,6 @@ tc = TestCase(
 configs.append(tc)
 
 tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
-tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
-for test in tests64gc:
-  tc = TestCase(
-        name=test,
-        variant="rv64gc",
-        cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+"\n!",
-        grepstr="All tests ran without failures")
-  configs.append(tc)
 
 tests64i = ["arch64i"] 
 for test in tests64i:
@@ -131,6 +125,21 @@ for test in ahbTests:
         cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
+
+#tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
+tests64gc = ["arch64i", "arch64c",  "arch64m"] 
+if (coverage):  # delete all but 64gc tests when running coverage
+    configs = []
+    coverStr = '-coverage'
+else:
+   coverStr = ''
+for test in tests64gc:
+  tc = TestCase(
+        name=test,
+        variant="rv64gc",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
   
 
 import os
@@ -158,7 +167,7 @@ def run_test_case(config):
 
 def main():
     """Run the tests and count the failures"""
-    global configs
+    global configs, coverage
     try:
         os.chdir(regressionDir)
         os.mkdir("logs")
@@ -183,6 +192,10 @@ def main():
     elif '-buildroot' in sys.argv:
         TIMEOUT_DUR = 30*7200 # seconds
         configs=[getBuildrootTC(boot=True)]
+    elif '-coverage' in sys.argv:
+        TIMEOUT_DUR = 20*60 # seconds       
+        #configs.append(getBuildrootTC(boot=False))
+        os.system('rm cov/*.ucdb')
     else:
         TIMEOUT_DUR = 10*60 # seconds
         configs.append(getBuildrootTC(boot=False))
@@ -201,6 +214,12 @@ def main():
              num_fail+=1
              print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
 
+    # Coverage report
+    if coverage:
+       print('Generating coverage report')
+       os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log')
+       os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage.rpt')
+       os.system('vcover report -html cov/cov.ucdb')
     # Count the number of failures
     if num_fail:
         print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)

sim/wally-batch.do

@@ -40,6 +40,9 @@ if {$2 eq "ahb"} {
     }
     vlib wkdir/work_${1}_${2}
 }
+# Create directory for coverage data
+mkdir -p cov
+
 # compile source files
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
@@ -112,20 +115,28 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
+    if {$argc >= 3} {
-    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
-    # Adding coverage increases runtime from 2:00 to 4:29.  Can't run it all the time
+        vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829 -coverage
-    #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
+    } else {
-    #vsim -coverage -lib work_$2 workopt_$2
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
+        vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
+    }
+#    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
     # power add generates the logging necessary for said generation.
     # power add -r /dut/core/*
     run -all
     # power off -r /dut/core/*
 } 
 
-#coverage report -file wally-coverage.txt
+if {$argc >= 3) {}
+    if ($3 eq "-coverage"} {
+        do coverage-exclusions.do
+        coverage save -instance /testbench/dut cov/${1}_${2}.ucdb
+    }
+}
+
 # These aren't doing anything helpful
-#coverage report -memory 
 #profile report -calltree -file wally-calltree.rpt -cutoff 2
 #power report -all -bsaif power.saif
 quit

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -69,6 +69,6 @@ module fdivsqrtexpcalc(
   assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
   
   // correct exponent for subnormal input's normalization shifts
-  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
+  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}}; // *** why Xzero?  Is this a hack for postprocessor?
   assign Qe = Sqrt ? SExp : DExp;
 endmodule

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -151,7 +151,7 @@ module fdivsqrtpreproc (
   lzc #(`DIVb) lzcY (IFNormLenD, mE);
 
   // Normalization shift
-  assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); 
+  assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
   assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
 
   // append leading 1 (for normal inputs)

src/ieu/alu.sv

@@ -38,7 +38,7 @@ module alu #(parameter WIDTH=32) (
 
   // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
   // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
-  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;  // Intermediate results
+  logic [WIDTH-1:0] CondInvB, Shift, FullResult;             // Intermediate results
   logic             Carry, Neg;                              // Flags: carry out, negative
   logic             LT, LTU;                                 // Less than, Less than unsigned
   logic             W64;                                     // RV64 W-type instruction
@@ -66,21 +66,17 @@ module alu #(parameter WIDTH=32) (
   assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; 
   assign LTU = ~Carry;
  
-  // SLT
-  assign SLT = {{(WIDTH-1){1'b0}}, LT};
-  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
- 
   // Select appropriate ALU Result
   always_comb
-    if (~ALUOp) FullResult = Sum;     // Always add for ALUOp = 0 (address generation)
+    if (~ALUOp) FullResult = Sum;                     // Always add for ALUOp = 0 (address generation)
-    else casez (Funct3)               // Otherwise check Funct3
+    else casez (Funct3)                               // Otherwise check Funct3
-      3'b000: FullResult = Sum;       // add or sub
+      3'b000: FullResult = Sum;                       // add or sub
-      3'b?01: FullResult = Shift;     // sll, sra, or srl
+      3'b?01: FullResult = Shift;                     // sll, sra, or srl
-      3'b010: FullResult = SLT;       // slt
+      3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT};   // slt
-      3'b011: FullResult = SLTU;      // sltu
+      3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU};  // sltu
-      3'b100: FullResult = A ^ B;     // xor
+      3'b100: FullResult = A ^ B;                     // xor
-      3'b110: FullResult = A | B;     // or 
+      3'b110: FullResult = A | B;                     // or 
-      3'b111: FullResult = A & B;     // and
+      3'b111: FullResult = A & B;                     // and
     endcase
 
   // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits

src/mdu/mdu.sv

@@ -32,11 +32,11 @@ module mdu(
   input  logic 							clk, reset,
   input  logic 							StallM, StallW, 
   input  logic							FlushE, FlushM, FlushW,
-	input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
+  input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
-	input  logic [2:0] 				Funct3E, Funct3M,									// type of MDU operation
+  input  logic [2:0] 				Funct3E, Funct3M,									// type of MDU operation
-	input  logic 							IntDivE, W64E, 										// Integer division/remainder, and W-type instrutions
+  input  logic 							IntDivE, W64E, 										// Integer division/remainder, and W-type instrutions
-	output logic [`XLEN-1:0] 	MDUResultW,												// multiply/divide result
+  output logic [`XLEN-1:0] 	MDUResultW,												// multiply/divide result
-	output logic 							DivBusyE													// busy signal to stall pipeline in Execute stage
+  output logic 							DivBusyE													// busy signal to stall pipeline in Execute stage
 );
 
 	logic [`XLEN*2-1:0] 			ProdM; 														// double-width product from mul