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https://github.com/openhwgroup/cvw
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Merge pull request #136 from davidharrishmc/dev
Bug fix in wally-regression
This commit is contained in:
Ross Thompson
GitHub
commit
9250c7b2de
5
.editorconfig
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5
.editorconfig
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@ -0,0 +1,5 @@
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root = true
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[src/**.sv]
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indent_style = space
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indent_size = 2
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5
setup.sh
5
setup.sh
@ -48,8 +48,9 @@ if [ -e "$IDV" ]; then
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export IMPERAS_HOME=$IDV/Imperas
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export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
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export ROOTDIR=~/
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source ${IDV}/Imperas/bin/setup.sh
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setupImperas ${IDV}/Imperas
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source ${IMPERAS_HOME}/bin/setup.sh
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setupImperas ${IMPERAS_HOME}
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export PATH=$IDV/scripts/cvw:$PATH
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fi
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@ -27,6 +27,8 @@ from collections import namedtuple
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regressionDir = os.path.dirname(os.path.abspath(__file__))
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os.chdir(regressionDir)
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coverage = '-coverage' in sys.argv
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
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# name: the name of this test configuration (used in printing human-readable
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# output and picking logfile names)
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@ -66,14 +68,6 @@ tc = TestCase(
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configs.append(tc)
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tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
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tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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for test in tests64gc:
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tc = TestCase(
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name=test,
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variant="rv64gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+"\n!",
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grepstr="All tests ran without failures")
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configs.append(tc)
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tests64i = ["arch64i"]
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for test in tests64i:
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@ -131,6 +125,21 @@ for test in ahbTests:
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
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grepstr="All tests ran without failures")
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configs.append(tc)
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#tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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tests64gc = ["arch64i", "arch64c", "arch64m"]
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if (coverage): # delete all but 64gc tests when running coverage
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configs = []
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coverStr = '-coverage'
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else:
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coverStr = ''
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for test in tests64gc:
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tc = TestCase(
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name=test,
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variant="rv64gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
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grepstr="All tests ran without failures")
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configs.append(tc)
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import os
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@ -158,7 +167,7 @@ def run_test_case(config):
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def main():
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"""Run the tests and count the failures"""
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global configs
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global configs, coverage
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try:
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os.chdir(regressionDir)
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os.mkdir("logs")
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@ -183,6 +192,10 @@ def main():
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elif '-buildroot' in sys.argv:
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TIMEOUT_DUR = 30*7200 # seconds
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configs=[getBuildrootTC(boot=True)]
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elif '-coverage' in sys.argv:
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TIMEOUT_DUR = 20*60 # seconds
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#configs.append(getBuildrootTC(boot=False))
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os.system('rm cov/*.ucdb')
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else:
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TIMEOUT_DUR = 10*60 # seconds
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configs.append(getBuildrootTC(boot=False))
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@ -201,6 +214,12 @@ def main():
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num_fail+=1
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print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
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# Coverage report
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if coverage:
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print('Generating coverage report')
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os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log')
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os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage.rpt')
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os.system('vcover report -html cov/cov.ucdb')
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# Count the number of failures
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if num_fail:
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print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
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@ -40,6 +40,9 @@ if {$2 eq "ahb"} {
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}
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vlib wkdir/work_${1}_${2}
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}
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# Create directory for coverage data
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mkdir -p cov
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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@ -112,20 +115,28 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
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#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
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#vsim -coverage -lib work_$2 workopt_$2
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if {$argc >= 3} {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage
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} else {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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}
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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run -all
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# power off -r /dut/core/*
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}
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#coverage report -file wally-coverage.txt
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if {$argc >= 3) {}
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if ($3 eq "-coverage"} {
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do coverage-exclusions.do
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coverage save -instance /testbench/dut cov/${1}_${2}.ucdb
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}
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}
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# These aren't doing anything helpful
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#coverage report -memory
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#profile report -calltree -file wally-calltree.rpt -cutoff 2
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#power report -all -bsaif power.saif
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quit
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@ -69,6 +69,6 @@ module fdivsqrtexpcalc(
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assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
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// correct exponent for subnormal input's normalization shifts
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assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
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assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}}; // *** why Xzero? Is this a hack for postprocessor?
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assign Qe = Sqrt ? SExp : DExp;
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endmodule
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@ -151,7 +151,7 @@ module fdivsqrtpreproc (
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lzc #(`DIVb) lzcY (IFNormLenD, mE);
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// Normalization shift
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1});
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for normal inputs)
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@ -38,7 +38,7 @@ module alu #(parameter WIDTH=32) (
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results
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logic [WIDTH-1:0] CondInvB, Shift, FullResult; // Intermediate results
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic W64; // RV64 W-type instruction
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@ -66,21 +66,17 @@ module alu #(parameter WIDTH=32) (
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg;
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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always_comb
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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@ -32,11 +32,11 @@ module mdu(
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input logic clk, reset,
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input logic StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
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input logic [2:0] Funct3E, Funct3M, // type of MDU operation
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input logic IntDivE, W64E, // Integer division/remainder, and W-type instrutions
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output logic [`XLEN-1:0] MDUResultW, // multiply/divide result
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output logic DivBusyE // busy signal to stall pipeline in Execute stage
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
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input logic [2:0] Funct3E, Funct3M, // type of MDU operation
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input logic IntDivE, W64E, // Integer division/remainder, and W-type instrutions
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output logic [`XLEN-1:0] MDUResultW, // multiply/divide result
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output logic DivBusyE // busy signal to stall pipeline in Execute stage
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);
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logic [`XLEN*2-1:0] ProdM; // double-width product from mul
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