Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

busybear: probably discovered bug in ahb code

Browse Source
This commit is contained in:
Noah Boorstin 2021-03-01 20:56:04 +00:00
parent b6dc0a8707
commit 923489fe16
3 changed files with 22 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
wally-pipelined/regression/wally-busybear.do
View File

@ -59,12 +59,20 @@ add wave /testbench_busybear/lastCheckInstrF
add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2
add wave -divider
add wave -divider
add wave /testbench_busybear/dut/uncore/HSELBootTim
add wave /testbench_busybear/dut/uncore/HSELTim
add wave /testbench_busybear/dut/uncore/HREADTim
add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYTim
add wave -divider
add wave /testbench_busybear/dut/uncore/HREADBootTim
add wave /testbench_busybear/dut/uncore/bootdtim/HREADTim0
add wave /testbench_busybear/dut/uncore/HREADYBootTim
add wave /testbench_busybear/dut/uncore/HADDR
add wave /testbench_busybear/dut/uncore/HRESP
add wave /testbench_busybear/dut/uncore/HREADY
add wave /testbench_busybear/dut/uncore/HRDATA
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG
#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG
@ -140,7 +148,7 @@ add wave /testbench_busybear/InstrWName
#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW
#add wave -divider
##add ww
#add wave -hex -r /testbench_busybear/*
add wave -hex -r /testbench_busybear/*
#
#-- Set Wave Output Items
#TreeUpdate [SetDefaultTree]

10
wally-pipelined/src/uncore/imem.sv
View File

@ -32,16 +32,16 @@ module imem (
output logic InstrAccessFaultF);
/* verilator lint_off UNDRIVEN */
logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE-`TIMBASE)>>(1+`XLEN/32)];
logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE-`BOOTTIMBASE)>>(1+`XLEN/32)];
logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
/* verilator lint_on UNDRIVEN */
logic [15:0] adrbits;
logic [28:0] adrbits;
logic [`XLEN-1:0] rd;
// logic [15:0] rd2;
generate
if (`XLEN==32) assign adrbits = AdrF[17:2];
else assign adrbits = AdrF[18:3];
if (`XLEN==32) assign adrbits = AdrF[30:2];
else assign adrbits = AdrF[31:3];
endgenerate
//assign #2 rd = RAM[adrbits]; // word aligned

12
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -204,9 +204,10 @@ module testbench_busybear();
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change
always @(HWDATA or HADDR or HSIZE or HWRITE) begin
#1;
if (HWRITE) begin
//always @(HWDATA or HADDR or HSIZE or HWRITE) begin
always @(negedge HWRITE) begin
//#1;
if ($time != 0) begin
if($feof(data_file_memW)) begin
$display("no more memW data to read");
`ERROR
@ -337,7 +338,9 @@ module testbench_busybear();
logic forcedInstr;
logic [63:0] lastPCF;
always @(dut.PCF or dut.hart.ifu.InstrF) begin
if (~reset && dut.hart.ifu.InstrF !== {32{1'bx}}) begin
if(~HWRITE) begin
#3;
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}}) begin
if (dut.PCF !== lastPCF) begin
lastCheckInstrF = CheckInstrF;
lastPC <= dut.PCF;
@ -416,6 +419,7 @@ module testbench_busybear();
end
lastPCF = dut.PCF;
end
end
end
// Track names of instructions