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ALU cleanup

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This commit is contained in:
David Harris 2022-12-24 07:18:35 -08:00
parent 56af142e7d
commit 921b5582da
2 changed files with 3 additions and 5 deletions
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7
pipelined/src/ieu/alu.sv
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@ -41,12 +41,11 @@ module alu #(parameter WIDTH=32) (
logic Carry, Neg; logic Carry, Neg;
logic LT, LTU; logic LT, LTU;
logic W64, SubArith, ALUOp; logic W64, SubArith, ALUOp;
logic [2:0] ALUFunct;
logic Asign, Bsign; logic Asign, Bsign;
// Extract control signals // Extract control signals
// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
// SubArith indicates subtraction // SubArith indicates subtraction or arithmetic right shift
// ALUOp = 0 for address generation addition or 1 for regular ALU // ALUOp = 0 for address generation addition or 1 for regular ALU
assign {W64, SubArith, ALUOp} = ALUControl; assign {W64, SubArith, ALUOp} = ALUControl;
@ -71,9 +70,9 @@ module alu #(parameter WIDTH=32) (
assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
// Select appropriate ALU Result // Select appropriate ALU Result
assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
always_comb always_comb
casez (ALUFunct) if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0
else casez (Funct3) // Otherwise check Funct3
3'b000: FullResult = Sum; // add or sub 3'b000: FullResult = Sum; // add or sub
3'b?01: FullResult = Shift; // sll, sra, or srl 3'b?01: FullResult = Shift; // sll, sra, or srl
3'b010: FullResult = SLT; // slt 3'b010: FullResult = SLT; // slt

1
pipelined/src/ieu/controller.sv
View File

@ -161,7 +161,6 @@ module controller(
ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
else else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
//7'b1010011: ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal