Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/generic/flop/bram2p1r1w.sv

@@ -78,8 +78,8 @@ module bram2p1r1w
   end
  -----/\----- EXCLUDED -----/\----- */
 
-  initial begin
+  if(PRELOAD_ENABLED) begin
-	if(PRELOAD_ENABLED) begin
+    initial begin
       RAM[0] =  64'h9581819300002197; 
       RAM[1] =  64'h4281420141014081; 
       RAM[2] =  64'h4481440143814301; 

pipelined/src/uncore/ram.sv

@@ -43,6 +43,12 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   output logic             HRESPRam, HREADYRam
 );
 
+  // Desired changes.
+  // 1. find a way to merge read and write address into 1 port.
+  // 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.)
+  // 3. implement burst.
+  // 4. remove the configurable latency.
+
   logic [`XLEN/8-1:0] 		  ByteMaskM;
   logic [31:0]        HWADDR, A;
   logic				  prevHREADYRam, risingHREADYRam;

pipelined/src/uncore/uartPC16550D.sv

@@ -310,7 +310,7 @@ module uartPC16550D(
           if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
         end else begin
           rxdataready <= #1 0;
-          RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
+          RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
         end
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register
         if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents