diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv
index 057c8766b..e66c22da2 100644
--- a/src/mmu/tlb/tlbcamline.sv
+++ b/src/mmu/tlb/tlbcamline.sv
@@ -41,7 +41,7 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
   input  logic                  PTE_NAPOT,  // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
   input  logic [1:0]            PageTypeWriteVal,
   input  logic                  TLBFlush,   // Flush this line (set valid to 0)
-  output logic [1:0]            PageTypeRead,  // *** should this be the stored version or the always updated one?
+  output logic [1:0]            PageTypeRead,  
   output logic                  Match
 );
 
@@ -102,8 +102,6 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
 
   // On a write, set the valid bit high and update the stored key.
   // On a flush, zero the valid bit and leave the key unchanged.
-  // *** Might we want to update stored key right away to output match on the
-  // write cycle? (using a mux)
   flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
   flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
 endmodule
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index e992ee526..d8ce0e709 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -95,11 +95,13 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   assign CounterEvent[1]    = 1'b0;                                                      // Counter 1 doesn't exist
   assign CounterEvent[2]    = InstrValidNotFlushedM;                                     // MINSTRET instructions retired
   if (P.ZIHPM_SUPPORTED) begin: cevent                                                   // User-defined counters
-    assign CounterEvent[3]  = IClassM[0] & InstrValidNotFlushedM;                    // branch instruction
-    assign CounterEvent[4]  = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM;  // jump and not return instructions
-    assign CounterEvent[5]  = IClassM[2] & InstrValidNotFlushedM;                    // return instructions
+    // Ideally all events would be counted in the M stage, but the pipelining is costly. The counters may
+    // count an event in a previous pipeline stage.
+    assign CounterEvent[3]  = IClassM[0] & InstrValidNotFlushedM;                        // branch instruction
+    assign CounterEvent[4]  = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM;          // jump and not return instructions
+    assign CounterEvent[5]  = IClassM[2] & InstrValidNotFlushedM;                        // return instructions
     assign CounterEvent[6]  = BPWrongM & InstrValidNotFlushedM;                          // branch predictor wrong
-    assign CounterEvent[7]  = BPDirWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
+    assign CounterEvent[7]  = BPDirWrongM & InstrValidNotFlushedM;                       // Branch predictor wrong direction
     assign CounterEvent[8]  = BTAWrongM & InstrValidNotFlushedM;                         // branch predictor wrong target
     assign CounterEvent[9]  = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
@@ -117,8 +119,8 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     assign CounterEvent[22] = InterruptM;                                                // interrupt, InstrValidNotFlushedM will be low
     assign CounterEvent[23] = ExceptionM;                                                // exceptions, InstrValidNotFlushedM will be low
     // coverage off
-    // DivBusyE will never be assert high since this configuration uses the FPU to do integer division
-    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles *** RT: might need to be delay until the next cycle
+    // DivBusyE will never be asserted high because the RV64GC configuration uses the FPU to do integer division
+    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles
     // coverage on
     assign CounterEvent[P.COUNTERS-1:25] = '0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end else begin: cevent