diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv
index 17591abe3..18752ed6c 100644
--- a/wally-pipelined/src/cache/DCacheMem.sv
+++ b/wally-pipelined/src/cache/DCacheMem.sv
@@ -30,7 +30,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
    input logic 			      reset,
 
    input logic [$clog2(NUMLINES)-1:0] Adr,
-   input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only
    input logic 			      WriteEnable,
    input logic [BLOCKLEN/`XLEN-1:0]   WriteWordEnable,
    input logic TagWriteEnable,
@@ -76,16 +75,16 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
   always_ff @(posedge clk, posedge reset) begin
     if (reset) 
   	ValidBits <= {NUMLINES{1'b0}};
-    else if (SetValid & WriteEnable) ValidBits[WAdr] <= 1'b1;
-    else if (ClearValid & WriteEnable) ValidBits[WAdr] <= 1'b0;
+    else if (SetValid & WriteEnable) ValidBits[Adr] <= 1'b1;
+    else if (ClearValid & WriteEnable) ValidBits[Adr] <= 1'b0;
     Valid <= ValidBits[Adr];
   end
 
   always_ff @(posedge clk, posedge reset) begin
     if (reset) 
   	DirtyBits <= {NUMLINES{1'b0}};
-    else if (SetDirty & WriteEnable) DirtyBits[WAdr] <= 1'b1;
-    else if (ClearDirty & WriteEnable) DirtyBits[WAdr] <= 1'b0;
+    else if (SetDirty & WriteEnable) DirtyBits[Adr] <= 1'b1;
+    else if (ClearDirty & WriteEnable) DirtyBits[Adr] <= 1'b0;
     Dirty <= DirtyBits[Adr];
   end
   
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index ec8e7f44e..d1dd34d75 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -212,7 +212,6 @@ module dcache
       MemWay(.clk(clk),
 	     .reset(reset),
 	     .Adr(SRAMAdr),
-	     .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	     .WriteEnable(SRAMWayWriteEnable[way]),
 	     .WriteWordEnable(SRAMWordEnable),
 	     .TagWriteEnable(SRAMBlockWayWriteEnableM[way]), 
@@ -709,7 +708,7 @@ module dcache
 	SelAdrM = 2'b01;
 	CommittedM = 1'b1;
 	SelEvict = 1'b1;
-	if( FetchCountFlag & AHBAck) begin
+	if(FetchCountFlag & AHBAck) begin
 	  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
 	end else begin
 	  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
@@ -988,7 +987,7 @@ module dcache
 	SelAdrM = 2'b01;
 	CommittedM = 1'b1;
 	SelEvict = 1'b1;
-	if( FetchCountFlag & AHBAck) begin
+	if(FetchCountFlag & AHBAck) begin
 	  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
 	end else begin
 	  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;