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generic cleanup

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This commit is contained in:
David Harris 2023-01-14 19:02:38 -08:00
parent 9c79078be1
commit 91afe5522b
4 changed files with 43 additions and 43 deletions
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75
pipelined/src/ebu/ahbcacheinterface.sv
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@ -30,51 +30,52 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) (
( input logic HCLK, HRESETn,
input logic HCLK, HRESETn,
// bus interface // bus interface
input logic HREADY, input logic HREADY,
input logic [`AHBW-1:0] HRDATA, input logic [`AHBW-1:0] HRDATA,
output logic [2:0] HSIZE, output logic [2:0] HSIZE,
output logic [2:0] HBURST, output logic [2:0] HBURST,
output logic [1:0] HTRANS, output logic [1:0] HTRANS,
output logic HWRITE, output logic HWRITE,
output logic [`PA_BITS-1:0] HADDR, output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA, output logic [`AHBW-1:0] HWDATA,
output logic [`AHBW/8-1:0] HWSTRB, output logic [`AHBW/8-1:0] HWSTRB,
output logic [LOGWPL-1:0] BeatCount, output logic [LOGWPL-1:0] BeatCount,
// cache interface // cache interface
input logic [`PA_BITS-1:0] CacheBusAdr, input logic [`PA_BITS-1:0] CacheBusAdr,
input logic [`LLEN-1:0] CacheReadDataWordM, input logic [`LLEN-1:0] CacheReadDataWordM,
input logic [`LLEN-1:0] WriteDataM, input logic [`LLEN-1:0] WriteDataM,
input logic CacheableOrFlushCacheM, input logic CacheableOrFlushCacheM,
input logic [1:0] CacheBusRW, input logic [1:0] CacheBusRW,
output logic CacheBusAck, output logic CacheBusAck,
output logic [LINELEN-1:0] FetchBuffer, output logic [LINELEN-1:0] FetchBuffer,
input logic Cacheable, input logic Cacheable,
// lsu/ifu interface // lsu/ifu interface
input logic Flush, input logic Flush,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [1:0] BusRW, input logic [1:0] BusRW,
input logic Stall, input logic Stall,
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusBeat, output logic SelBusBeat,
output logic BusStall, output logic BusStall,
output logic BusCommitted); output logic BusCommitted
);
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu. localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
logic [`PA_BITS-1:0] LocalHADDR; logic [`PA_BITS-1:0] LocalHADDR;
logic [LOGWPL-1:0] BeatCountDelayed; logic [LOGWPL-1:0] BeatCountDelayed;
logic CaptureEn; logic CaptureEn;
logic [`AHBW-1:0] PreHWDATA; logic [`AHBW-1:0] PreHWDATA;
genvar index; genvar index;
// fetch buffer is made of BEATSPERLINE flip-flops
for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
logic [BEATSPERLINE-1:0] CaptureBeat; logic [BEATSPERLINE-1:0] CaptureBeat;
assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);

1
pipelined/src/generic/mux.sv
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@ -27,7 +27,6 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_off DECLFILENAME */ /* verilator lint_off DECLFILENAME */
module mux2 #(parameter WIDTH = 8) ( module mux2 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, input logic [WIDTH-1:0] d0, d1,
input logic s, input logic s,

1
pipelined/src/generic/priorityonehot.sv
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@ -41,6 +41,7 @@ module priorityonehot #(parameter N = 8) (
); );
genvar i; genvar i;
assign y[0] = a[0]; assign y[0] = a[0];
for (i=1; i<N; i++) begin:poh for (i=1; i<N; i++) begin:poh
assign y[i] = a[i] & ~|a[i-1:0]; assign y[i] = a[i] & ~|a[i-1:0];

9
pipelined/src/generic/prioritythermometer.sv
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@ -31,24 +31,23 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_off UNOPTFLAT */
module prioritythermometer #(parameter N = 8) ( module prioritythermometer #(parameter N = 8) (
input logic [N-1:0] a, input logic [N-1:0] a,
output logic [N-1:0] y output logic [N-1:0] y
); );
// Carefully crafted so design compiler will synthesize into a fast tree structure // Carefully crafted so design compiler will synthesize into a fast tree structure
// Rather than linear. // Rather than linear.
// create thermometer code mask // create thermometer code mask
/* verilator lint_off UNOPTFLAT */
genvar i; genvar i;
assign y[0] = ~a[0]; assign y[0] = ~a[0];
for (i=1; i<N; i++) begin:therm for (i=1; i<N; i++) begin:therm
assign y[i] = y[i-1] & ~a[i]; assign y[i] = y[i-1] & ~a[i];
end end
/* verilator lint_on UNOPTFLAT */
endmodule endmodule
/* verilator lint_on UNOPTFLAT */