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Update sim/verilator/Makefile with more comments and merging variables.

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This commit is contained in:
Kunlin Han 2024-04-17 09:52:54 -07:00
parent 392eedb342
commit 91a88fa46c
1 changed files with 8 additions and 4 deletions
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12
sim/verilator/Makefile
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@ -9,11 +9,15 @@ WALLYCONF?=rv64gc
TEST?=arch64i TEST?=arch64i
# constants # constants
# assume WALLY variable is correctly configured in the shell environment
WORKING_DIR=${WALLY}/sim/verilator WORKING_DIR=${WALLY}/sim/verilator
TARGET=$(WORKING_DIR)/target TARGET=$(WORKING_DIR)/target
DEPENDENCIES=${WALLY}/config/shared/*.vh ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv # INCLUDE_PATH are pathes that Verilator should search for files it needs
INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)" INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
SOURCE_PATH=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv # SOURCES are source files
SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
default: run default: run
@ -40,7 +44,7 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
$(INCLUDE_PATH) \ $(INCLUDE_PATH) \
wrapper.c \ wrapper.c \
$(SOURCE_PATH) $(SOURCES)
obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES) obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
mkdir -p obj_dir_profiling mkdir -p obj_dir_profiling
@ -51,7 +55,7 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \ --timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
$(INCLUDE_PATH) \ $(INCLUDE_PATH) \
wrapper.c \ wrapper.c \
$(SOURCE_PATH) $(SOURCES)
questa: questa:
time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"